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12#include "qemu/osdep.h"
13#include "qemu-common.h"
14#include "cpu.h"
15#include "hw/i386/apic_internal.h"
16#include "hw/pci/msi.h"
17#include "sysemu/kvm.h"
18
19static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,
20 int reg_id, uint32_t val)
21{
22 *((uint32_t *)(kapic->regs + (reg_id << 4))) = val;
23}
24
25static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic,
26 int reg_id)
27{
28 return *((uint32_t *)(kapic->regs + (reg_id << 4)));
29}
30
31void kvm_put_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic)
32{
33 APICCommonState *s = APIC_COMMON(dev);
34 int i;
35
36 memset(kapic, 0, sizeof(*kapic));
37 kvm_apic_set_reg(kapic, 0x2, s->id << 24);
38 kvm_apic_set_reg(kapic, 0x8, s->tpr);
39 kvm_apic_set_reg(kapic, 0xd, s->log_dest << 24);
40 kvm_apic_set_reg(kapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
41 kvm_apic_set_reg(kapic, 0xf, s->spurious_vec);
42 for (i = 0; i < 8; i++) {
43 kvm_apic_set_reg(kapic, 0x10 + i, s->isr[i]);
44 kvm_apic_set_reg(kapic, 0x18 + i, s->tmr[i]);
45 kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]);
46 }
47 kvm_apic_set_reg(kapic, 0x28, s->esr);
48 kvm_apic_set_reg(kapic, 0x30, s->icr[0]);
49 kvm_apic_set_reg(kapic, 0x31, s->icr[1]);
50 for (i = 0; i < APIC_LVT_NB; i++) {
51 kvm_apic_set_reg(kapic, 0x32 + i, s->lvt[i]);
52 }
53 kvm_apic_set_reg(kapic, 0x38, s->initial_count);
54 kvm_apic_set_reg(kapic, 0x3e, s->divide_conf);
55}
56
57void kvm_get_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic)
58{
59 APICCommonState *s = APIC_COMMON(dev);
60 int i, v;
61
62 s->id = kvm_apic_get_reg(kapic, 0x2) >> 24;
63 s->tpr = kvm_apic_get_reg(kapic, 0x8);
64 s->arb_id = kvm_apic_get_reg(kapic, 0x9);
65 s->log_dest = kvm_apic_get_reg(kapic, 0xd) >> 24;
66 s->dest_mode = kvm_apic_get_reg(kapic, 0xe) >> 28;
67 s->spurious_vec = kvm_apic_get_reg(kapic, 0xf);
68 for (i = 0; i < 8; i++) {
69 s->isr[i] = kvm_apic_get_reg(kapic, 0x10 + i);
70 s->tmr[i] = kvm_apic_get_reg(kapic, 0x18 + i);
71 s->irr[i] = kvm_apic_get_reg(kapic, 0x20 + i);
72 }
73 s->esr = kvm_apic_get_reg(kapic, 0x28);
74 s->icr[0] = kvm_apic_get_reg(kapic, 0x30);
75 s->icr[1] = kvm_apic_get_reg(kapic, 0x31);
76 for (i = 0; i < APIC_LVT_NB; i++) {
77 s->lvt[i] = kvm_apic_get_reg(kapic, 0x32 + i);
78 }
79 s->initial_count = kvm_apic_get_reg(kapic, 0x38);
80 s->divide_conf = kvm_apic_get_reg(kapic, 0x3e);
81
82 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
83 s->count_shift = (v + 1) & 7;
84
85 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
86 apic_next_timer(s, s->initial_count_load_time);
87}
88
89static void kvm_apic_set_base(APICCommonState *s, uint64_t val)
90{
91 s->apicbase = val;
92}
93
94static void kvm_apic_set_tpr(APICCommonState *s, uint8_t val)
95{
96 s->tpr = (val & 0x0f) << 4;
97}
98
99static uint8_t kvm_apic_get_tpr(APICCommonState *s)
100{
101 return s->tpr >> 4;
102}
103
104static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable)
105{
106 struct kvm_tpr_access_ctl ctl = {
107 .enabled = enable
108 };
109
110 kvm_vcpu_ioctl(CPU(s->cpu), KVM_TPR_ACCESS_REPORTING, &ctl);
111}
112
113static void kvm_apic_vapic_base_update(APICCommonState *s)
114{
115 struct kvm_vapic_addr vapid_addr = {
116 .vapic_addr = s->vapic_paddr,
117 };
118 int ret;
119
120 ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_VAPIC_ADDR, &vapid_addr);
121 if (ret < 0) {
122 fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n",
123 strerror(-ret));
124 abort();
125 }
126}
127
128static void do_inject_external_nmi(void *data)
129{
130 APICCommonState *s = data;
131 CPUState *cpu = CPU(s->cpu);
132 uint32_t lvt;
133 int ret;
134
135 cpu_synchronize_state(cpu);
136
137 lvt = s->lvt[APIC_LVT_LINT1];
138 if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) {
139 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
140 if (ret < 0) {
141 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
142 strerror(-ret));
143 }
144 }
145}
146
147static void kvm_apic_external_nmi(APICCommonState *s)
148{
149 run_on_cpu(CPU(s->cpu), do_inject_external_nmi, s);
150}
151
152static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr,
153 unsigned size)
154{
155 return ~(uint64_t)0;
156}
157
158static void kvm_apic_mem_write(void *opaque, hwaddr addr,
159 uint64_t data, unsigned size)
160{
161 MSIMessage msg = { .address = addr, .data = data };
162 int ret;
163
164 ret = kvm_irqchip_send_msi(kvm_state, msg);
165 if (ret < 0) {
166 fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n",
167 strerror(-ret));
168 }
169}
170
171static const MemoryRegionOps kvm_apic_io_ops = {
172 .read = kvm_apic_mem_read,
173 .write = kvm_apic_mem_write,
174 .endianness = DEVICE_NATIVE_ENDIAN,
175};
176
177static void kvm_apic_reset(APICCommonState *s)
178{
179
180 s->wait_for_sipi = 0;
181}
182
183static void kvm_apic_realize(DeviceState *dev, Error **errp)
184{
185 APICCommonState *s = APIC_COMMON(dev);
186
187 memory_region_init_io(&s->io_memory, OBJECT(s), &kvm_apic_io_ops, s,
188 "kvm-apic-msi", APIC_SPACE_SIZE);
189
190 if (kvm_has_gsi_routing()) {
191 msi_nonbroken = true;
192 }
193}
194
195static void kvm_apic_unrealize(DeviceState *dev, Error **errp)
196{
197}
198
199static void kvm_apic_class_init(ObjectClass *klass, void *data)
200{
201 APICCommonClass *k = APIC_COMMON_CLASS(klass);
202
203 k->realize = kvm_apic_realize;
204 k->unrealize = kvm_apic_unrealize;
205 k->reset = kvm_apic_reset;
206 k->set_base = kvm_apic_set_base;
207 k->set_tpr = kvm_apic_set_tpr;
208 k->get_tpr = kvm_apic_get_tpr;
209 k->enable_tpr_reporting = kvm_apic_enable_tpr_reporting;
210 k->vapic_base_update = kvm_apic_vapic_base_update;
211 k->external_nmi = kvm_apic_external_nmi;
212}
213
214static const TypeInfo kvm_apic_info = {
215 .name = "kvm-apic",
216 .parent = TYPE_APIC_COMMON,
217 .instance_size = sizeof(APICCommonState),
218 .class_init = kvm_apic_class_init,
219};
220
221static void kvm_apic_register_types(void)
222{
223 type_register_static(&kvm_apic_info);
224}
225
226type_init(kvm_apic_register_types)
227
