1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#include "qemu/osdep.h"
20#include "qemu-common.h"
21#include "cpu.h"
22#include "qemu/thread.h"
23#include "hw/i386/apic_internal.h"
24#include "hw/i386/apic.h"
25#include "hw/i386/ioapic.h"
26#include "hw/pci/msi.h"
27#include "qemu/host-utils.h"
28#include "trace.h"
29#include "hw/i386/pc.h"
30#include "hw/i386/apic-msidef.h"
31#include "qapi/error.h"
32
33#define MAX_APICS 255
34#define MAX_APIC_WORDS 8
35
36#define SYNC_FROM_VAPIC 0x1
37#define SYNC_TO_VAPIC 0x2
38#define SYNC_ISR_IRR_TO_VAPIC 0x4
39
40static APICCommonState *local_apics[MAX_APICS + 1];
41
42static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode);
43static void apic_update_irq(APICCommonState *s);
44static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
45 uint8_t dest, uint8_t dest_mode);
46
47
48static int apic_fls_bit(uint32_t value)
49{
50 return 31 - clz32(value);
51}
52
53
54static int apic_ffs_bit(uint32_t value)
55{
56 return ctz32(value);
57}
58
59static inline void apic_reset_bit(uint32_t *tab, int index)
60{
61 int i, mask;
62 i = index >> 5;
63 mask = 1 << (index & 0x1f);
64 tab[i] &= ~mask;
65}
66
67
68static int get_highest_priority_int(uint32_t *tab)
69{
70 int i;
71 for (i = 7; i >= 0; i--) {
72 if (tab[i] != 0) {
73 return i * 32 + apic_fls_bit(tab[i]);
74 }
75 }
76 return -1;
77}
78
79static void apic_sync_vapic(APICCommonState *s, int sync_type)
80{
81 VAPICState vapic_state;
82 size_t length;
83 off_t start;
84 int vector;
85
86 if (!s->vapic_paddr) {
87 return;
88 }
89 if (sync_type & SYNC_FROM_VAPIC) {
90 cpu_physical_memory_read(s->vapic_paddr, &vapic_state,
91 sizeof(vapic_state));
92 s->tpr = vapic_state.tpr;
93 }
94 if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) {
95 start = offsetof(VAPICState, isr);
96 length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);
97
98 if (sync_type & SYNC_TO_VAPIC) {
99 assert(qemu_cpu_is_self(CPU(s->cpu)));
100
101 vapic_state.tpr = s->tpr;
102 vapic_state.enabled = 1;
103 start = 0;
104 length = sizeof(VAPICState);
105 }
106
107 vector = get_highest_priority_int(s->isr);
108 if (vector < 0) {
109 vector = 0;
110 }
111 vapic_state.isr = vector & 0xf0;
112
113 vapic_state.zero = 0;
114
115 vector = get_highest_priority_int(s->irr);
116 if (vector < 0) {
117 vector = 0;
118 }
119 vapic_state.irr = vector & 0xff;
120
121 cpu_physical_memory_write_rom(&address_space_memory,
122 s->vapic_paddr + start,
123 ((void *)&vapic_state) + start, length);
124 }
125}
126
127static void apic_vapic_base_update(APICCommonState *s)
128{
129 apic_sync_vapic(s, SYNC_TO_VAPIC);
130}
131
132static void apic_local_deliver(APICCommonState *s, int vector)
133{
134 uint32_t lvt = s->lvt[vector];
135 int trigger_mode;
136
137 trace_apic_local_deliver(vector, (lvt >> 8) & 7);
138
139 if (lvt & APIC_LVT_MASKED)
140 return;
141
142 switch ((lvt >> 8) & 7) {
143 case APIC_DM_SMI:
144 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI);
145 break;
146
147 case APIC_DM_NMI:
148 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI);
149 break;
150
151 case APIC_DM_EXTINT:
152 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
153 break;
154
155 case APIC_DM_FIXED:
156 trigger_mode = APIC_TRIGGER_EDGE;
157 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
158 (lvt & APIC_LVT_LEVEL_TRIGGER))
159 trigger_mode = APIC_TRIGGER_LEVEL;
160 apic_set_irq(s, lvt & 0xff, trigger_mode);
161 }
162}
163
164void apic_deliver_pic_intr(DeviceState *dev, int level)
165{
166 APICCommonState *s = APIC_COMMON(dev);
167
168 if (level) {
169 apic_local_deliver(s, APIC_LVT_LINT0);
170 } else {
171 uint32_t lvt = s->lvt[APIC_LVT_LINT0];
172
173 switch ((lvt >> 8) & 7) {
174 case APIC_DM_FIXED:
175 if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
176 break;
177 apic_reset_bit(s->irr, lvt & 0xff);
178
179 case APIC_DM_EXTINT:
180 apic_update_irq(s);
181 break;
182 }
183 }
184}
185
186static void apic_external_nmi(APICCommonState *s)
187{
188 apic_local_deliver(s, APIC_LVT_LINT1);
189}
190
191#define foreach_apic(apic, deliver_bitmask, code) \
192{\
193 int __i, __j;\
194 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
195 uint32_t __mask = deliver_bitmask[__i];\
196 if (__mask) {\
197 for(__j = 0; __j < 32; __j++) {\
198 if (__mask & (1U << __j)) {\
199 apic = local_apics[__i * 32 + __j];\
200 if (apic) {\
201 code;\
202 }\
203 }\
204 }\
205 }\
206 }\
207}
208
209static void apic_bus_deliver(const uint32_t *deliver_bitmask,
210 uint8_t delivery_mode, uint8_t vector_num,
211 uint8_t trigger_mode)
212{
213 APICCommonState *apic_iter;
214
215 switch (delivery_mode) {
216 case APIC_DM_LOWPRI:
217
218 {
219 int i, d;
220 d = -1;
221 for(i = 0; i < MAX_APIC_WORDS; i++) {
222 if (deliver_bitmask[i]) {
223 d = i * 32 + apic_ffs_bit(deliver_bitmask[i]);
224 break;
225 }
226 }
227 if (d >= 0) {
228 apic_iter = local_apics[d];
229 if (apic_iter) {
230 apic_set_irq(apic_iter, vector_num, trigger_mode);
231 }
232 }
233 }
234 return;
235
236 case APIC_DM_FIXED:
237 break;
238
239 case APIC_DM_SMI:
240 foreach_apic(apic_iter, deliver_bitmask,
241 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI)
242 );
243 return;
244
245 case APIC_DM_NMI:
246 foreach_apic(apic_iter, deliver_bitmask,
247 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI)
248 );
249 return;
250
251 case APIC_DM_INIT:
252
253 foreach_apic(apic_iter, deliver_bitmask,
254 cpu_interrupt(CPU(apic_iter->cpu),
255 CPU_INTERRUPT_INIT)
256 );
257 return;
258
259 case APIC_DM_EXTINT:
260
261 break;
262
263 default:
264 return;
265 }
266
267 foreach_apic(apic_iter, deliver_bitmask,
268 apic_set_irq(apic_iter, vector_num, trigger_mode) );
269}
270
271void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
272 uint8_t vector_num, uint8_t trigger_mode)
273{
274 uint32_t deliver_bitmask[MAX_APIC_WORDS];
275
276 trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
277 trigger_mode);
278
279 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
280 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
281}
282
283static void apic_set_base(APICCommonState *s, uint64_t val)
284{
285 s->apicbase = (val & 0xfffff000) |
286 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
287
288 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
289 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
290 cpu_clear_apic_feature(&s->cpu->env);
291 s->spurious_vec &= ~APIC_SV_ENABLE;
292 }
293}
294
295static void apic_set_tpr(APICCommonState *s, uint8_t val)
296{
297
298 if (!s->vapic_paddr) {
299 s->tpr = val << 4;
300 apic_update_irq(s);
301 }
302}
303
304static uint8_t apic_get_tpr(APICCommonState *s)
305{
306 apic_sync_vapic(s, SYNC_FROM_VAPIC);
307 return s->tpr >> 4;
308}
309
310int apic_get_ppr(APICCommonState *s)
311{
312 int tpr, isrv, ppr;
313
314 tpr = (s->tpr >> 4);
315 isrv = get_highest_priority_int(s->isr);
316 if (isrv < 0)
317 isrv = 0;
318 isrv >>= 4;
319 if (tpr >= isrv)
320 ppr = s->tpr;
321 else
322 ppr = isrv << 4;
323 return ppr;
324}
325
326static int apic_get_arb_pri(APICCommonState *s)
327{
328
329 return 0;
330}
331
332
333
334
335
336
337
338static int apic_irq_pending(APICCommonState *s)
339{
340 int irrv, ppr;
341
342 if (!(s->spurious_vec & APIC_SV_ENABLE)) {
343 return 0;
344 }
345
346 irrv = get_highest_priority_int(s->irr);
347 if (irrv < 0) {
348 return 0;
349 }
350 ppr = apic_get_ppr(s);
351 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
352 return -1;
353 }
354
355 return irrv;
356}
357
358
359static void apic_update_irq(APICCommonState *s)
360{
361 CPUState *cpu;
362 DeviceState *dev = (DeviceState *)s;
363
364 cpu = CPU(s->cpu);
365 if (!qemu_cpu_is_self(cpu)) {
366 cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
367 } else if (apic_irq_pending(s) > 0) {
368 cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
369 } else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
370 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
371 }
372}
373
374void apic_poll_irq(DeviceState *dev)
375{
376 APICCommonState *s = APIC_COMMON(dev);
377
378 apic_sync_vapic(s, SYNC_FROM_VAPIC);
379 apic_update_irq(s);
380}
381
382static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
383{
384 apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
385
386 apic_set_bit(s->irr, vector_num);
387 if (trigger_mode)
388 apic_set_bit(s->tmr, vector_num);
389 else
390 apic_reset_bit(s->tmr, vector_num);
391 if (s->vapic_paddr) {
392 apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC);
393
394
395
396
397
398 smp_wmb();
399 apic_sync_vapic(s, SYNC_FROM_VAPIC);
400 }
401 apic_update_irq(s);
402}
403
404static void apic_eoi(APICCommonState *s)
405{
406 int isrv;
407 isrv = get_highest_priority_int(s->isr);
408 if (isrv < 0)
409 return;
410 apic_reset_bit(s->isr, isrv);
411 if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) {
412 ioapic_eoi_broadcast(isrv);
413 }
414 apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC);
415 apic_update_irq(s);
416}
417
418static int apic_find_dest(uint8_t dest)
419{
420 APICCommonState *apic = local_apics[dest];
421 int i;
422
423 if (apic && apic->id == dest)
424 return dest;
425
426 for (i = 0; i < MAX_APICS; i++) {
427 apic = local_apics[i];
428 if (apic && apic->id == dest)
429 return i;
430 if (!apic)
431 break;
432 }
433
434 return -1;
435}
436
437static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
438 uint8_t dest, uint8_t dest_mode)
439{
440 APICCommonState *apic_iter;
441 int i;
442
443 if (dest_mode == 0) {
444 if (dest == 0xff) {
445 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
446 } else {
447 int idx = apic_find_dest(dest);
448 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
449 if (idx >= 0)
450 apic_set_bit(deliver_bitmask, idx);
451 }
452 } else {
453
454 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
455 for(i = 0; i < MAX_APICS; i++) {
456 apic_iter = local_apics[i];
457 if (apic_iter) {
458 if (apic_iter->dest_mode == 0xf) {
459 if (dest & apic_iter->log_dest)
460 apic_set_bit(deliver_bitmask, i);
461 } else if (apic_iter->dest_mode == 0x0) {
462 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
463 (dest & apic_iter->log_dest & 0x0f)) {
464 apic_set_bit(deliver_bitmask, i);
465 }
466 }
467 } else {
468 break;
469 }
470 }
471 }
472}
473
474static void apic_startup(APICCommonState *s, int vector_num)
475{
476 s->sipi_vector = vector_num;
477 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
478}
479
480void apic_sipi(DeviceState *dev)
481{
482 APICCommonState *s = APIC_COMMON(dev);
483
484 cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
485
486 if (!s->wait_for_sipi)
487 return;
488 cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector);
489 s->wait_for_sipi = 0;
490}
491
492static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode,
493 uint8_t delivery_mode, uint8_t vector_num,
494 uint8_t trigger_mode)
495{
496 APICCommonState *s = APIC_COMMON(dev);
497 uint32_t deliver_bitmask[MAX_APIC_WORDS];
498 int dest_shorthand = (s->icr[0] >> 18) & 3;
499 APICCommonState *apic_iter;
500
501 switch (dest_shorthand) {
502 case 0:
503 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
504 break;
505 case 1:
506 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
507 apic_set_bit(deliver_bitmask, s->id);
508 break;
509 case 2:
510 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
511 break;
512 case 3:
513 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
514 apic_reset_bit(deliver_bitmask, s->id);
515 break;
516 }
517
518 switch (delivery_mode) {
519 case APIC_DM_INIT:
520 {
521 int trig_mode = (s->icr[0] >> 15) & 1;
522 int level = (s->icr[0] >> 14) & 1;
523 if (level == 0 && trig_mode == 1) {
524 foreach_apic(apic_iter, deliver_bitmask,
525 apic_iter->arb_id = apic_iter->id );
526 return;
527 }
528 }
529 break;
530
531 case APIC_DM_SIPI:
532 foreach_apic(apic_iter, deliver_bitmask,
533 apic_startup(apic_iter, vector_num) );
534 return;
535 }
536
537 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
538}
539
540static bool apic_check_pic(APICCommonState *s)
541{
542 DeviceState *dev = (DeviceState *)s;
543
544 if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
545 return false;
546 }
547 apic_deliver_pic_intr(dev, 1);
548 return true;
549}
550
551int apic_get_interrupt(DeviceState *dev)
552{
553 APICCommonState *s = APIC_COMMON(dev);
554 int intno;
555
556
557
558 if (!s)
559 return -1;
560 if (!(s->spurious_vec & APIC_SV_ENABLE))
561 return -1;
562
563 apic_sync_vapic(s, SYNC_FROM_VAPIC);
564 intno = apic_irq_pending(s);
565
566
567
568
569 if (intno == 0 || apic_check_pic(s)) {
570 apic_sync_vapic(s, SYNC_TO_VAPIC);
571 return -1;
572 } else if (intno < 0) {
573 apic_sync_vapic(s, SYNC_TO_VAPIC);
574 return s->spurious_vec & 0xff;
575 }
576 apic_reset_bit(s->irr, intno);
577 apic_set_bit(s->isr, intno);
578 apic_sync_vapic(s, SYNC_TO_VAPIC);
579
580 apic_update_irq(s);
581
582 return intno;
583}
584
585int apic_accept_pic_intr(DeviceState *dev)
586{
587 APICCommonState *s = APIC_COMMON(dev);
588 uint32_t lvt0;
589
590 if (!s)
591 return -1;
592
593 lvt0 = s->lvt[APIC_LVT_LINT0];
594
595 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
596 (lvt0 & APIC_LVT_MASKED) == 0)
597 return 1;
598
599 return 0;
600}
601
602static uint32_t apic_get_current_count(APICCommonState *s)
603{
604 int64_t d;
605 uint32_t val;
606 d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >>
607 s->count_shift;
608 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
609
610 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
611 } else {
612 if (d >= s->initial_count)
613 val = 0;
614 else
615 val = s->initial_count - d;
616 }
617 return val;
618}
619
620static void apic_timer_update(APICCommonState *s, int64_t current_time)
621{
622 if (apic_next_timer(s, current_time)) {
623 timer_mod(s->timer, s->next_time);
624 } else {
625 timer_del(s->timer);
626 }
627}
628
629static void apic_timer(void *opaque)
630{
631 APICCommonState *s = opaque;
632
633 apic_local_deliver(s, APIC_LVT_TIMER);
634 apic_timer_update(s, s->next_time);
635}
636
637static uint32_t apic_mem_readb(void *opaque, hwaddr addr)
638{
639 return 0;
640}
641
642static uint32_t apic_mem_readw(void *opaque, hwaddr addr)
643{
644 return 0;
645}
646
647static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
648{
649}
650
651static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val)
652{
653}
654
655static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
656{
657 DeviceState *dev;
658 APICCommonState *s;
659 uint32_t val;
660 int index;
661
662 dev = cpu_get_current_apic();
663 if (!dev) {
664 return 0;
665 }
666 s = APIC_COMMON(dev);
667
668 index = (addr >> 4) & 0xff;
669 switch(index) {
670 case 0x02:
671 val = s->id << 24;
672 break;
673 case 0x03:
674 val = s->version | ((APIC_LVT_NB - 1) << 16);
675 break;
676 case 0x08:
677 apic_sync_vapic(s, SYNC_FROM_VAPIC);
678 if (apic_report_tpr_access) {
679 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ);
680 }
681 val = s->tpr;
682 break;
683 case 0x09:
684 val = apic_get_arb_pri(s);
685 break;
686 case 0x0a:
687
688 val = apic_get_ppr(s);
689 break;
690 case 0x0b:
691 val = 0;
692 break;
693 case 0x0d:
694 val = s->log_dest << 24;
695 break;
696 case 0x0e:
697 val = (s->dest_mode << 28) | 0xfffffff;
698 break;
699 case 0x0f:
700 val = s->spurious_vec;
701 break;
702 case 0x10 ... 0x17:
703 val = s->isr[index & 7];
704 break;
705 case 0x18 ... 0x1f:
706 val = s->tmr[index & 7];
707 break;
708 case 0x20 ... 0x27:
709 val = s->irr[index & 7];
710 break;
711 case 0x28:
712 val = s->esr;
713 break;
714 case 0x30:
715 case 0x31:
716 val = s->icr[index & 1];
717 break;
718 case 0x32 ... 0x37:
719 val = s->lvt[index - 0x32];
720 break;
721 case 0x38:
722 val = s->initial_count;
723 break;
724 case 0x39:
725 val = apic_get_current_count(s);
726 break;
727 case 0x3e:
728 val = s->divide_conf;
729 break;
730 default:
731 s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
732 val = 0;
733 break;
734 }
735 trace_apic_mem_readl(addr, val);
736 return val;
737}
738
739static void apic_send_msi(hwaddr addr, uint32_t data)
740{
741 uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
742 uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
743 uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
744 uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
745 uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
746
747 apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
748}
749
750static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
751{
752 DeviceState *dev;
753 APICCommonState *s;
754 int index = (addr >> 4) & 0xff;
755 if (addr > 0xfff || !index) {
756
757
758
759
760
761 apic_send_msi(addr, val);
762 return;
763 }
764
765 dev = cpu_get_current_apic();
766 if (!dev) {
767 return;
768 }
769 s = APIC_COMMON(dev);
770
771 trace_apic_mem_writel(addr, val);
772
773 switch(index) {
774 case 0x02:
775 s->id = (val >> 24);
776 break;
777 case 0x03:
778 break;
779 case 0x08:
780 if (apic_report_tpr_access) {
781 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE);
782 }
783 s->tpr = val;
784 apic_sync_vapic(s, SYNC_TO_VAPIC);
785 apic_update_irq(s);
786 break;
787 case 0x09:
788 case 0x0a:
789 break;
790 case 0x0b:
791 apic_eoi(s);
792 break;
793 case 0x0d:
794 s->log_dest = val >> 24;
795 break;
796 case 0x0e:
797 s->dest_mode = val >> 28;
798 break;
799 case 0x0f:
800 s->spurious_vec = val & 0x1ff;
801 apic_update_irq(s);
802 break;
803 case 0x10 ... 0x17:
804 case 0x18 ... 0x1f:
805 case 0x20 ... 0x27:
806 case 0x28:
807 break;
808 case 0x30:
809 s->icr[0] = val;
810 apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
811 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
812 (s->icr[0] >> 15) & 1);
813 break;
814 case 0x31:
815 s->icr[1] = val;
816 break;
817 case 0x32 ... 0x37:
818 {
819 int n = index - 0x32;
820 s->lvt[n] = val;
821 if (n == APIC_LVT_TIMER) {
822 apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
823 } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) {
824 apic_update_irq(s);
825 }
826 }
827 break;
828 case 0x38:
829 s->initial_count = val;
830 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
831 apic_timer_update(s, s->initial_count_load_time);
832 break;
833 case 0x39:
834 break;
835 case 0x3e:
836 {
837 int v;
838 s->divide_conf = val & 0xb;
839 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
840 s->count_shift = (v + 1) & 7;
841 }
842 break;
843 default:
844 s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
845 break;
846 }
847}
848
849static void apic_pre_save(APICCommonState *s)
850{
851 apic_sync_vapic(s, SYNC_FROM_VAPIC);
852}
853
854static void apic_post_load(APICCommonState *s)
855{
856 if (s->timer_expiry != -1) {
857 timer_mod(s->timer, s->timer_expiry);
858 } else {
859 timer_del(s->timer);
860 }
861}
862
863static const MemoryRegionOps apic_io_ops = {
864 .old_mmio = {
865 .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
866 .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
867 },
868 .endianness = DEVICE_NATIVE_ENDIAN,
869};
870
871static void apic_realize(DeviceState *dev, Error **errp)
872{
873 APICCommonState *s = APIC_COMMON(dev);
874
875 if (s->id >= MAX_APICS) {
876 error_setg(errp, "%s initialization failed. APIC ID %d is invalid",
877 object_get_typename(OBJECT(dev)), s->id);
878 return;
879 }
880
881 memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi",
882 APIC_SPACE_SIZE);
883
884 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s);
885 local_apics[s->id] = s;
886
887 msi_nonbroken = true;
888}
889
890static void apic_unrealize(DeviceState *dev, Error **errp)
891{
892 APICCommonState *s = APIC_COMMON(dev);
893
894 timer_del(s->timer);
895 timer_free(s->timer);
896 local_apics[s->id] = NULL;
897}
898
899static void apic_class_init(ObjectClass *klass, void *data)
900{
901 APICCommonClass *k = APIC_COMMON_CLASS(klass);
902
903 k->realize = apic_realize;
904 k->unrealize = apic_unrealize;
905 k->set_base = apic_set_base;
906 k->set_tpr = apic_set_tpr;
907 k->get_tpr = apic_get_tpr;
908 k->vapic_base_update = apic_vapic_base_update;
909 k->external_nmi = apic_external_nmi;
910 k->pre_save = apic_pre_save;
911 k->post_load = apic_post_load;
912}
913
914static const TypeInfo apic_info = {
915 .name = "apic",
916 .instance_size = sizeof(APICCommonState),
917 .parent = TYPE_APIC_COMMON,
918 .class_init = apic_class_init,
919};
920
921static void apic_register_types(void)
922{
923 type_register_static(&apic_info);
924}
925
926type_init(apic_register_types)
927