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20#include "qemu/osdep.h"
21#include "qapi/error.h"
22#include "qemu-common.h"
23#include "cpu.h"
24#include "hw/i386/apic.h"
25#include "hw/i386/apic_internal.h"
26#include "trace.h"
27#include "sysemu/kvm.h"
28#include "hw/qdev.h"
29#include "hw/sysbus.h"
30
31static int apic_irq_delivered;
32bool apic_report_tpr_access;
33
34void cpu_set_apic_base(DeviceState *dev, uint64_t val)
35{
36 trace_cpu_set_apic_base(val);
37
38 if (dev) {
39 APICCommonState *s = APIC_COMMON(dev);
40 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
41 info->set_base(s, val);
42 }
43}
44
45uint64_t cpu_get_apic_base(DeviceState *dev)
46{
47 if (dev) {
48 APICCommonState *s = APIC_COMMON(dev);
49 trace_cpu_get_apic_base((uint64_t)s->apicbase);
50 return s->apicbase;
51 } else {
52 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
53 return MSR_IA32_APICBASE_BSP;
54 }
55}
56
57void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
58{
59 APICCommonState *s;
60 APICCommonClass *info;
61
62 if (!dev) {
63 return;
64 }
65
66 s = APIC_COMMON(dev);
67 info = APIC_COMMON_GET_CLASS(s);
68
69 info->set_tpr(s, val);
70}
71
72uint8_t cpu_get_apic_tpr(DeviceState *dev)
73{
74 APICCommonState *s;
75 APICCommonClass *info;
76
77 if (!dev) {
78 return 0;
79 }
80
81 s = APIC_COMMON(dev);
82 info = APIC_COMMON_GET_CLASS(s);
83
84 return info->get_tpr(s);
85}
86
87void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
88{
89 APICCommonState *s = APIC_COMMON(dev);
90 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
91
92 apic_report_tpr_access = enable;
93 if (info->enable_tpr_reporting) {
94 info->enable_tpr_reporting(s, enable);
95 }
96}
97
98void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
99{
100 APICCommonState *s = APIC_COMMON(dev);
101 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
102
103 s->vapic_paddr = paddr;
104 info->vapic_base_update(s);
105}
106
107void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
108 TPRAccess access)
109{
110 APICCommonState *s = APIC_COMMON(dev);
111
112 vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
113}
114
115void apic_report_irq_delivered(int delivered)
116{
117 apic_irq_delivered += delivered;
118
119 trace_apic_report_irq_delivered(apic_irq_delivered);
120}
121
122void apic_reset_irq_delivered(void)
123{
124
125
126
127
128 volatile int a_i_d = apic_irq_delivered;
129 trace_apic_reset_irq_delivered(a_i_d);
130
131 apic_irq_delivered = 0;
132}
133
134int apic_get_irq_delivered(void)
135{
136 trace_apic_get_irq_delivered(apic_irq_delivered);
137
138 return apic_irq_delivered;
139}
140
141void apic_deliver_nmi(DeviceState *dev)
142{
143 APICCommonState *s = APIC_COMMON(dev);
144 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
145
146 info->external_nmi(s);
147}
148
149bool apic_next_timer(APICCommonState *s, int64_t current_time)
150{
151 int64_t d;
152
153
154
155
156
157 s->timer_expiry = -1;
158
159 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
160 return false;
161 }
162
163 d = (current_time - s->initial_count_load_time) >> s->count_shift;
164
165 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
166 if (!s->initial_count) {
167 return false;
168 }
169 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
170 ((uint64_t)s->initial_count + 1);
171 } else {
172 if (d >= s->initial_count) {
173 return false;
174 }
175 d = (uint64_t)s->initial_count + 1;
176 }
177 s->next_time = s->initial_count_load_time + (d << s->count_shift);
178 s->timer_expiry = s->next_time;
179 return true;
180}
181
182void apic_init_reset(DeviceState *dev)
183{
184 APICCommonState *s;
185 APICCommonClass *info;
186 int i;
187
188 if (!dev) {
189 return;
190 }
191 s = APIC_COMMON(dev);
192 s->tpr = 0;
193 s->spurious_vec = 0xff;
194 s->log_dest = 0;
195 s->dest_mode = 0xf;
196 memset(s->isr, 0, sizeof(s->isr));
197 memset(s->tmr, 0, sizeof(s->tmr));
198 memset(s->irr, 0, sizeof(s->irr));
199 for (i = 0; i < APIC_LVT_NB; i++) {
200 s->lvt[i] = APIC_LVT_MASKED;
201 }
202 s->esr = 0;
203 memset(s->icr, 0, sizeof(s->icr));
204 s->divide_conf = 0;
205 s->count_shift = 0;
206 s->initial_count = 0;
207 s->initial_count_load_time = 0;
208 s->next_time = 0;
209 s->wait_for_sipi = !cpu_is_bsp(s->cpu);
210
211 if (s->timer) {
212 timer_del(s->timer);
213 }
214 s->timer_expiry = -1;
215
216 info = APIC_COMMON_GET_CLASS(s);
217 if (info->reset) {
218 info->reset(s);
219 }
220}
221
222void apic_designate_bsp(DeviceState *dev, bool bsp)
223{
224 if (dev == NULL) {
225 return;
226 }
227
228 APICCommonState *s = APIC_COMMON(dev);
229 if (bsp) {
230 s->apicbase |= MSR_IA32_APICBASE_BSP;
231 } else {
232 s->apicbase &= ~MSR_IA32_APICBASE_BSP;
233 }
234}
235
236static void apic_reset_common(DeviceState *dev)
237{
238 APICCommonState *s = APIC_COMMON(dev);
239 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
240 uint32_t bsp;
241
242 bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
243 s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
244
245 s->vapic_paddr = 0;
246 info->vapic_base_update(s);
247
248 apic_init_reset(dev);
249}
250
251
252static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
253{
254 APICCommonState *s = opaque;
255 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
256 int i;
257
258 if (version_id > 2) {
259 return -EINVAL;
260 }
261
262
263 qemu_get_be32s(f, &s->apicbase);
264 qemu_get_8s(f, &s->id);
265 qemu_get_8s(f, &s->arb_id);
266 qemu_get_8s(f, &s->tpr);
267 qemu_get_be32s(f, &s->spurious_vec);
268 qemu_get_8s(f, &s->log_dest);
269 qemu_get_8s(f, &s->dest_mode);
270 for (i = 0; i < 8; i++) {
271 qemu_get_be32s(f, &s->isr[i]);
272 qemu_get_be32s(f, &s->tmr[i]);
273 qemu_get_be32s(f, &s->irr[i]);
274 }
275 for (i = 0; i < APIC_LVT_NB; i++) {
276 qemu_get_be32s(f, &s->lvt[i]);
277 }
278 qemu_get_be32s(f, &s->esr);
279 qemu_get_be32s(f, &s->icr[0]);
280 qemu_get_be32s(f, &s->icr[1]);
281 qemu_get_be32s(f, &s->divide_conf);
282 s->count_shift = qemu_get_be32(f);
283 qemu_get_be32s(f, &s->initial_count);
284 s->initial_count_load_time = qemu_get_be64(f);
285 s->next_time = qemu_get_be64(f);
286
287 if (version_id >= 2) {
288 s->timer_expiry = qemu_get_be64(f);
289 }
290
291 if (info->post_load) {
292 info->post_load(s);
293 }
294 return 0;
295}
296
297static const VMStateDescription vmstate_apic_common;
298
299static void apic_common_realize(DeviceState *dev, Error **errp)
300{
301 APICCommonState *s = APIC_COMMON(dev);
302 APICCommonClass *info;
303 static DeviceState *vapic;
304 int instance_id = s->id;
305
306 info = APIC_COMMON_GET_CLASS(s);
307 info->realize(dev, errp);
308
309
310 if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
311 ram_size >= 1024 * 1024) {
312 vapic = sysbus_create_simple("kvmvapic", -1, NULL);
313 }
314 s->vapic = vapic;
315 if (apic_report_tpr_access && info->enable_tpr_reporting) {
316 info->enable_tpr_reporting(s, true);
317 }
318
319 if (s->legacy_instance_id) {
320 instance_id = -1;
321 }
322 vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,
323 s, -1, 0);
324}
325
326static void apic_common_unrealize(DeviceState *dev, Error **errp)
327{
328 APICCommonState *s = APIC_COMMON(dev);
329 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
330
331 vmstate_unregister(NULL, &vmstate_apic_common, s);
332 info->unrealize(dev, errp);
333
334 if (apic_report_tpr_access && info->enable_tpr_reporting) {
335 info->enable_tpr_reporting(s, false);
336 }
337}
338
339static int apic_pre_load(void *opaque)
340{
341 APICCommonState *s = APIC_COMMON(opaque);
342
343
344
345
346
347
348 s->wait_for_sipi = 0;
349 return 0;
350}
351
352static void apic_dispatch_pre_save(void *opaque)
353{
354 APICCommonState *s = APIC_COMMON(opaque);
355 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
356
357 if (info->pre_save) {
358 info->pre_save(s);
359 }
360}
361
362static int apic_dispatch_post_load(void *opaque, int version_id)
363{
364 APICCommonState *s = APIC_COMMON(opaque);
365 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
366
367 if (info->post_load) {
368 info->post_load(s);
369 }
370 return 0;
371}
372
373static bool apic_common_sipi_needed(void *opaque)
374{
375 APICCommonState *s = APIC_COMMON(opaque);
376 return s->wait_for_sipi != 0;
377}
378
379static const VMStateDescription vmstate_apic_common_sipi = {
380 .name = "apic_sipi",
381 .version_id = 1,
382 .minimum_version_id = 1,
383 .needed = apic_common_sipi_needed,
384 .fields = (VMStateField[]) {
385 VMSTATE_INT32(sipi_vector, APICCommonState),
386 VMSTATE_INT32(wait_for_sipi, APICCommonState),
387 VMSTATE_END_OF_LIST()
388 }
389};
390
391static const VMStateDescription vmstate_apic_common = {
392 .name = "apic",
393 .version_id = 3,
394 .minimum_version_id = 3,
395 .minimum_version_id_old = 1,
396 .load_state_old = apic_load_old,
397 .pre_load = apic_pre_load,
398 .pre_save = apic_dispatch_pre_save,
399 .post_load = apic_dispatch_post_load,
400 .fields = (VMStateField[]) {
401 VMSTATE_UINT32(apicbase, APICCommonState),
402 VMSTATE_UINT8(id, APICCommonState),
403 VMSTATE_UINT8(arb_id, APICCommonState),
404 VMSTATE_UINT8(tpr, APICCommonState),
405 VMSTATE_UINT32(spurious_vec, APICCommonState),
406 VMSTATE_UINT8(log_dest, APICCommonState),
407 VMSTATE_UINT8(dest_mode, APICCommonState),
408 VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
409 VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
410 VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
411 VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
412 VMSTATE_UINT32(esr, APICCommonState),
413 VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
414 VMSTATE_UINT32(divide_conf, APICCommonState),
415 VMSTATE_INT32(count_shift, APICCommonState),
416 VMSTATE_UINT32(initial_count, APICCommonState),
417 VMSTATE_INT64(initial_count_load_time, APICCommonState),
418 VMSTATE_INT64(next_time, APICCommonState),
419 VMSTATE_INT64(timer_expiry,
420 APICCommonState),
421 VMSTATE_END_OF_LIST()
422 },
423 .subsections = (const VMStateDescription*[]) {
424 &vmstate_apic_common_sipi,
425 NULL
426 }
427};
428
429static Property apic_properties_common[] = {
430 DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
431 DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
432 DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
433 true),
434 DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
435 false),
436 DEFINE_PROP_END_OF_LIST(),
437};
438
439static void apic_common_class_init(ObjectClass *klass, void *data)
440{
441 DeviceClass *dc = DEVICE_CLASS(klass);
442
443 dc->reset = apic_reset_common;
444 dc->props = apic_properties_common;
445 dc->realize = apic_common_realize;
446 dc->unrealize = apic_common_unrealize;
447
448
449
450
451 dc->cannot_instantiate_with_device_add_yet = true;
452}
453
454static const TypeInfo apic_common_type = {
455 .name = TYPE_APIC_COMMON,
456 .parent = TYPE_DEVICE,
457 .instance_size = sizeof(APICCommonState),
458 .class_size = sizeof(APICCommonClass),
459 .class_init = apic_common_class_init,
460 .abstract = true,
461};
462
463static void apic_common_register_types(void)
464{
465 type_register_static(&apic_common_type);
466}
467
468type_init(apic_common_register_types)
469
