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19#include "qemu/osdep.h"
20#include "qemu/error-report.h"
21#include "hw/hw.h"
22#include "qemu/log.h"
23#include "sysemu/kvm.h"
24#include "hw/qdev.h"
25#include "kvm_ppc.h"
26#include "sysemu/dma.h"
27#include "exec/address-spaces.h"
28#include "trace.h"
29
30#include "hw/ppc/spapr.h"
31#include "hw/ppc/spapr_vio.h"
32
33#include <libfdt.h>
34
35enum sPAPRTCEAccess {
36 SPAPR_TCE_FAULT = 0,
37 SPAPR_TCE_RO = 1,
38 SPAPR_TCE_WO = 2,
39 SPAPR_TCE_RW = 3,
40};
41
42#define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
43#define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
44
45static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables;
46
47sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn)
48{
49 sPAPRTCETable *tcet;
50
51 if (liobn & 0xFFFFFFFF00000000ULL) {
52 hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
53 liobn);
54 return NULL;
55 }
56
57 QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
58 if (tcet->liobn == (uint32_t)liobn) {
59 return tcet;
60 }
61 }
62
63 return NULL;
64}
65
66static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
67{
68 switch (tce & SPAPR_TCE_RW) {
69 case SPAPR_TCE_FAULT:
70 return IOMMU_NONE;
71 case SPAPR_TCE_RO:
72 return IOMMU_RO;
73 case SPAPR_TCE_WO:
74 return IOMMU_WO;
75 default:
76 return IOMMU_RW;
77 }
78}
79
80static uint64_t *spapr_tce_alloc_table(uint32_t liobn,
81 uint32_t page_shift,
82 uint32_t nb_table,
83 int *fd,
84 bool need_vfio)
85{
86 uint64_t *table = NULL;
87 uint64_t window_size = (uint64_t)nb_table << page_shift;
88
89 if (kvm_enabled() && !(window_size >> 32)) {
90 table = kvmppc_create_spapr_tce(liobn, window_size, fd, need_vfio);
91 }
92
93 if (!table) {
94 *fd = -1;
95 table = g_malloc0(nb_table * sizeof(uint64_t));
96 }
97
98 trace_spapr_iommu_new_table(liobn, table, *fd);
99
100 return table;
101}
102
103static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table)
104{
105 if (!kvm_enabled() ||
106 (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) {
107 g_free(table);
108 }
109}
110
111
112static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr addr,
113 bool is_write)
114{
115 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
116 uint64_t tce;
117 IOMMUTLBEntry ret = {
118 .target_as = &address_space_memory,
119 .iova = 0,
120 .translated_addr = 0,
121 .addr_mask = ~(hwaddr)0,
122 .perm = IOMMU_NONE,
123 };
124
125 if ((addr >> tcet->page_shift) < tcet->nb_table) {
126
127 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
128
129 tce = tcet->table[addr >> tcet->page_shift];
130 ret.iova = addr & page_mask;
131 ret.translated_addr = tce & page_mask;
132 ret.addr_mask = ~page_mask;
133 ret.perm = spapr_tce_iommu_access_flags(tce);
134 }
135 trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm,
136 ret.addr_mask);
137
138 return ret;
139}
140
141static void spapr_tce_table_pre_save(void *opaque)
142{
143 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
144
145 tcet->mig_table = tcet->table;
146 tcet->mig_nb_table = tcet->nb_table;
147
148 trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table,
149 tcet->bus_offset, tcet->page_shift);
150}
151
152static uint64_t spapr_tce_get_min_page_size(MemoryRegion *iommu)
153{
154 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
155
156 return 1ULL << tcet->page_shift;
157}
158
159static void spapr_tce_notify_started(MemoryRegion *iommu)
160{
161 spapr_tce_set_need_vfio(container_of(iommu, sPAPRTCETable, iommu), true);
162}
163
164static void spapr_tce_notify_stopped(MemoryRegion *iommu)
165{
166 spapr_tce_set_need_vfio(container_of(iommu, sPAPRTCETable, iommu), false);
167}
168
169static int spapr_tce_table_post_load(void *opaque, int version_id)
170{
171 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
172 uint32_t old_nb_table = tcet->nb_table;
173 uint64_t old_bus_offset = tcet->bus_offset;
174 uint32_t old_page_shift = tcet->page_shift;
175
176 if (tcet->vdev) {
177 spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
178 }
179
180 if (tcet->mig_nb_table != tcet->nb_table) {
181 spapr_tce_table_disable(tcet);
182 }
183
184 if (tcet->mig_nb_table) {
185 if (!tcet->nb_table) {
186 spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset,
187 tcet->mig_nb_table);
188 }
189
190 memcpy(tcet->table, tcet->mig_table,
191 tcet->nb_table * sizeof(tcet->table[0]));
192
193 free(tcet->mig_table);
194 tcet->mig_table = NULL;
195 }
196
197 trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table,
198 tcet->bus_offset, tcet->page_shift);
199
200 return 0;
201}
202
203static bool spapr_tce_table_ex_needed(void *opaque)
204{
205 sPAPRTCETable *tcet = opaque;
206
207 return tcet->bus_offset || tcet->page_shift != 0xC;
208}
209
210static const VMStateDescription vmstate_spapr_tce_table_ex = {
211 .name = "spapr_iommu_ex",
212 .version_id = 1,
213 .minimum_version_id = 1,
214 .needed = spapr_tce_table_ex_needed,
215 .fields = (VMStateField[]) {
216 VMSTATE_UINT64(bus_offset, sPAPRTCETable),
217 VMSTATE_UINT32(page_shift, sPAPRTCETable),
218 VMSTATE_END_OF_LIST()
219 },
220};
221
222static const VMStateDescription vmstate_spapr_tce_table = {
223 .name = "spapr_iommu",
224 .version_id = 2,
225 .minimum_version_id = 2,
226 .pre_save = spapr_tce_table_pre_save,
227 .post_load = spapr_tce_table_post_load,
228 .fields = (VMStateField []) {
229
230 VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable),
231
232
233 VMSTATE_UINT32(mig_nb_table, sPAPRTCETable),
234 VMSTATE_BOOL(bypass, sPAPRTCETable),
235 VMSTATE_VARRAY_UINT32_ALLOC(mig_table, sPAPRTCETable, mig_nb_table, 0,
236 vmstate_info_uint64, uint64_t),
237
238 VMSTATE_END_OF_LIST()
239 },
240 .subsections = (const VMStateDescription*[]) {
241 &vmstate_spapr_tce_table_ex,
242 NULL
243 }
244};
245
246static MemoryRegionIOMMUOps spapr_iommu_ops = {
247 .translate = spapr_tce_translate_iommu,
248 .get_min_page_size = spapr_tce_get_min_page_size,
249 .notify_started = spapr_tce_notify_started,
250 .notify_stopped = spapr_tce_notify_stopped,
251};
252
253static int spapr_tce_table_realize(DeviceState *dev)
254{
255 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
256 Object *tcetobj = OBJECT(tcet);
257 char tmp[32];
258
259 tcet->fd = -1;
260 tcet->need_vfio = false;
261 snprintf(tmp, sizeof(tmp), "tce-root-%x", tcet->liobn);
262 memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX);
263
264 snprintf(tmp, sizeof(tmp), "tce-iommu-%x", tcet->liobn);
265 memory_region_init_iommu(&tcet->iommu, tcetobj, &spapr_iommu_ops, tmp, 0);
266
267 QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
268
269 vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
270 tcet);
271
272 return 0;
273}
274
275void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio)
276{
277 size_t table_size = tcet->nb_table * sizeof(uint64_t);
278 void *newtable;
279
280 if (need_vfio == tcet->need_vfio) {
281
282 return;
283 }
284
285 if (!need_vfio) {
286
287
288 return;
289 }
290
291 tcet->need_vfio = true;
292
293 if (tcet->fd < 0) {
294
295 return;
296 }
297
298 newtable = g_malloc(table_size);
299 memcpy(newtable, tcet->table, table_size);
300
301 kvmppc_remove_spapr_tce(tcet->table, tcet->fd, tcet->nb_table);
302
303 tcet->fd = -1;
304 tcet->table = newtable;
305}
306
307sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
308{
309 sPAPRTCETable *tcet;
310 char tmp[32];
311
312 if (spapr_tce_find_by_liobn(liobn)) {
313 fprintf(stderr, "Attempted to create TCE table with duplicate"
314 " LIOBN 0x%x\n", liobn);
315 return NULL;
316 }
317
318 tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
319 tcet->liobn = liobn;
320
321 snprintf(tmp, sizeof(tmp), "tce-table-%x", liobn);
322 object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
323
324 object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
325
326 return tcet;
327}
328
329void spapr_tce_table_enable(sPAPRTCETable *tcet,
330 uint32_t page_shift, uint64_t bus_offset,
331 uint32_t nb_table)
332{
333 if (tcet->nb_table) {
334 error_report("Warning: trying to enable already enabled TCE table");
335 return;
336 }
337
338 tcet->bus_offset = bus_offset;
339 tcet->page_shift = page_shift;
340 tcet->nb_table = nb_table;
341 tcet->table = spapr_tce_alloc_table(tcet->liobn,
342 tcet->page_shift,
343 tcet->nb_table,
344 &tcet->fd,
345 tcet->need_vfio);
346
347 memory_region_set_size(&tcet->iommu,
348 (uint64_t)tcet->nb_table << tcet->page_shift);
349 memory_region_add_subregion(&tcet->root, tcet->bus_offset, &tcet->iommu);
350}
351
352void spapr_tce_table_disable(sPAPRTCETable *tcet)
353{
354 if (!tcet->nb_table) {
355 return;
356 }
357
358 memory_region_del_subregion(&tcet->root, &tcet->iommu);
359 memory_region_set_size(&tcet->iommu, 0);
360
361 spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table);
362 tcet->fd = -1;
363 tcet->table = NULL;
364 tcet->bus_offset = 0;
365 tcet->page_shift = 0;
366 tcet->nb_table = 0;
367}
368
369static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
370{
371 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
372
373 QLIST_REMOVE(tcet, list);
374
375 spapr_tce_table_disable(tcet);
376}
377
378MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet)
379{
380 return &tcet->root;
381}
382
383static void spapr_tce_reset(DeviceState *dev)
384{
385 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
386 size_t table_size = tcet->nb_table * sizeof(uint64_t);
387
388 if (tcet->nb_table) {
389 memset(tcet->table, 0, table_size);
390 }
391}
392
393static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
394 target_ulong tce)
395{
396 IOMMUTLBEntry entry;
397 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
398 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
399
400 if (index >= tcet->nb_table) {
401 hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
402 TARGET_FMT_lx "\n", ioba);
403 return H_PARAMETER;
404 }
405
406 tcet->table[index] = tce;
407
408 entry.target_as = &address_space_memory,
409 entry.iova = (ioba - tcet->bus_offset) & page_mask;
410 entry.translated_addr = tce & page_mask;
411 entry.addr_mask = ~page_mask;
412 entry.perm = spapr_tce_iommu_access_flags(tce);
413 memory_region_notify_iommu(&tcet->iommu, entry);
414
415 return H_SUCCESS;
416}
417
418static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
419 sPAPRMachineState *spapr,
420 target_ulong opcode, target_ulong *args)
421{
422 int i;
423 target_ulong liobn = args[0];
424 target_ulong ioba = args[1];
425 target_ulong ioba1 = ioba;
426 target_ulong tce_list = args[2];
427 target_ulong npages = args[3];
428 target_ulong ret = H_PARAMETER, tce = 0;
429 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
430 CPUState *cs = CPU(cpu);
431 hwaddr page_mask, page_size;
432
433 if (!tcet) {
434 return H_PARAMETER;
435 }
436
437 if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
438 return H_PARAMETER;
439 }
440
441 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
442 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
443 ioba &= page_mask;
444
445 for (i = 0; i < npages; ++i, ioba += page_size) {
446 tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
447
448 ret = put_tce_emu(tcet, ioba, tce);
449 if (ret) {
450 break;
451 }
452 }
453
454
455 i = i ? (i - 1) : 0;
456 if (SPAPR_IS_PCI_LIOBN(liobn)) {
457 trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
458 } else {
459 trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
460 }
461 return ret;
462}
463
464static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
465 target_ulong opcode, target_ulong *args)
466{
467 int i;
468 target_ulong liobn = args[0];
469 target_ulong ioba = args[1];
470 target_ulong tce_value = args[2];
471 target_ulong npages = args[3];
472 target_ulong ret = H_PARAMETER;
473 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
474 hwaddr page_mask, page_size;
475
476 if (!tcet) {
477 return H_PARAMETER;
478 }
479
480 if (npages > tcet->nb_table) {
481 return H_PARAMETER;
482 }
483
484 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
485 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
486 ioba &= page_mask;
487
488 for (i = 0; i < npages; ++i, ioba += page_size) {
489 ret = put_tce_emu(tcet, ioba, tce_value);
490 if (ret) {
491 break;
492 }
493 }
494 if (SPAPR_IS_PCI_LIOBN(liobn)) {
495 trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
496 } else {
497 trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
498 }
499
500 return ret;
501}
502
503static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
504 target_ulong opcode, target_ulong *args)
505{
506 target_ulong liobn = args[0];
507 target_ulong ioba = args[1];
508 target_ulong tce = args[2];
509 target_ulong ret = H_PARAMETER;
510 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
511
512 if (tcet) {
513 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
514
515 ioba &= page_mask;
516
517 ret = put_tce_emu(tcet, ioba, tce);
518 }
519 if (SPAPR_IS_PCI_LIOBN(liobn)) {
520 trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
521 } else {
522 trace_spapr_iommu_put(liobn, ioba, tce, ret);
523 }
524
525 return ret;
526}
527
528static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
529 target_ulong *tce)
530{
531 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
532
533 if (index >= tcet->nb_table) {
534 hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
535 TARGET_FMT_lx "\n", ioba);
536 return H_PARAMETER;
537 }
538
539 *tce = tcet->table[index];
540
541 return H_SUCCESS;
542}
543
544static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
545 target_ulong opcode, target_ulong *args)
546{
547 target_ulong liobn = args[0];
548 target_ulong ioba = args[1];
549 target_ulong tce = 0;
550 target_ulong ret = H_PARAMETER;
551 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
552
553 if (tcet) {
554 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
555
556 ioba &= page_mask;
557
558 ret = get_tce_emu(tcet, ioba, &tce);
559 if (!ret) {
560 args[0] = tce;
561 }
562 }
563 if (SPAPR_IS_PCI_LIOBN(liobn)) {
564 trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
565 } else {
566 trace_spapr_iommu_get(liobn, ioba, ret, tce);
567 }
568
569 return ret;
570}
571
572int spapr_dma_dt(void *fdt, int node_off, const char *propname,
573 uint32_t liobn, uint64_t window, uint32_t size)
574{
575 uint32_t dma_prop[5];
576 int ret;
577
578 dma_prop[0] = cpu_to_be32(liobn);
579 dma_prop[1] = cpu_to_be32(window >> 32);
580 dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
581 dma_prop[3] = 0;
582 dma_prop[4] = cpu_to_be32(size);
583
584 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
585 if (ret < 0) {
586 return ret;
587 }
588
589 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
590 if (ret < 0) {
591 return ret;
592 }
593
594 ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
595 if (ret < 0) {
596 return ret;
597 }
598
599 return 0;
600}
601
602int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
603 sPAPRTCETable *tcet)
604{
605 if (!tcet) {
606 return 0;
607 }
608
609 return spapr_dma_dt(fdt, node_off, propname,
610 tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
611}
612
613static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
614{
615 DeviceClass *dc = DEVICE_CLASS(klass);
616 dc->init = spapr_tce_table_realize;
617 dc->reset = spapr_tce_reset;
618 dc->unrealize = spapr_tce_table_unrealize;
619
620 QLIST_INIT(&spapr_tce_tables);
621
622
623 spapr_register_hypercall(H_PUT_TCE, h_put_tce);
624 spapr_register_hypercall(H_GET_TCE, h_get_tce);
625 spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
626 spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
627}
628
629static TypeInfo spapr_tce_table_info = {
630 .name = TYPE_SPAPR_TCE_TABLE,
631 .parent = TYPE_DEVICE,
632 .instance_size = sizeof(sPAPRTCETable),
633 .class_init = spapr_tce_table_class_init,
634};
635
636static void register_types(void)
637{
638 type_register_static(&spapr_tce_table_info);
639}
640
641type_init(register_types);
642