qemu/hw/scsi/megasas.c
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   1/*
   2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
   3 * Based on the linux driver code at drivers/scsi/megaraid
   4 *
   5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "hw/hw.h"
  23#include "hw/pci/pci.h"
  24#include "sysemu/dma.h"
  25#include "sysemu/block-backend.h"
  26#include "hw/pci/msi.h"
  27#include "hw/pci/msix.h"
  28#include "qemu/iov.h"
  29#include "hw/scsi/scsi.h"
  30#include "block/scsi.h"
  31#include "trace.h"
  32#include "qapi/error.h"
  33#include "mfi.h"
  34
  35#define MEGASAS_VERSION_GEN1 "1.70"
  36#define MEGASAS_VERSION_GEN2 "1.80"
  37#define MEGASAS_MAX_FRAMES 2048         /* Firmware limit at 65535 */
  38#define MEGASAS_DEFAULT_FRAMES 1000     /* Windows requires this */
  39#define MEGASAS_GEN2_DEFAULT_FRAMES 1008     /* Windows requires this */
  40#define MEGASAS_MAX_SGE 128             /* Firmware limit */
  41#define MEGASAS_DEFAULT_SGE 80
  42#define MEGASAS_MAX_SECTORS 0xFFFF      /* No real limit */
  43#define MEGASAS_MAX_ARRAYS 128
  44
  45#define MEGASAS_HBA_SERIAL "QEMU123456"
  46#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
  47#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
  48
  49#define MEGASAS_FLAG_USE_JBOD      0
  50#define MEGASAS_MASK_USE_JBOD      (1 << MEGASAS_FLAG_USE_JBOD)
  51#define MEGASAS_FLAG_USE_QUEUE64   1
  52#define MEGASAS_MASK_USE_QUEUE64   (1 << MEGASAS_FLAG_USE_QUEUE64)
  53
  54static const char *mfi_frame_desc[] = {
  55    "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
  56    "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
  57
  58typedef struct MegasasCmd {
  59    uint32_t index;
  60    uint16_t flags;
  61    uint16_t count;
  62    uint64_t context;
  63
  64    hwaddr pa;
  65    hwaddr pa_size;
  66    union mfi_frame *frame;
  67    SCSIRequest *req;
  68    QEMUSGList qsg;
  69    void *iov_buf;
  70    size_t iov_size;
  71    size_t iov_offset;
  72    struct MegasasState *state;
  73} MegasasCmd;
  74
  75typedef struct MegasasState {
  76    /*< private >*/
  77    PCIDevice parent_obj;
  78    /*< public >*/
  79
  80    MemoryRegion mmio_io;
  81    MemoryRegion port_io;
  82    MemoryRegion queue_io;
  83    uint32_t frame_hi;
  84
  85    int fw_state;
  86    uint32_t fw_sge;
  87    uint32_t fw_cmds;
  88    uint32_t flags;
  89    int fw_luns;
  90    int intr_mask;
  91    int doorbell;
  92    int busy;
  93    int diag;
  94    int adp_reset;
  95    OnOffAuto msi;
  96    OnOffAuto msix;
  97
  98    MegasasCmd *event_cmd;
  99    int event_locale;
 100    int event_class;
 101    int event_count;
 102    int shutdown_event;
 103    int boot_event;
 104
 105    uint64_t sas_addr;
 106    char *hba_serial;
 107
 108    uint64_t reply_queue_pa;
 109    void *reply_queue;
 110    int reply_queue_len;
 111    int reply_queue_head;
 112    int reply_queue_tail;
 113    uint64_t consumer_pa;
 114    uint64_t producer_pa;
 115
 116    MegasasCmd frames[MEGASAS_MAX_FRAMES];
 117    DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
 118    SCSIBus bus;
 119} MegasasState;
 120
 121typedef struct MegasasBaseClass {
 122    PCIDeviceClass parent_class;
 123    const char *product_name;
 124    const char *product_version;
 125    int mmio_bar;
 126    int ioport_bar;
 127    int osts;
 128} MegasasBaseClass;
 129
 130#define TYPE_MEGASAS_BASE "megasas-base"
 131#define TYPE_MEGASAS_GEN1 "megasas"
 132#define TYPE_MEGASAS_GEN2 "megasas-gen2"
 133
 134#define MEGASAS(obj) \
 135    OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
 136
 137#define MEGASAS_DEVICE_CLASS(oc) \
 138    OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
 139#define MEGASAS_DEVICE_GET_CLASS(oc) \
 140    OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
 141
 142#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
 143
 144static bool megasas_intr_enabled(MegasasState *s)
 145{
 146    if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
 147        MEGASAS_INTR_DISABLED_MASK) {
 148        return true;
 149    }
 150    return false;
 151}
 152
 153static bool megasas_use_queue64(MegasasState *s)
 154{
 155    return s->flags & MEGASAS_MASK_USE_QUEUE64;
 156}
 157
 158static bool megasas_use_msix(MegasasState *s)
 159{
 160    return s->msix != ON_OFF_AUTO_OFF;
 161}
 162
 163static bool megasas_is_jbod(MegasasState *s)
 164{
 165    return s->flags & MEGASAS_MASK_USE_JBOD;
 166}
 167
 168static void megasas_frame_set_cmd_status(MegasasState *s,
 169                                         unsigned long frame, uint8_t v)
 170{
 171    PCIDevice *pci = &s->parent_obj;
 172    stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), v);
 173}
 174
 175static void megasas_frame_set_scsi_status(MegasasState *s,
 176                                          unsigned long frame, uint8_t v)
 177{
 178    PCIDevice *pci = &s->parent_obj;
 179    stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status), v);
 180}
 181
 182/*
 183 * Context is considered opaque, but the HBA firmware is running
 184 * in little endian mode. So convert it to little endian, too.
 185 */
 186static uint64_t megasas_frame_get_context(MegasasState *s,
 187                                          unsigned long frame)
 188{
 189    PCIDevice *pci = &s->parent_obj;
 190    return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context));
 191}
 192
 193static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
 194{
 195    return cmd->flags & MFI_FRAME_IEEE_SGL;
 196}
 197
 198static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
 199{
 200    return cmd->flags & MFI_FRAME_SGL64;
 201}
 202
 203static bool megasas_frame_is_sense64(MegasasCmd *cmd)
 204{
 205    return cmd->flags & MFI_FRAME_SENSE64;
 206}
 207
 208static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
 209                                     union mfi_sgl *sgl)
 210{
 211    uint64_t addr;
 212
 213    if (megasas_frame_is_ieee_sgl(cmd)) {
 214        addr = le64_to_cpu(sgl->sg_skinny->addr);
 215    } else if (megasas_frame_is_sgl64(cmd)) {
 216        addr = le64_to_cpu(sgl->sg64->addr);
 217    } else {
 218        addr = le32_to_cpu(sgl->sg32->addr);
 219    }
 220    return addr;
 221}
 222
 223static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
 224                                    union mfi_sgl *sgl)
 225{
 226    uint32_t len;
 227
 228    if (megasas_frame_is_ieee_sgl(cmd)) {
 229        len = le32_to_cpu(sgl->sg_skinny->len);
 230    } else if (megasas_frame_is_sgl64(cmd)) {
 231        len = le32_to_cpu(sgl->sg64->len);
 232    } else {
 233        len = le32_to_cpu(sgl->sg32->len);
 234    }
 235    return len;
 236}
 237
 238static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
 239                                       union mfi_sgl *sgl)
 240{
 241    uint8_t *next = (uint8_t *)sgl;
 242
 243    if (megasas_frame_is_ieee_sgl(cmd)) {
 244        next += sizeof(struct mfi_sg_skinny);
 245    } else if (megasas_frame_is_sgl64(cmd)) {
 246        next += sizeof(struct mfi_sg64);
 247    } else {
 248        next += sizeof(struct mfi_sg32);
 249    }
 250
 251    if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
 252        return NULL;
 253    }
 254    return (union mfi_sgl *)next;
 255}
 256
 257static void megasas_soft_reset(MegasasState *s);
 258
 259static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
 260{
 261    int i;
 262    int iov_count = 0;
 263    size_t iov_size = 0;
 264
 265    cmd->flags = le16_to_cpu(cmd->frame->header.flags);
 266    iov_count = cmd->frame->header.sge_count;
 267    if (iov_count > MEGASAS_MAX_SGE) {
 268        trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
 269                                         MEGASAS_MAX_SGE);
 270        return iov_count;
 271    }
 272    pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
 273    for (i = 0; i < iov_count; i++) {
 274        dma_addr_t iov_pa, iov_size_p;
 275
 276        if (!sgl) {
 277            trace_megasas_iovec_sgl_underflow(cmd->index, i);
 278            goto unmap;
 279        }
 280        iov_pa = megasas_sgl_get_addr(cmd, sgl);
 281        iov_size_p = megasas_sgl_get_len(cmd, sgl);
 282        if (!iov_pa || !iov_size_p) {
 283            trace_megasas_iovec_sgl_invalid(cmd->index, i,
 284                                            iov_pa, iov_size_p);
 285            goto unmap;
 286        }
 287        qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
 288        sgl = megasas_sgl_next(cmd, sgl);
 289        iov_size += (size_t)iov_size_p;
 290    }
 291    if (cmd->iov_size > iov_size) {
 292        trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
 293    } else if (cmd->iov_size < iov_size) {
 294        trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size);
 295    }
 296    cmd->iov_offset = 0;
 297    return 0;
 298unmap:
 299    qemu_sglist_destroy(&cmd->qsg);
 300    return iov_count - i;
 301}
 302
 303static void megasas_unmap_sgl(MegasasCmd *cmd)
 304{
 305    qemu_sglist_destroy(&cmd->qsg);
 306    cmd->iov_offset = 0;
 307}
 308
 309/*
 310 * passthrough sense and io sense are at the same offset
 311 */
 312static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
 313    uint8_t sense_len)
 314{
 315    PCIDevice *pcid = PCI_DEVICE(cmd->state);
 316    uint32_t pa_hi = 0, pa_lo;
 317    hwaddr pa;
 318
 319    if (sense_len > cmd->frame->header.sense_len) {
 320        sense_len = cmd->frame->header.sense_len;
 321    }
 322    if (sense_len) {
 323        pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
 324        if (megasas_frame_is_sense64(cmd)) {
 325            pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
 326        }
 327        pa = ((uint64_t) pa_hi << 32) | pa_lo;
 328        pci_dma_write(pcid, pa, sense_ptr, sense_len);
 329        cmd->frame->header.sense_len = sense_len;
 330    }
 331    return sense_len;
 332}
 333
 334static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
 335{
 336    uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
 337    uint8_t sense_len = 18;
 338
 339    memset(sense_buf, 0, sense_len);
 340    sense_buf[0] = 0xf0;
 341    sense_buf[2] = sense.key;
 342    sense_buf[7] = 10;
 343    sense_buf[12] = sense.asc;
 344    sense_buf[13] = sense.ascq;
 345    megasas_build_sense(cmd, sense_buf, sense_len);
 346}
 347
 348static void megasas_copy_sense(MegasasCmd *cmd)
 349{
 350    uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
 351    uint8_t sense_len;
 352
 353    sense_len = scsi_req_get_sense(cmd->req, sense_buf,
 354                                   SCSI_SENSE_BUF_SIZE);
 355    megasas_build_sense(cmd, sense_buf, sense_len);
 356}
 357
 358/*
 359 * Format an INQUIRY CDB
 360 */
 361static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
 362{
 363    memset(cdb, 0, 6);
 364    cdb[0] = INQUIRY;
 365    if (pg > 0) {
 366        cdb[1] = 0x1;
 367        cdb[2] = pg;
 368    }
 369    cdb[3] = (len >> 8) & 0xff;
 370    cdb[4] = (len & 0xff);
 371    return len;
 372}
 373
 374/*
 375 * Encode lba and len into a READ_16/WRITE_16 CDB
 376 */
 377static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
 378                               uint32_t len, bool is_write)
 379{
 380    memset(cdb, 0x0, 16);
 381    if (is_write) {
 382        cdb[0] = WRITE_16;
 383    } else {
 384        cdb[0] = READ_16;
 385    }
 386    cdb[2] = (lba >> 56) & 0xff;
 387    cdb[3] = (lba >> 48) & 0xff;
 388    cdb[4] = (lba >> 40) & 0xff;
 389    cdb[5] = (lba >> 32) & 0xff;
 390    cdb[6] = (lba >> 24) & 0xff;
 391    cdb[7] = (lba >> 16) & 0xff;
 392    cdb[8] = (lba >> 8) & 0xff;
 393    cdb[9] = (lba) & 0xff;
 394    cdb[10] = (len >> 24) & 0xff;
 395    cdb[11] = (len >> 16) & 0xff;
 396    cdb[12] = (len >> 8) & 0xff;
 397    cdb[13] = (len) & 0xff;
 398}
 399
 400/*
 401 * Utility functions
 402 */
 403static uint64_t megasas_fw_time(void)
 404{
 405    struct tm curtime;
 406
 407    qemu_get_timedate(&curtime, 0);
 408    return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
 409        ((uint64_t)curtime.tm_min & 0xff)  << 40 |
 410        ((uint64_t)curtime.tm_hour & 0xff) << 32 |
 411        ((uint64_t)curtime.tm_mday & 0xff) << 24 |
 412        ((uint64_t)curtime.tm_mon & 0xff)  << 16 |
 413        ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
 414}
 415
 416/*
 417 * Default disk sata address
 418 * 0x1221 is the magic number as
 419 * present in real hardware,
 420 * so use it here, too.
 421 */
 422static uint64_t megasas_get_sata_addr(uint16_t id)
 423{
 424    uint64_t addr = (0x1221ULL << 48);
 425    return addr | ((uint64_t)id << 24);
 426}
 427
 428/*
 429 * Frame handling
 430 */
 431static int megasas_next_index(MegasasState *s, int index, int limit)
 432{
 433    index++;
 434    if (index == limit) {
 435        index = 0;
 436    }
 437    return index;
 438}
 439
 440static MegasasCmd *megasas_lookup_frame(MegasasState *s,
 441    hwaddr frame)
 442{
 443    MegasasCmd *cmd = NULL;
 444    int num = 0, index;
 445
 446    index = s->reply_queue_head;
 447
 448    while (num < s->fw_cmds) {
 449        if (s->frames[index].pa && s->frames[index].pa == frame) {
 450            cmd = &s->frames[index];
 451            break;
 452        }
 453        index = megasas_next_index(s, index, s->fw_cmds);
 454        num++;
 455    }
 456
 457    return cmd;
 458}
 459
 460static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
 461{
 462    PCIDevice *p = PCI_DEVICE(s);
 463
 464    pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
 465    cmd->frame = NULL;
 466    cmd->pa = 0;
 467    clear_bit(cmd->index, s->frame_map);
 468}
 469
 470/*
 471 * This absolutely needs to be locked if
 472 * qemu ever goes multithreaded.
 473 */
 474static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
 475    hwaddr frame, uint64_t context, int count)
 476{
 477    PCIDevice *pcid = PCI_DEVICE(s);
 478    MegasasCmd *cmd = NULL;
 479    int frame_size = MFI_FRAME_SIZE * 16;
 480    hwaddr frame_size_p = frame_size;
 481    unsigned long index;
 482
 483    index = 0;
 484    while (index < s->fw_cmds) {
 485        index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
 486        if (!s->frames[index].pa)
 487            break;
 488        /* Busy frame found */
 489        trace_megasas_qf_mapped(index);
 490    }
 491    if (index >= s->fw_cmds) {
 492        /* All frames busy */
 493        trace_megasas_qf_busy(frame);
 494        return NULL;
 495    }
 496    cmd = &s->frames[index];
 497    set_bit(index, s->frame_map);
 498    trace_megasas_qf_new(index, frame);
 499
 500    cmd->pa = frame;
 501    /* Map all possible frames */
 502    cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
 503    if (frame_size_p != frame_size) {
 504        trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
 505        if (cmd->frame) {
 506            megasas_unmap_frame(s, cmd);
 507        }
 508        s->event_count++;
 509        return NULL;
 510    }
 511    cmd->pa_size = frame_size_p;
 512    cmd->context = context;
 513    if (!megasas_use_queue64(s)) {
 514        cmd->context &= (uint64_t)0xFFFFFFFF;
 515    }
 516    cmd->count = count;
 517    s->busy++;
 518
 519    if (s->consumer_pa) {
 520        s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
 521    }
 522    trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
 523                             s->reply_queue_head, s->reply_queue_tail, s->busy);
 524
 525    return cmd;
 526}
 527
 528static void megasas_complete_frame(MegasasState *s, uint64_t context)
 529{
 530    PCIDevice *pci_dev = PCI_DEVICE(s);
 531    int tail, queue_offset;
 532
 533    /* Decrement busy count */
 534    s->busy--;
 535    if (s->reply_queue_pa) {
 536        /*
 537         * Put command on the reply queue.
 538         * Context is opaque, but emulation is running in
 539         * little endian. So convert it.
 540         */
 541        if (megasas_use_queue64(s)) {
 542            queue_offset = s->reply_queue_head * sizeof(uint64_t);
 543            stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
 544        } else {
 545            queue_offset = s->reply_queue_head * sizeof(uint32_t);
 546            stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
 547        }
 548        s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
 549        trace_megasas_qf_complete(context, s->reply_queue_head,
 550                                  s->reply_queue_tail, s->busy);
 551    }
 552
 553    if (megasas_intr_enabled(s)) {
 554        /* Update reply queue pointer */
 555        s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
 556        tail = s->reply_queue_head;
 557        s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
 558        trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
 559                                s->busy);
 560        stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head);
 561        /* Notify HBA */
 562        if (msix_enabled(pci_dev)) {
 563            trace_megasas_msix_raise(0);
 564            msix_notify(pci_dev, 0);
 565        } else if (msi_enabled(pci_dev)) {
 566            trace_megasas_msi_raise(0);
 567            msi_notify(pci_dev, 0);
 568        } else {
 569            s->doorbell++;
 570            if (s->doorbell == 1) {
 571                trace_megasas_irq_raise();
 572                pci_irq_assert(pci_dev);
 573            }
 574        }
 575    } else {
 576        trace_megasas_qf_complete_noirq(context);
 577    }
 578}
 579
 580static void megasas_reset_frames(MegasasState *s)
 581{
 582    int i;
 583    MegasasCmd *cmd;
 584
 585    for (i = 0; i < s->fw_cmds; i++) {
 586        cmd = &s->frames[i];
 587        if (cmd->pa) {
 588            megasas_unmap_frame(s, cmd);
 589        }
 590    }
 591    bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
 592}
 593
 594static void megasas_abort_command(MegasasCmd *cmd)
 595{
 596    if (cmd->req) {
 597        scsi_req_cancel(cmd->req);
 598        cmd->req = NULL;
 599    }
 600}
 601
 602static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
 603{
 604    PCIDevice *pcid = PCI_DEVICE(s);
 605    uint32_t pa_hi, pa_lo;
 606    hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
 607    struct mfi_init_qinfo *initq = NULL;
 608    uint32_t flags;
 609    int ret = MFI_STAT_OK;
 610
 611    if (s->reply_queue_pa) {
 612        trace_megasas_initq_mapped(s->reply_queue_pa);
 613        goto out;
 614    }
 615    pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
 616    pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
 617    iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
 618    trace_megasas_init_firmware((uint64_t)iq_pa);
 619    initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
 620    if (!initq || initq_size != sizeof(*initq)) {
 621        trace_megasas_initq_map_failed(cmd->index);
 622        s->event_count++;
 623        ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
 624        goto out;
 625    }
 626    s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
 627    if (s->reply_queue_len > s->fw_cmds) {
 628        trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
 629        s->event_count++;
 630        ret = MFI_STAT_INVALID_PARAMETER;
 631        goto out;
 632    }
 633    pa_lo = le32_to_cpu(initq->rq_addr_lo);
 634    pa_hi = le32_to_cpu(initq->rq_addr_hi);
 635    s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
 636    pa_lo = le32_to_cpu(initq->ci_addr_lo);
 637    pa_hi = le32_to_cpu(initq->ci_addr_hi);
 638    s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
 639    pa_lo = le32_to_cpu(initq->pi_addr_lo);
 640    pa_hi = le32_to_cpu(initq->pi_addr_hi);
 641    s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
 642    s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa);
 643    s->reply_queue_head %= MEGASAS_MAX_FRAMES;
 644    s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
 645    s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
 646    flags = le32_to_cpu(initq->flags);
 647    if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
 648        s->flags |= MEGASAS_MASK_USE_QUEUE64;
 649    }
 650    trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
 651                             s->reply_queue_len, s->reply_queue_head,
 652                             s->reply_queue_tail, flags);
 653    megasas_reset_frames(s);
 654    s->fw_state = MFI_FWSTATE_OPERATIONAL;
 655out:
 656    if (initq) {
 657        pci_dma_unmap(pcid, initq, initq_size, 0, 0);
 658    }
 659    return ret;
 660}
 661
 662static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
 663{
 664    dma_addr_t iov_pa, iov_size;
 665
 666    cmd->flags = le16_to_cpu(cmd->frame->header.flags);
 667    if (!cmd->frame->header.sge_count) {
 668        trace_megasas_dcmd_zero_sge(cmd->index);
 669        cmd->iov_size = 0;
 670        return 0;
 671    } else if (cmd->frame->header.sge_count > 1) {
 672        trace_megasas_dcmd_invalid_sge(cmd->index,
 673                                       cmd->frame->header.sge_count);
 674        cmd->iov_size = 0;
 675        return -1;
 676    }
 677    iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
 678    iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
 679    pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
 680    qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
 681    cmd->iov_size = iov_size;
 682    return cmd->iov_size;
 683}
 684
 685static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
 686{
 687    trace_megasas_finish_dcmd(cmd->index, iov_size);
 688
 689    if (cmd->frame->header.sge_count) {
 690        qemu_sglist_destroy(&cmd->qsg);
 691    }
 692    if (iov_size > cmd->iov_size) {
 693        if (megasas_frame_is_ieee_sgl(cmd)) {
 694            cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
 695        } else if (megasas_frame_is_sgl64(cmd)) {
 696            cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
 697        } else {
 698            cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
 699        }
 700    }
 701    cmd->iov_size = 0;
 702}
 703
 704static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
 705{
 706    PCIDevice *pci_dev = PCI_DEVICE(s);
 707    PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
 708    MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
 709    struct mfi_ctrl_info info;
 710    size_t dcmd_size = sizeof(info);
 711    BusChild *kid;
 712    int num_pd_disks = 0;
 713
 714    memset(&info, 0x0, dcmd_size);
 715    if (cmd->iov_size < dcmd_size) {
 716        trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
 717                                            dcmd_size);
 718        return MFI_STAT_INVALID_PARAMETER;
 719    }
 720
 721    info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
 722    info.pci.device = cpu_to_le16(pci_class->device_id);
 723    info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
 724    info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
 725
 726    /*
 727     * For some reason the firmware supports
 728     * only up to 8 device ports.
 729     * Despite supporting a far larger number
 730     * of devices for the physical devices.
 731     * So just display the first 8 devices
 732     * in the device port list, independent
 733     * of how many logical devices are actually
 734     * present.
 735     */
 736    info.host.type = MFI_INFO_HOST_PCIE;
 737    info.device.type = MFI_INFO_DEV_SAS3G;
 738    info.device.port_count = 8;
 739    QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
 740        SCSIDevice *sdev = SCSI_DEVICE(kid->child);
 741        uint16_t pd_id;
 742
 743        if (num_pd_disks < 8) {
 744            pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
 745            info.device.port_addr[num_pd_disks] =
 746                cpu_to_le64(megasas_get_sata_addr(pd_id));
 747        }
 748        num_pd_disks++;
 749    }
 750
 751    memcpy(info.product_name, base_class->product_name, 24);
 752    snprintf(info.serial_number, 32, "%s", s->hba_serial);
 753    snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
 754    memcpy(info.image_component[0].name, "APP", 3);
 755    snprintf(info.image_component[0].version, 10, "%s-QEMU",
 756             base_class->product_version);
 757    memcpy(info.image_component[0].build_date, "Apr  1 2014", 11);
 758    memcpy(info.image_component[0].build_time, "12:34:56", 8);
 759    info.image_component_count = 1;
 760    if (pci_dev->has_rom) {
 761        uint8_t biosver[32];
 762        uint8_t *ptr;
 763
 764        ptr = memory_region_get_ram_ptr(&pci_dev->rom);
 765        memcpy(biosver, ptr + 0x41, 31);
 766        biosver[31] = 0;
 767        memcpy(info.image_component[1].name, "BIOS", 4);
 768        memcpy(info.image_component[1].version, biosver,
 769               strlen((const char *)biosver));
 770        info.image_component_count++;
 771    }
 772    info.current_fw_time = cpu_to_le32(megasas_fw_time());
 773    info.max_arms = 32;
 774    info.max_spans = 8;
 775    info.max_arrays = MEGASAS_MAX_ARRAYS;
 776    info.max_lds = MFI_MAX_LD;
 777    info.max_cmds = cpu_to_le16(s->fw_cmds);
 778    info.max_sg_elements = cpu_to_le16(s->fw_sge);
 779    info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
 780    if (!megasas_is_jbod(s))
 781        info.lds_present = cpu_to_le16(num_pd_disks);
 782    info.pd_present = cpu_to_le16(num_pd_disks);
 783    info.pd_disks_present = cpu_to_le16(num_pd_disks);
 784    info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
 785                                   MFI_INFO_HW_MEM |
 786                                   MFI_INFO_HW_FLASH);
 787    info.memory_size = cpu_to_le16(512);
 788    info.nvram_size = cpu_to_le16(32);
 789    info.flash_size = cpu_to_le16(16);
 790    info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
 791    info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
 792                                    MFI_INFO_AOPS_SELF_DIAGNOSTIC |
 793                                    MFI_INFO_AOPS_MIXED_ARRAY);
 794    info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
 795                               MFI_INFO_LDOPS_ACCESS_POLICY |
 796                               MFI_INFO_LDOPS_IO_POLICY |
 797                               MFI_INFO_LDOPS_WRITE_POLICY |
 798                               MFI_INFO_LDOPS_READ_POLICY);
 799    info.max_strips_per_io = cpu_to_le16(s->fw_sge);
 800    info.stripe_sz_ops.min = 3;
 801    info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
 802    info.properties.pred_fail_poll_interval = cpu_to_le16(300);
 803    info.properties.intr_throttle_cnt = cpu_to_le16(16);
 804    info.properties.intr_throttle_timeout = cpu_to_le16(50);
 805    info.properties.rebuild_rate = 30;
 806    info.properties.patrol_read_rate = 30;
 807    info.properties.bgi_rate = 30;
 808    info.properties.cc_rate = 30;
 809    info.properties.recon_rate = 30;
 810    info.properties.cache_flush_interval = 4;
 811    info.properties.spinup_drv_cnt = 2;
 812    info.properties.spinup_delay = 6;
 813    info.properties.ecc_bucket_size = 15;
 814    info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
 815    info.properties.expose_encl_devices = 1;
 816    info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
 817    info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
 818                               MFI_INFO_PDOPS_FORCE_OFFLINE);
 819    info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
 820                                       MFI_INFO_PDMIX_SATA |
 821                                       MFI_INFO_PDMIX_LD);
 822
 823    cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
 824    return MFI_STAT_OK;
 825}
 826
 827static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
 828{
 829    struct mfi_defaults info;
 830    size_t dcmd_size = sizeof(struct mfi_defaults);
 831
 832    memset(&info, 0x0, dcmd_size);
 833    if (cmd->iov_size < dcmd_size) {
 834        trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
 835                                            dcmd_size);
 836        return MFI_STAT_INVALID_PARAMETER;
 837    }
 838
 839    info.sas_addr = cpu_to_le64(s->sas_addr);
 840    info.stripe_size = 3;
 841    info.flush_time = 4;
 842    info.background_rate = 30;
 843    info.allow_mix_in_enclosure = 1;
 844    info.allow_mix_in_ld = 1;
 845    info.direct_pd_mapping = 1;
 846    /* Enable for BIOS support */
 847    info.bios_enumerate_lds = 1;
 848    info.disable_ctrl_r = 1;
 849    info.expose_enclosure_devices = 1;
 850    info.disable_preboot_cli = 1;
 851    info.cluster_disable = 1;
 852
 853    cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
 854    return MFI_STAT_OK;
 855}
 856
 857static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
 858{
 859    struct mfi_bios_data info;
 860    size_t dcmd_size = sizeof(info);
 861
 862    memset(&info, 0x0, dcmd_size);
 863    if (cmd->iov_size < dcmd_size) {
 864        trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
 865                                            dcmd_size);
 866        return MFI_STAT_INVALID_PARAMETER;
 867    }
 868    info.continue_on_error = 1;
 869    info.verbose = 1;
 870    if (megasas_is_jbod(s)) {
 871        info.expose_all_drives = 1;
 872    }
 873
 874    cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
 875    return MFI_STAT_OK;
 876}
 877
 878static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
 879{
 880    uint64_t fw_time;
 881    size_t dcmd_size = sizeof(fw_time);
 882
 883    fw_time = cpu_to_le64(megasas_fw_time());
 884
 885    cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
 886    return MFI_STAT_OK;
 887}
 888
 889static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
 890{
 891    uint64_t fw_time;
 892
 893    /* This is a dummy; setting of firmware time is not allowed */
 894    memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
 895
 896    trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
 897    fw_time = cpu_to_le64(megasas_fw_time());
 898    return MFI_STAT_OK;
 899}
 900
 901static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
 902{
 903    struct mfi_evt_log_state info;
 904    size_t dcmd_size = sizeof(info);
 905
 906    memset(&info, 0, dcmd_size);
 907
 908    info.newest_seq_num = cpu_to_le32(s->event_count);
 909    info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
 910    info.boot_seq_num = cpu_to_le32(s->boot_event);
 911
 912    cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
 913    return MFI_STAT_OK;
 914}
 915
 916static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
 917{
 918    union mfi_evt event;
 919
 920    if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
 921        trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
 922                                            sizeof(struct mfi_evt_detail));
 923        return MFI_STAT_INVALID_PARAMETER;
 924    }
 925    s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
 926    event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
 927    s->event_locale = event.members.locale;
 928    s->event_class = event.members.class;
 929    s->event_cmd = cmd;
 930    /* Decrease busy count; event frame doesn't count here */
 931    s->busy--;
 932    cmd->iov_size = sizeof(struct mfi_evt_detail);
 933    return MFI_STAT_INVALID_STATUS;
 934}
 935
 936static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
 937{
 938    struct mfi_pd_list info;
 939    size_t dcmd_size = sizeof(info);
 940    BusChild *kid;
 941    uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
 942
 943    memset(&info, 0, dcmd_size);
 944    offset = 8;
 945    dcmd_limit = offset + sizeof(struct mfi_pd_address);
 946    if (cmd->iov_size < dcmd_limit) {
 947        trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
 948                                            dcmd_limit);
 949        return MFI_STAT_INVALID_PARAMETER;
 950    }
 951
 952    max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
 953    if (max_pd_disks > MFI_MAX_SYS_PDS) {
 954        max_pd_disks = MFI_MAX_SYS_PDS;
 955    }
 956    QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
 957        SCSIDevice *sdev = SCSI_DEVICE(kid->child);
 958        uint16_t pd_id;
 959
 960        if (num_pd_disks >= max_pd_disks)
 961            break;
 962
 963        pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
 964        info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
 965        info.addr[num_pd_disks].encl_device_id = 0xFFFF;
 966        info.addr[num_pd_disks].encl_index = 0;
 967        info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
 968        info.addr[num_pd_disks].scsi_dev_type = sdev->type;
 969        info.addr[num_pd_disks].connect_port_bitmap = 0x1;
 970        info.addr[num_pd_disks].sas_addr[0] =
 971            cpu_to_le64(megasas_get_sata_addr(pd_id));
 972        num_pd_disks++;
 973        offset += sizeof(struct mfi_pd_address);
 974    }
 975    trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
 976                                   max_pd_disks, offset);
 977
 978    info.size = cpu_to_le32(offset);
 979    info.count = cpu_to_le32(num_pd_disks);
 980
 981    cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
 982    return MFI_STAT_OK;
 983}
 984
 985static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
 986{
 987    uint16_t flags;
 988
 989    /* mbox0 contains flags */
 990    flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
 991    trace_megasas_dcmd_pd_list_query(cmd->index, flags);
 992    if (flags == MR_PD_QUERY_TYPE_ALL ||
 993        megasas_is_jbod(s)) {
 994        return megasas_dcmd_pd_get_list(s, cmd);
 995    }
 996
 997    return MFI_STAT_OK;
 998}
 999
1000static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1001                                      MegasasCmd *cmd)
1002{
1003    struct mfi_pd_info *info = cmd->iov_buf;
1004    size_t dcmd_size = sizeof(struct mfi_pd_info);
1005    uint64_t pd_size;
1006    uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1007    uint8_t cmdbuf[6];
1008    SCSIRequest *req;
1009    size_t len, resid;
1010
1011    if (!cmd->iov_buf) {
1012        cmd->iov_buf = g_malloc0(dcmd_size);
1013        info = cmd->iov_buf;
1014        info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1015        info->vpd_page83[0] = 0x7f;
1016        megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1017        req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1018        if (!req) {
1019            trace_megasas_dcmd_req_alloc_failed(cmd->index,
1020                                                "PD get info std inquiry");
1021            g_free(cmd->iov_buf);
1022            cmd->iov_buf = NULL;
1023            return MFI_STAT_FLASH_ALLOC_FAIL;
1024        }
1025        trace_megasas_dcmd_internal_submit(cmd->index,
1026                                           "PD get info std inquiry", lun);
1027        len = scsi_req_enqueue(req);
1028        if (len > 0) {
1029            cmd->iov_size = len;
1030            scsi_req_continue(req);
1031        }
1032        return MFI_STAT_INVALID_STATUS;
1033    } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1034        megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1035        req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1036        if (!req) {
1037            trace_megasas_dcmd_req_alloc_failed(cmd->index,
1038                                                "PD get info vpd inquiry");
1039            return MFI_STAT_FLASH_ALLOC_FAIL;
1040        }
1041        trace_megasas_dcmd_internal_submit(cmd->index,
1042                                           "PD get info vpd inquiry", lun);
1043        len = scsi_req_enqueue(req);
1044        if (len > 0) {
1045            cmd->iov_size = len;
1046            scsi_req_continue(req);
1047        }
1048        return MFI_STAT_INVALID_STATUS;
1049    }
1050    /* Finished, set FW state */
1051    if ((info->inquiry_data[0] >> 5) == 0) {
1052        if (megasas_is_jbod(cmd->state)) {
1053            info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1054        } else {
1055            info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1056        }
1057    } else {
1058        info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1059    }
1060
1061    info->ref.v.device_id = cpu_to_le16(pd_id);
1062    info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1063                                          MFI_PD_DDF_TYPE_INTF_SAS);
1064    blk_get_geometry(sdev->conf.blk, &pd_size);
1065    info->raw_size = cpu_to_le64(pd_size);
1066    info->non_coerced_size = cpu_to_le64(pd_size);
1067    info->coerced_size = cpu_to_le64(pd_size);
1068    info->encl_device_id = 0xFFFF;
1069    info->slot_number = (sdev->id & 0xFF);
1070    info->path_info.count = 1;
1071    info->path_info.sas_addr[0] =
1072        cpu_to_le64(megasas_get_sata_addr(pd_id));
1073    info->connected_port_bitmap = 0x1;
1074    info->device_speed = 1;
1075    info->link_speed = 1;
1076    resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1077    g_free(cmd->iov_buf);
1078    cmd->iov_size = dcmd_size - resid;
1079    cmd->iov_buf = NULL;
1080    return MFI_STAT_OK;
1081}
1082
1083static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1084{
1085    size_t dcmd_size = sizeof(struct mfi_pd_info);
1086    uint16_t pd_id;
1087    uint8_t target_id, lun_id;
1088    SCSIDevice *sdev = NULL;
1089    int retval = MFI_STAT_DEVICE_NOT_FOUND;
1090
1091    if (cmd->iov_size < dcmd_size) {
1092        return MFI_STAT_INVALID_PARAMETER;
1093    }
1094
1095    /* mbox0 has the ID */
1096    pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1097    target_id = (pd_id >> 8) & 0xFF;
1098    lun_id = pd_id & 0xFF;
1099    sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1100    trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1101
1102    if (sdev) {
1103        /* Submit inquiry */
1104        retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1105    }
1106
1107    return retval;
1108}
1109
1110static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1111{
1112    struct mfi_ld_list info;
1113    size_t dcmd_size = sizeof(info), resid;
1114    uint32_t num_ld_disks = 0, max_ld_disks;
1115    uint64_t ld_size;
1116    BusChild *kid;
1117
1118    memset(&info, 0, dcmd_size);
1119    if (cmd->iov_size > dcmd_size) {
1120        trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1121                                            dcmd_size);
1122        return MFI_STAT_INVALID_PARAMETER;
1123    }
1124
1125    max_ld_disks = (cmd->iov_size - 8) / 16;
1126    if (megasas_is_jbod(s)) {
1127        max_ld_disks = 0;
1128    }
1129    if (max_ld_disks > MFI_MAX_LD) {
1130        max_ld_disks = MFI_MAX_LD;
1131    }
1132    QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1133        SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1134
1135        if (num_ld_disks >= max_ld_disks) {
1136            break;
1137        }
1138        /* Logical device size is in blocks */
1139        blk_get_geometry(sdev->conf.blk, &ld_size);
1140        info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1141        info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1142        info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1143        num_ld_disks++;
1144    }
1145    info.ld_count = cpu_to_le32(num_ld_disks);
1146    trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1147
1148    resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1149    cmd->iov_size = dcmd_size - resid;
1150    return MFI_STAT_OK;
1151}
1152
1153static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1154{
1155    uint16_t flags;
1156    struct mfi_ld_targetid_list info;
1157    size_t dcmd_size = sizeof(info), resid;
1158    uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1159    BusChild *kid;
1160
1161    /* mbox0 contains flags */
1162    flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1163    trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1164    if (flags != MR_LD_QUERY_TYPE_ALL &&
1165        flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1166        max_ld_disks = 0;
1167    }
1168
1169    memset(&info, 0, dcmd_size);
1170    if (cmd->iov_size < 12) {
1171        trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1172                                            dcmd_size);
1173        return MFI_STAT_INVALID_PARAMETER;
1174    }
1175    dcmd_size = sizeof(uint32_t) * 2 + 3;
1176    max_ld_disks = cmd->iov_size - dcmd_size;
1177    if (megasas_is_jbod(s)) {
1178        max_ld_disks = 0;
1179    }
1180    if (max_ld_disks > MFI_MAX_LD) {
1181        max_ld_disks = MFI_MAX_LD;
1182    }
1183    QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1184        SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1185
1186        if (num_ld_disks >= max_ld_disks) {
1187            break;
1188        }
1189        info.targetid[num_ld_disks] = sdev->lun;
1190        num_ld_disks++;
1191        dcmd_size++;
1192    }
1193    info.ld_count = cpu_to_le32(num_ld_disks);
1194    info.size = dcmd_size;
1195    trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1196
1197    resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1198    cmd->iov_size = dcmd_size - resid;
1199    return MFI_STAT_OK;
1200}
1201
1202static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1203                                      MegasasCmd *cmd)
1204{
1205    struct mfi_ld_info *info = cmd->iov_buf;
1206    size_t dcmd_size = sizeof(struct mfi_ld_info);
1207    uint8_t cdb[6];
1208    SCSIRequest *req;
1209    ssize_t len, resid;
1210    uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1211    uint64_t ld_size;
1212
1213    if (!cmd->iov_buf) {
1214        cmd->iov_buf = g_malloc0(dcmd_size);
1215        info = cmd->iov_buf;
1216        megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1217        req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1218        if (!req) {
1219            trace_megasas_dcmd_req_alloc_failed(cmd->index,
1220                                                "LD get info vpd inquiry");
1221            g_free(cmd->iov_buf);
1222            cmd->iov_buf = NULL;
1223            return MFI_STAT_FLASH_ALLOC_FAIL;
1224        }
1225        trace_megasas_dcmd_internal_submit(cmd->index,
1226                                           "LD get info vpd inquiry", lun);
1227        len = scsi_req_enqueue(req);
1228        if (len > 0) {
1229            cmd->iov_size = len;
1230            scsi_req_continue(req);
1231        }
1232        return MFI_STAT_INVALID_STATUS;
1233    }
1234
1235    info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1236    info->ld_config.properties.ld.v.target_id = lun;
1237    info->ld_config.params.stripe_size = 3;
1238    info->ld_config.params.num_drives = 1;
1239    info->ld_config.params.is_consistent = 1;
1240    /* Logical device size is in blocks */
1241    blk_get_geometry(sdev->conf.blk, &ld_size);
1242    info->size = cpu_to_le64(ld_size);
1243    memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1244    info->ld_config.span[0].start_block = 0;
1245    info->ld_config.span[0].num_blocks = info->size;
1246    info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1247
1248    resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1249    g_free(cmd->iov_buf);
1250    cmd->iov_size = dcmd_size - resid;
1251    cmd->iov_buf = NULL;
1252    return MFI_STAT_OK;
1253}
1254
1255static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1256{
1257    struct mfi_ld_info info;
1258    size_t dcmd_size = sizeof(info);
1259    uint16_t ld_id;
1260    uint32_t max_ld_disks = s->fw_luns;
1261    SCSIDevice *sdev = NULL;
1262    int retval = MFI_STAT_DEVICE_NOT_FOUND;
1263
1264    if (cmd->iov_size < dcmd_size) {
1265        return MFI_STAT_INVALID_PARAMETER;
1266    }
1267
1268    /* mbox0 has the ID */
1269    ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1270    trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1271
1272    if (megasas_is_jbod(s)) {
1273        return MFI_STAT_DEVICE_NOT_FOUND;
1274    }
1275
1276    if (ld_id < max_ld_disks) {
1277        sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1278    }
1279
1280    if (sdev) {
1281        retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1282    }
1283
1284    return retval;
1285}
1286
1287static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1288{
1289    uint8_t data[4096] = { 0 };
1290    struct mfi_config_data *info;
1291    int num_pd_disks = 0, array_offset, ld_offset;
1292    BusChild *kid;
1293
1294    if (cmd->iov_size > 4096) {
1295        return MFI_STAT_INVALID_PARAMETER;
1296    }
1297
1298    QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1299        num_pd_disks++;
1300    }
1301    info = (struct mfi_config_data *)&data;
1302    /*
1303     * Array mapping:
1304     * - One array per SCSI device
1305     * - One logical drive per SCSI device
1306     *   spanning the entire device
1307     */
1308    info->array_count = num_pd_disks;
1309    info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1310    info->log_drv_count = num_pd_disks;
1311    info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1312    info->spares_count = 0;
1313    info->spares_size = sizeof(struct mfi_spare);
1314    info->size = sizeof(struct mfi_config_data) + info->array_size +
1315        info->log_drv_size;
1316    if (info->size > 4096) {
1317        return MFI_STAT_INVALID_PARAMETER;
1318    }
1319
1320    array_offset = sizeof(struct mfi_config_data);
1321    ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1322
1323    QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1324        SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1325        uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1326        struct mfi_array *array;
1327        struct mfi_ld_config *ld;
1328        uint64_t pd_size;
1329        int i;
1330
1331        array = (struct mfi_array *)(data + array_offset);
1332        blk_get_geometry(sdev->conf.blk, &pd_size);
1333        array->size = cpu_to_le64(pd_size);
1334        array->num_drives = 1;
1335        array->array_ref = cpu_to_le16(sdev_id);
1336        array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1337        array->pd[0].ref.v.seq_num = 0;
1338        array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1339        array->pd[0].encl.pd = 0xFF;
1340        array->pd[0].encl.slot = (sdev->id & 0xFF);
1341        for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1342            array->pd[i].ref.v.device_id = 0xFFFF;
1343            array->pd[i].ref.v.seq_num = 0;
1344            array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1345            array->pd[i].encl.pd = 0xFF;
1346            array->pd[i].encl.slot = 0xFF;
1347        }
1348        array_offset += sizeof(struct mfi_array);
1349        ld = (struct mfi_ld_config *)(data + ld_offset);
1350        memset(ld, 0, sizeof(struct mfi_ld_config));
1351        ld->properties.ld.v.target_id = sdev->id;
1352        ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1353            MR_LD_CACHE_READ_ADAPTIVE;
1354        ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1355            MR_LD_CACHE_READ_ADAPTIVE;
1356        ld->params.state = MFI_LD_STATE_OPTIMAL;
1357        ld->params.stripe_size = 3;
1358        ld->params.num_drives = 1;
1359        ld->params.span_depth = 1;
1360        ld->params.is_consistent = 1;
1361        ld->span[0].start_block = 0;
1362        ld->span[0].num_blocks = cpu_to_le64(pd_size);
1363        ld->span[0].array_ref = cpu_to_le16(sdev_id);
1364        ld_offset += sizeof(struct mfi_ld_config);
1365    }
1366
1367    cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1368    return MFI_STAT_OK;
1369}
1370
1371static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1372{
1373    struct mfi_ctrl_props info;
1374    size_t dcmd_size = sizeof(info);
1375
1376    memset(&info, 0x0, dcmd_size);
1377    if (cmd->iov_size < dcmd_size) {
1378        trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1379                                            dcmd_size);
1380        return MFI_STAT_INVALID_PARAMETER;
1381    }
1382    info.pred_fail_poll_interval = cpu_to_le16(300);
1383    info.intr_throttle_cnt = cpu_to_le16(16);
1384    info.intr_throttle_timeout = cpu_to_le16(50);
1385    info.rebuild_rate = 30;
1386    info.patrol_read_rate = 30;
1387    info.bgi_rate = 30;
1388    info.cc_rate = 30;
1389    info.recon_rate = 30;
1390    info.cache_flush_interval = 4;
1391    info.spinup_drv_cnt = 2;
1392    info.spinup_delay = 6;
1393    info.ecc_bucket_size = 15;
1394    info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1395    info.expose_encl_devices = 1;
1396
1397    cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1398    return MFI_STAT_OK;
1399}
1400
1401static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1402{
1403    blk_drain_all();
1404    return MFI_STAT_OK;
1405}
1406
1407static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1408{
1409    s->fw_state = MFI_FWSTATE_READY;
1410    return MFI_STAT_OK;
1411}
1412
1413/* Some implementations use CLUSTER RESET LD to simulate a device reset */
1414static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1415{
1416    uint16_t target_id;
1417    int i;
1418
1419    /* mbox0 contains the device index */
1420    target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1421    trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1422    for (i = 0; i < s->fw_cmds; i++) {
1423        MegasasCmd *tmp_cmd = &s->frames[i];
1424        if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1425            SCSIDevice *d = tmp_cmd->req->dev;
1426            qdev_reset_all(&d->qdev);
1427        }
1428    }
1429    return MFI_STAT_OK;
1430}
1431
1432static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1433{
1434    struct mfi_ctrl_props info;
1435    size_t dcmd_size = sizeof(info);
1436
1437    if (cmd->iov_size < dcmd_size) {
1438        trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1439                                            dcmd_size);
1440        return MFI_STAT_INVALID_PARAMETER;
1441    }
1442    dma_buf_write((uint8_t *)&info, dcmd_size, &cmd->qsg);
1443    trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
1444    return MFI_STAT_OK;
1445}
1446
1447static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1448{
1449    trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1450    return MFI_STAT_OK;
1451}
1452
1453static const struct dcmd_cmd_tbl_t {
1454    int opcode;
1455    const char *desc;
1456    int (*func)(MegasasState *s, MegasasCmd *cmd);
1457} dcmd_cmd_tbl[] = {
1458    { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1459      megasas_dcmd_dummy },
1460    { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1461      megasas_ctrl_get_info },
1462    { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1463      megasas_dcmd_get_properties },
1464    { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1465      megasas_dcmd_set_properties },
1466    { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1467      megasas_dcmd_dummy },
1468    { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1469      megasas_dcmd_dummy },
1470    { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1471      megasas_dcmd_dummy },
1472    { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1473      megasas_dcmd_dummy },
1474    { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1475      megasas_dcmd_dummy },
1476    { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1477      megasas_event_info },
1478    { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1479      megasas_dcmd_dummy },
1480    { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1481      megasas_event_wait },
1482    { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1483      megasas_ctrl_shutdown },
1484    { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1485      megasas_dcmd_dummy },
1486    { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1487      megasas_dcmd_get_fw_time },
1488    { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1489      megasas_dcmd_set_fw_time },
1490    { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1491      megasas_dcmd_get_bios_info },
1492    { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1493      megasas_dcmd_dummy },
1494    { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1495      megasas_mfc_get_defaults },
1496    { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1497      megasas_dcmd_dummy },
1498    { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1499      megasas_cache_flush },
1500    { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1501      megasas_dcmd_pd_get_list },
1502    { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1503      megasas_dcmd_pd_list_query },
1504    { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1505      megasas_dcmd_pd_get_info },
1506    { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1507      megasas_dcmd_dummy },
1508    { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1509      megasas_dcmd_dummy },
1510    { MFI_DCMD_PD_BLINK, "PD_BLINK",
1511      megasas_dcmd_dummy },
1512    { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1513      megasas_dcmd_dummy },
1514    { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1515      megasas_dcmd_ld_get_list},
1516    { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1517      megasas_dcmd_ld_list_query },
1518    { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1519      megasas_dcmd_ld_get_info },
1520    { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1521      megasas_dcmd_dummy },
1522    { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1523      megasas_dcmd_dummy },
1524    { MFI_DCMD_LD_DELETE, "LD_DELETE",
1525      megasas_dcmd_dummy },
1526    { MFI_DCMD_CFG_READ, "CFG_READ",
1527      megasas_dcmd_cfg_read },
1528    { MFI_DCMD_CFG_ADD, "CFG_ADD",
1529      megasas_dcmd_dummy },
1530    { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1531      megasas_dcmd_dummy },
1532    { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1533      megasas_dcmd_dummy },
1534    { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1535      megasas_dcmd_dummy },
1536    { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1537      megasas_dcmd_dummy },
1538    { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1539      megasas_dcmd_dummy },
1540    { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1541      megasas_dcmd_dummy },
1542    { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1543      megasas_dcmd_dummy },
1544    { MFI_DCMD_CLUSTER, "CLUSTER",
1545      megasas_dcmd_dummy },
1546    { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1547      megasas_dcmd_dummy },
1548    { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1549      megasas_cluster_reset_ld },
1550    { -1, NULL, NULL }
1551};
1552
1553static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1554{
1555    int opcode, len;
1556    int retval = 0;
1557    const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1558
1559    opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1560    trace_megasas_handle_dcmd(cmd->index, opcode);
1561    len = megasas_map_dcmd(s, cmd);
1562    if (len < 0) {
1563        return MFI_STAT_MEMORY_NOT_AVAILABLE;
1564    }
1565    while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) {
1566        cmdptr++;
1567    }
1568    if (cmdptr->opcode == -1) {
1569        trace_megasas_dcmd_unhandled(cmd->index, opcode, len);
1570        retval = megasas_dcmd_dummy(s, cmd);
1571    } else {
1572        trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1573        retval = cmdptr->func(s, cmd);
1574    }
1575    if (retval != MFI_STAT_INVALID_STATUS) {
1576        megasas_finish_dcmd(cmd, len);
1577    }
1578    return retval;
1579}
1580
1581static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1582                                        SCSIRequest *req)
1583{
1584    int opcode;
1585    int retval = MFI_STAT_OK;
1586    int lun = req->lun;
1587
1588    opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1589    scsi_req_unref(req);
1590    trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun);
1591    switch (opcode) {
1592    case MFI_DCMD_PD_GET_INFO:
1593        retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1594        break;
1595    case MFI_DCMD_LD_GET_INFO:
1596        retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1597        break;
1598    default:
1599        trace_megasas_dcmd_internal_invalid(cmd->index, opcode);
1600        retval = MFI_STAT_INVALID_DCMD;
1601        break;
1602    }
1603    if (retval != MFI_STAT_INVALID_STATUS) {
1604        megasas_finish_dcmd(cmd, cmd->iov_size);
1605    }
1606    return retval;
1607}
1608
1609static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1610{
1611    int len;
1612
1613    len = scsi_req_enqueue(cmd->req);
1614    if (len < 0) {
1615        len = -len;
1616    }
1617    if (len > 0) {
1618        if (len > cmd->iov_size) {
1619            if (is_write) {
1620                trace_megasas_iov_write_overflow(cmd->index, len,
1621                                                 cmd->iov_size);
1622            } else {
1623                trace_megasas_iov_read_overflow(cmd->index, len,
1624                                                cmd->iov_size);
1625            }
1626        }
1627        if (len < cmd->iov_size) {
1628            if (is_write) {
1629                trace_megasas_iov_write_underflow(cmd->index, len,
1630                                                  cmd->iov_size);
1631            } else {
1632                trace_megasas_iov_read_underflow(cmd->index, len,
1633                                                 cmd->iov_size);
1634            }
1635            cmd->iov_size = len;
1636        }
1637        scsi_req_continue(cmd->req);
1638    }
1639    return len;
1640}
1641
1642static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1643                               bool is_logical)
1644{
1645    uint8_t *cdb;
1646    bool is_write;
1647    struct SCSIDevice *sdev = NULL;
1648
1649    cdb = cmd->frame->pass.cdb;
1650
1651    if (is_logical) {
1652        if (cmd->frame->header.target_id >= MFI_MAX_LD ||
1653            cmd->frame->header.lun_id != 0) {
1654            trace_megasas_scsi_target_not_present(
1655                mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1656                cmd->frame->header.target_id, cmd->frame->header.lun_id);
1657            return MFI_STAT_DEVICE_NOT_FOUND;
1658        }
1659    }
1660    sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1661                            cmd->frame->header.lun_id);
1662
1663    cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1664    trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
1665                              is_logical, cmd->frame->header.target_id,
1666                              cmd->frame->header.lun_id, sdev, cmd->iov_size);
1667
1668    if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1669        trace_megasas_scsi_target_not_present(
1670            mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1671            cmd->frame->header.target_id, cmd->frame->header.lun_id);
1672        return MFI_STAT_DEVICE_NOT_FOUND;
1673    }
1674
1675    if (cmd->frame->header.cdb_len > 16) {
1676        trace_megasas_scsi_invalid_cdb_len(
1677                mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1678                cmd->frame->header.target_id, cmd->frame->header.lun_id,
1679                cmd->frame->header.cdb_len);
1680        megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1681        cmd->frame->header.scsi_status = CHECK_CONDITION;
1682        s->event_count++;
1683        return MFI_STAT_SCSI_DONE_WITH_ERROR;
1684    }
1685
1686    if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1687        megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1688        cmd->frame->header.scsi_status = CHECK_CONDITION;
1689        s->event_count++;
1690        return MFI_STAT_SCSI_DONE_WITH_ERROR;
1691    }
1692
1693    cmd->req = scsi_req_new(sdev, cmd->index,
1694                            cmd->frame->header.lun_id, cdb, cmd);
1695    if (!cmd->req) {
1696        trace_megasas_scsi_req_alloc_failed(
1697                mfi_frame_desc[cmd->frame->header.frame_cmd],
1698                cmd->frame->header.target_id, cmd->frame->header.lun_id);
1699        megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1700        cmd->frame->header.scsi_status = BUSY;
1701        s->event_count++;
1702        return MFI_STAT_SCSI_DONE_WITH_ERROR;
1703    }
1704
1705    is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1706    if (cmd->iov_size) {
1707        if (is_write) {
1708            trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
1709        } else {
1710            trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
1711        }
1712    } else {
1713        trace_megasas_scsi_nodata(cmd->index);
1714    }
1715    megasas_enqueue_req(cmd, is_write);
1716    return MFI_STAT_INVALID_STATUS;
1717}
1718
1719static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd)
1720{
1721    uint32_t lba_count, lba_start_hi, lba_start_lo;
1722    uint64_t lba_start;
1723    bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
1724    uint8_t cdb[16];
1725    int len;
1726    struct SCSIDevice *sdev = NULL;
1727
1728    lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1729    lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1730    lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1731    lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1732
1733    if (cmd->frame->header.target_id < MFI_MAX_LD &&
1734        cmd->frame->header.lun_id == 0) {
1735        sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1736                                cmd->frame->header.lun_id);
1737    }
1738
1739    trace_megasas_handle_io(cmd->index,
1740                            mfi_frame_desc[cmd->frame->header.frame_cmd],
1741                            cmd->frame->header.target_id,
1742                            cmd->frame->header.lun_id,
1743                            (unsigned long)lba_start, (unsigned long)lba_count);
1744    if (!sdev) {
1745        trace_megasas_io_target_not_present(cmd->index,
1746            mfi_frame_desc[cmd->frame->header.frame_cmd],
1747            cmd->frame->header.target_id, cmd->frame->header.lun_id);
1748        return MFI_STAT_DEVICE_NOT_FOUND;
1749    }
1750
1751    if (cmd->frame->header.cdb_len > 16) {
1752        trace_megasas_scsi_invalid_cdb_len(
1753            mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
1754            cmd->frame->header.target_id, cmd->frame->header.lun_id,
1755            cmd->frame->header.cdb_len);
1756        megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1757        cmd->frame->header.scsi_status = CHECK_CONDITION;
1758        s->event_count++;
1759        return MFI_STAT_SCSI_DONE_WITH_ERROR;
1760    }
1761
1762    cmd->iov_size = lba_count * sdev->blocksize;
1763    if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1764        megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1765        cmd->frame->header.scsi_status = CHECK_CONDITION;
1766        s->event_count++;
1767        return MFI_STAT_SCSI_DONE_WITH_ERROR;
1768    }
1769
1770    megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1771    cmd->req = scsi_req_new(sdev, cmd->index,
1772                            cmd->frame->header.lun_id, cdb, cmd);
1773    if (!cmd->req) {
1774        trace_megasas_scsi_req_alloc_failed(
1775            mfi_frame_desc[cmd->frame->header.frame_cmd],
1776            cmd->frame->header.target_id, cmd->frame->header.lun_id);
1777        megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1778        cmd->frame->header.scsi_status = BUSY;
1779        s->event_count++;
1780        return MFI_STAT_SCSI_DONE_WITH_ERROR;
1781    }
1782    len = megasas_enqueue_req(cmd, is_write);
1783    if (len > 0) {
1784        if (is_write) {
1785            trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1786        } else {
1787            trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1788        }
1789    }
1790    return MFI_STAT_INVALID_STATUS;
1791}
1792
1793static int megasas_finish_internal_command(MegasasCmd *cmd,
1794                                           SCSIRequest *req, size_t resid)
1795{
1796    int retval = MFI_STAT_INVALID_CMD;
1797
1798    if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1799        cmd->iov_size -= resid;
1800        retval = megasas_finish_internal_dcmd(cmd, req);
1801    }
1802    return retval;
1803}
1804
1805static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1806{
1807    MegasasCmd *cmd = req->hba_private;
1808
1809    if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1810        return NULL;
1811    } else {
1812        return &cmd->qsg;
1813    }
1814}
1815
1816static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1817{
1818    MegasasCmd *cmd = req->hba_private;
1819    uint8_t *buf;
1820    uint32_t opcode;
1821
1822    trace_megasas_io_complete(cmd->index, len);
1823
1824    if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
1825        scsi_req_continue(req);
1826        return;
1827    }
1828
1829    buf = scsi_req_get_buf(req);
1830    opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1831    if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1832        struct mfi_pd_info *info = cmd->iov_buf;
1833
1834        if (info->inquiry_data[0] == 0x7f) {
1835            memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1836            memcpy(info->inquiry_data, buf, len);
1837        } else if (info->vpd_page83[0] == 0x7f) {
1838            memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1839            memcpy(info->vpd_page83, buf, len);
1840        }
1841        scsi_req_continue(req);
1842    } else if (opcode == MFI_DCMD_LD_GET_INFO) {
1843        struct mfi_ld_info *info = cmd->iov_buf;
1844
1845        if (cmd->iov_buf) {
1846            memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1847            scsi_req_continue(req);
1848        }
1849    }
1850}
1851
1852static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1853                                     size_t resid)
1854{
1855    MegasasCmd *cmd = req->hba_private;
1856    uint8_t cmd_status = MFI_STAT_OK;
1857
1858    trace_megasas_command_complete(cmd->index, status, resid);
1859
1860    if (cmd->req != req) {
1861        /*
1862         * Internal command complete
1863         */
1864        cmd_status = megasas_finish_internal_command(cmd, req, resid);
1865        if (cmd_status == MFI_STAT_INVALID_STATUS) {
1866            return;
1867        }
1868    } else {
1869        req->status = status;
1870        trace_megasas_scsi_complete(cmd->index, req->status,
1871                                    cmd->iov_size, req->cmd.xfer);
1872        if (req->status != GOOD) {
1873            cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1874        }
1875        if (req->status == CHECK_CONDITION) {
1876            megasas_copy_sense(cmd);
1877        }
1878
1879        megasas_unmap_sgl(cmd);
1880        cmd->frame->header.scsi_status = req->status;
1881        scsi_req_unref(cmd->req);
1882        cmd->req = NULL;
1883    }
1884    cmd->frame->header.cmd_status = cmd_status;
1885    megasas_unmap_frame(cmd->state, cmd);
1886    megasas_complete_frame(cmd->state, cmd->context);
1887}
1888
1889static void megasas_command_cancel(SCSIRequest *req)
1890{
1891    MegasasCmd *cmd = req->hba_private;
1892
1893    if (cmd) {
1894        megasas_abort_command(cmd);
1895    } else {
1896        scsi_req_unref(req);
1897    }
1898}
1899
1900static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1901{
1902    uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
1903    hwaddr abort_addr, addr_hi, addr_lo;
1904    MegasasCmd *abort_cmd;
1905
1906    addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1907    addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1908    abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1909
1910    abort_cmd = megasas_lookup_frame(s, abort_addr);
1911    if (!abort_cmd) {
1912        trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1913        s->event_count++;
1914        return MFI_STAT_OK;
1915    }
1916    if (!megasas_use_queue64(s)) {
1917        abort_ctx &= (uint64_t)0xFFFFFFFF;
1918    }
1919    if (abort_cmd->context != abort_ctx) {
1920        trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index,
1921                                            abort_cmd->context);
1922        s->event_count++;
1923        return MFI_STAT_ABORT_NOT_POSSIBLE;
1924    }
1925    trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1926    megasas_abort_command(abort_cmd);
1927    if (!s->event_cmd || abort_cmd != s->event_cmd) {
1928        s->event_cmd = NULL;
1929    }
1930    s->event_count++;
1931    return MFI_STAT_OK;
1932}
1933
1934static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1935                                 uint32_t frame_count)
1936{
1937    uint8_t frame_status = MFI_STAT_INVALID_CMD;
1938    uint64_t frame_context;
1939    MegasasCmd *cmd;
1940
1941    /*
1942     * Always read 64bit context, top bits will be
1943     * masked out if required in megasas_enqueue_frame()
1944     */
1945    frame_context = megasas_frame_get_context(s, frame_addr);
1946
1947    cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1948    if (!cmd) {
1949        /* reply queue full */
1950        trace_megasas_frame_busy(frame_addr);
1951        megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1952        megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1953        megasas_complete_frame(s, frame_context);
1954        s->event_count++;
1955        return;
1956    }
1957    switch (cmd->frame->header.frame_cmd) {
1958    case MFI_CMD_INIT:
1959        frame_status = megasas_init_firmware(s, cmd);
1960        break;
1961    case MFI_CMD_DCMD:
1962        frame_status = megasas_handle_dcmd(s, cmd);
1963        break;
1964    case MFI_CMD_ABORT:
1965        frame_status = megasas_handle_abort(s, cmd);
1966        break;
1967    case MFI_CMD_PD_SCSI_IO:
1968        frame_status = megasas_handle_scsi(s, cmd, 0);
1969        break;
1970    case MFI_CMD_LD_SCSI_IO:
1971        frame_status = megasas_handle_scsi(s, cmd, 1);
1972        break;
1973    case MFI_CMD_LD_READ:
1974    case MFI_CMD_LD_WRITE:
1975        frame_status = megasas_handle_io(s, cmd);
1976        break;
1977    default:
1978        trace_megasas_unhandled_frame_cmd(cmd->index,
1979                                          cmd->frame->header.frame_cmd);
1980        s->event_count++;
1981        break;
1982    }
1983    if (frame_status != MFI_STAT_INVALID_STATUS) {
1984        cmd->frame->header.cmd_status = frame_status;
1985        megasas_unmap_frame(s, cmd);
1986        megasas_complete_frame(s, cmd->context);
1987    }
1988}
1989
1990static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
1991                                  unsigned size)
1992{
1993    MegasasState *s = opaque;
1994    PCIDevice *pci_dev = PCI_DEVICE(s);
1995    MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
1996    uint32_t retval = 0;
1997
1998    switch (addr) {
1999    case MFI_IDB:
2000        retval = 0;
2001        trace_megasas_mmio_readl("MFI_IDB", retval);
2002        break;
2003    case MFI_OMSG0:
2004    case MFI_OSP0:
2005        retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
2006            (s->fw_state & MFI_FWSTATE_MASK) |
2007            ((s->fw_sge & 0xff) << 16) |
2008            (s->fw_cmds & 0xFFFF);
2009        trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2010                                 retval);
2011        break;
2012    case MFI_OSTS:
2013        if (megasas_intr_enabled(s) && s->doorbell) {
2014            retval = base_class->osts;
2015        }
2016        trace_megasas_mmio_readl("MFI_OSTS", retval);
2017        break;
2018    case MFI_OMSK:
2019        retval = s->intr_mask;
2020        trace_megasas_mmio_readl("MFI_OMSK", retval);
2021        break;
2022    case MFI_ODCR0:
2023        retval = s->doorbell ? 1 : 0;
2024        trace_megasas_mmio_readl("MFI_ODCR0", retval);
2025        break;
2026    case MFI_DIAG:
2027        retval = s->diag;
2028        trace_megasas_mmio_readl("MFI_DIAG", retval);
2029        break;
2030    case MFI_OSP1:
2031        retval = 15;
2032        trace_megasas_mmio_readl("MFI_OSP1", retval);
2033        break;
2034    default:
2035        trace_megasas_mmio_invalid_readl(addr);
2036        break;
2037    }
2038    return retval;
2039}
2040
2041static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2042
2043static void megasas_mmio_write(void *opaque, hwaddr addr,
2044                               uint64_t val, unsigned size)
2045{
2046    MegasasState *s = opaque;
2047    PCIDevice *pci_dev = PCI_DEVICE(s);
2048    uint64_t frame_addr;
2049    uint32_t frame_count;
2050    int i;
2051
2052    switch (addr) {
2053    case MFI_IDB:
2054        trace_megasas_mmio_writel("MFI_IDB", val);
2055        if (val & MFI_FWINIT_ABORT) {
2056            /* Abort all pending cmds */
2057            for (i = 0; i < s->fw_cmds; i++) {
2058                megasas_abort_command(&s->frames[i]);
2059            }
2060        }
2061        if (val & MFI_FWINIT_READY) {
2062            /* move to FW READY */
2063            megasas_soft_reset(s);
2064        }
2065        if (val & MFI_FWINIT_MFIMODE) {
2066            /* discard MFIs */
2067        }
2068        if (val & MFI_FWINIT_STOP_ADP) {
2069            /* Terminal error, stop processing */
2070            s->fw_state = MFI_FWSTATE_FAULT;
2071        }
2072        break;
2073    case MFI_OMSK:
2074        trace_megasas_mmio_writel("MFI_OMSK", val);
2075        s->intr_mask = val;
2076        if (!megasas_intr_enabled(s) &&
2077            !msi_enabled(pci_dev) &&
2078            !msix_enabled(pci_dev)) {
2079            trace_megasas_irq_lower();
2080            pci_irq_deassert(pci_dev);
2081        }
2082        if (megasas_intr_enabled(s)) {
2083            if (msix_enabled(pci_dev)) {
2084                trace_megasas_msix_enabled(0);
2085            } else if (msi_enabled(pci_dev)) {
2086                trace_megasas_msi_enabled(0);
2087            } else {
2088                trace_megasas_intr_enabled();
2089            }
2090        } else {
2091            trace_megasas_intr_disabled();
2092            megasas_soft_reset(s);
2093        }
2094        break;
2095    case MFI_ODCR0:
2096        trace_megasas_mmio_writel("MFI_ODCR0", val);
2097        s->doorbell = 0;
2098        if (megasas_intr_enabled(s)) {
2099            if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
2100                trace_megasas_irq_lower();
2101                pci_irq_deassert(pci_dev);
2102            }
2103        }
2104        break;
2105    case MFI_IQPH:
2106        trace_megasas_mmio_writel("MFI_IQPH", val);
2107        /* Received high 32 bits of a 64 bit MFI frame address */
2108        s->frame_hi = val;
2109        break;
2110    case MFI_IQPL:
2111        trace_megasas_mmio_writel("MFI_IQPL", val);
2112        /* Received low 32 bits of a 64 bit MFI frame address */
2113        /* Fallthrough */
2114    case MFI_IQP:
2115        if (addr == MFI_IQP) {
2116            trace_megasas_mmio_writel("MFI_IQP", val);
2117            /* Received 64 bit MFI frame address */
2118            s->frame_hi = 0;
2119        }
2120        frame_addr = (val & ~0x1F);
2121        /* Add possible 64 bit offset */
2122        frame_addr |= ((uint64_t)s->frame_hi << 32);
2123        s->frame_hi = 0;
2124        frame_count = (val >> 1) & 0xF;
2125        megasas_handle_frame(s, frame_addr, frame_count);
2126        break;
2127    case MFI_SEQ:
2128        trace_megasas_mmio_writel("MFI_SEQ", val);
2129        /* Magic sequence to start ADP reset */
2130        if (adp_reset_seq[s->adp_reset] == val) {
2131            s->adp_reset++;
2132        } else {
2133            s->adp_reset = 0;
2134            s->diag = 0;
2135        }
2136        if (s->adp_reset == 6) {
2137            s->diag = MFI_DIAG_WRITE_ENABLE;
2138        }
2139        break;
2140    case MFI_DIAG:
2141        trace_megasas_mmio_writel("MFI_DIAG", val);
2142        /* ADP reset */
2143        if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2144            (val & MFI_DIAG_RESET_ADP)) {
2145            s->diag |= MFI_DIAG_RESET_ADP;
2146            megasas_soft_reset(s);
2147            s->adp_reset = 0;
2148            s->diag = 0;
2149        }
2150        break;
2151    default:
2152        trace_megasas_mmio_invalid_writel(addr, val);
2153        break;
2154    }
2155}
2156
2157static const MemoryRegionOps megasas_mmio_ops = {
2158    .read = megasas_mmio_read,
2159    .write = megasas_mmio_write,
2160    .endianness = DEVICE_LITTLE_ENDIAN,
2161    .impl = {
2162        .min_access_size = 8,
2163        .max_access_size = 8,
2164    }
2165};
2166
2167static uint64_t megasas_port_read(void *opaque, hwaddr addr,
2168                                  unsigned size)
2169{
2170    return megasas_mmio_read(opaque, addr & 0xff, size);
2171}
2172
2173static void megasas_port_write(void *opaque, hwaddr addr,
2174                               uint64_t val, unsigned size)
2175{
2176    megasas_mmio_write(opaque, addr & 0xff, val, size);
2177}
2178
2179static const MemoryRegionOps megasas_port_ops = {
2180    .read = megasas_port_read,
2181    .write = megasas_port_write,
2182    .endianness = DEVICE_LITTLE_ENDIAN,
2183    .impl = {
2184        .min_access_size = 4,
2185        .max_access_size = 4,
2186    }
2187};
2188
2189static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
2190                                   unsigned size)
2191{
2192    return 0;
2193}
2194
2195static void megasas_queue_write(void *opaque, hwaddr addr,
2196                               uint64_t val, unsigned size)
2197{
2198    return;
2199}
2200
2201static const MemoryRegionOps megasas_queue_ops = {
2202    .read = megasas_queue_read,
2203    .write = megasas_queue_write,
2204    .endianness = DEVICE_LITTLE_ENDIAN,
2205    .impl = {
2206        .min_access_size = 8,
2207        .max_access_size = 8,
2208    }
2209};
2210
2211static void megasas_soft_reset(MegasasState *s)
2212{
2213    int i;
2214    MegasasCmd *cmd;
2215
2216    trace_megasas_reset(s->fw_state);
2217    for (i = 0; i < s->fw_cmds; i++) {
2218        cmd = &s->frames[i];
2219        megasas_abort_command(cmd);
2220    }
2221    if (s->fw_state == MFI_FWSTATE_READY) {
2222        BusChild *kid;
2223
2224        /*
2225         * The EFI firmware doesn't handle UA,
2226         * so we need to clear the Power On/Reset UA
2227         * after the initial reset.
2228         */
2229        QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2230            SCSIDevice *sdev = SCSI_DEVICE(kid->child);
2231
2232            sdev->unit_attention = SENSE_CODE(NO_SENSE);
2233            scsi_device_unit_attention_reported(sdev);
2234        }
2235    }
2236    megasas_reset_frames(s);
2237    s->reply_queue_len = s->fw_cmds;
2238    s->reply_queue_pa = 0;
2239    s->consumer_pa = 0;
2240    s->producer_pa = 0;
2241    s->fw_state = MFI_FWSTATE_READY;
2242    s->doorbell = 0;
2243    s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2244    s->frame_hi = 0;
2245    s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2246    s->event_count++;
2247    s->boot_event = s->event_count;
2248}
2249
2250static void megasas_scsi_reset(DeviceState *dev)
2251{
2252    MegasasState *s = MEGASAS(dev);
2253
2254    megasas_soft_reset(s);
2255}
2256
2257static const VMStateDescription vmstate_megasas_gen1 = {
2258    .name = "megasas",
2259    .version_id = 0,
2260    .minimum_version_id = 0,
2261    .fields = (VMStateField[]) {
2262        VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2263        VMSTATE_MSIX(parent_obj, MegasasState),
2264
2265        VMSTATE_INT32(fw_state, MegasasState),
2266        VMSTATE_INT32(intr_mask, MegasasState),
2267        VMSTATE_INT32(doorbell, MegasasState),
2268        VMSTATE_UINT64(reply_queue_pa, MegasasState),
2269        VMSTATE_UINT64(consumer_pa, MegasasState),
2270        VMSTATE_UINT64(producer_pa, MegasasState),
2271        VMSTATE_END_OF_LIST()
2272    }
2273};
2274
2275static const VMStateDescription vmstate_megasas_gen2 = {
2276    .name = "megasas-gen2",
2277    .version_id = 0,
2278    .minimum_version_id = 0,
2279    .minimum_version_id_old = 0,
2280    .fields      = (VMStateField[]) {
2281        VMSTATE_PCIE_DEVICE(parent_obj, MegasasState),
2282        VMSTATE_MSIX(parent_obj, MegasasState),
2283
2284        VMSTATE_INT32(fw_state, MegasasState),
2285        VMSTATE_INT32(intr_mask, MegasasState),
2286        VMSTATE_INT32(doorbell, MegasasState),
2287        VMSTATE_UINT64(reply_queue_pa, MegasasState),
2288        VMSTATE_UINT64(consumer_pa, MegasasState),
2289        VMSTATE_UINT64(producer_pa, MegasasState),
2290        VMSTATE_END_OF_LIST()
2291    }
2292};
2293
2294static void megasas_scsi_uninit(PCIDevice *d)
2295{
2296    MegasasState *s = MEGASAS(d);
2297
2298    if (megasas_use_msix(s)) {
2299        msix_uninit(d, &s->mmio_io, &s->mmio_io);
2300    }
2301    msi_uninit(d);
2302}
2303
2304static const struct SCSIBusInfo megasas_scsi_info = {
2305    .tcq = true,
2306    .max_target = MFI_MAX_LD,
2307    .max_lun = 255,
2308
2309    .transfer_data = megasas_xfer_complete,
2310    .get_sg_list = megasas_get_sg_list,
2311    .complete = megasas_command_complete,
2312    .cancel = megasas_command_cancel,
2313};
2314
2315static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
2316{
2317    DeviceState *d = DEVICE(dev);
2318    MegasasState *s = MEGASAS(dev);
2319    MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
2320    uint8_t *pci_conf;
2321    int i, bar_type;
2322    Error *err = NULL;
2323    int ret;
2324
2325    pci_conf = dev->config;
2326
2327    /* PCI latency timer = 0 */
2328    pci_conf[PCI_LATENCY_TIMER] = 0;
2329    /* Interrupt pin 1 */
2330    pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2331
2332    if (s->msi != ON_OFF_AUTO_OFF) {
2333        ret = msi_init(dev, 0x50, 1, true, false, &err);
2334        /* Any error other than -ENOTSUP(board's MSI support is broken)
2335         * is a programming error */
2336        assert(!ret || ret == -ENOTSUP);
2337        if (ret && s->msi == ON_OFF_AUTO_ON) {
2338            /* Can't satisfy user's explicit msi=on request, fail */
2339            error_append_hint(&err, "You have to use msi=auto (default) or "
2340                    "msi=off with this machine type.\n");
2341            error_propagate(errp, err);
2342            return;
2343        } else if (ret) {
2344            /* With msi=auto, we fall back to MSI off silently */
2345            s->msi = ON_OFF_AUTO_OFF;
2346            error_free(err);
2347        }
2348    }
2349
2350    memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
2351                          "megasas-mmio", 0x4000);
2352    memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
2353                          "megasas-io", 256);
2354    memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
2355                          "megasas-queue", 0x40000);
2356
2357    if (megasas_use_msix(s) &&
2358        msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2359                  &s->mmio_io, b->mmio_bar, 0x3800, 0x68)) {
2360        s->msix = ON_OFF_AUTO_OFF;
2361    }
2362    if (pci_is_express(dev)) {
2363        pcie_endpoint_cap_init(dev, 0xa0);
2364    }
2365
2366    bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
2367    pci_register_bar(dev, b->ioport_bar,
2368                     PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2369    pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
2370    pci_register_bar(dev, 3, bar_type, &s->queue_io);
2371
2372    if (megasas_use_msix(s)) {
2373        msix_vector_use(dev, 0);
2374    }
2375
2376    s->fw_state = MFI_FWSTATE_READY;
2377    if (!s->sas_addr) {
2378        s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2379                       IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2380        s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2381        s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2382        s->sas_addr |= PCI_FUNC(dev->devfn);
2383    }
2384    if (!s->hba_serial) {
2385        s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
2386    }
2387    if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2388        s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2389    } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2390        s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2391    } else {
2392        s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2393    }
2394    if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2395        s->fw_cmds = MEGASAS_MAX_FRAMES;
2396    }
2397    trace_megasas_init(s->fw_sge, s->fw_cmds,
2398                       megasas_is_jbod(s) ? "jbod" : "raid");
2399
2400    if (megasas_is_jbod(s)) {
2401        s->fw_luns = MFI_MAX_SYS_PDS;
2402    } else {
2403        s->fw_luns = MFI_MAX_LD;
2404    }
2405    s->producer_pa = 0;
2406    s->consumer_pa = 0;
2407    for (i = 0; i < s->fw_cmds; i++) {
2408        s->frames[i].index = i;
2409        s->frames[i].context = -1;
2410        s->frames[i].pa = 0;
2411        s->frames[i].state = s;
2412    }
2413
2414    scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2415                 &megasas_scsi_info, NULL);
2416    if (!d->hotplugged) {
2417        scsi_bus_legacy_handle_cmdline(&s->bus, errp);
2418    }
2419}
2420
2421static Property megasas_properties_gen1[] = {
2422    DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2423                       MEGASAS_DEFAULT_SGE),
2424    DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2425                       MEGASAS_DEFAULT_FRAMES),
2426    DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2427    DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2428    DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2429    DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2430    DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2431                    MEGASAS_FLAG_USE_JBOD, false),
2432    DEFINE_PROP_END_OF_LIST(),
2433};
2434
2435static Property megasas_properties_gen2[] = {
2436    DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2437                       MEGASAS_DEFAULT_SGE),
2438    DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2439                       MEGASAS_GEN2_DEFAULT_FRAMES),
2440    DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2441    DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2442    DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2443    DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2444    DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2445                    MEGASAS_FLAG_USE_JBOD, false),
2446    DEFINE_PROP_END_OF_LIST(),
2447};
2448
2449typedef struct MegasasInfo {
2450    const char *name;
2451    const char *desc;
2452    const char *product_name;
2453    const char *product_version;
2454    uint16_t device_id;
2455    uint16_t subsystem_id;
2456    int ioport_bar;
2457    int mmio_bar;
2458    bool is_express;
2459    int osts;
2460    const VMStateDescription *vmsd;
2461    Property *props;
2462} MegasasInfo;
2463
2464static struct MegasasInfo megasas_devices[] = {
2465    {
2466        .name = TYPE_MEGASAS_GEN1,
2467        .desc = "LSI MegaRAID SAS 1078",
2468        .product_name = "LSI MegaRAID SAS 8708EM2",
2469        .product_version = MEGASAS_VERSION_GEN1,
2470        .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2471        .subsystem_id = 0x1013,
2472        .ioport_bar = 2,
2473        .mmio_bar = 0,
2474        .osts = MFI_1078_RM | 1,
2475        .is_express = false,
2476        .vmsd = &vmstate_megasas_gen1,
2477        .props = megasas_properties_gen1,
2478    },{
2479        .name = TYPE_MEGASAS_GEN2,
2480        .desc = "LSI MegaRAID SAS 2108",
2481        .product_name = "LSI MegaRAID SAS 9260-8i",
2482        .product_version = MEGASAS_VERSION_GEN2,
2483        .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2484        .subsystem_id = 0x9261,
2485        .ioport_bar = 0,
2486        .mmio_bar = 1,
2487        .osts = MFI_GEN2_RM,
2488        .is_express = true,
2489        .vmsd = &vmstate_megasas_gen2,
2490        .props = megasas_properties_gen2,
2491    }
2492};
2493
2494static void megasas_class_init(ObjectClass *oc, void *data)
2495{
2496    DeviceClass *dc = DEVICE_CLASS(oc);
2497    PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2498    MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
2499    const MegasasInfo *info = data;
2500
2501    pc->realize = megasas_scsi_realize;
2502    pc->exit = megasas_scsi_uninit;
2503    pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2504    pc->device_id = info->device_id;
2505    pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2506    pc->subsystem_id = info->subsystem_id;
2507    pc->class_id = PCI_CLASS_STORAGE_RAID;
2508    pc->is_express = info->is_express;
2509    e->mmio_bar = info->mmio_bar;
2510    e->ioport_bar = info->ioport_bar;
2511    e->osts = info->osts;
2512    e->product_name = info->product_name;
2513    e->product_version = info->product_version;
2514    dc->props = info->props;
2515    dc->reset = megasas_scsi_reset;
2516    dc->vmsd = info->vmsd;
2517    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2518    dc->desc = info->desc;
2519}
2520
2521static const TypeInfo megasas_info = {
2522    .name  = TYPE_MEGASAS_BASE,
2523    .parent = TYPE_PCI_DEVICE,
2524    .instance_size = sizeof(MegasasState),
2525    .class_size = sizeof(MegasasBaseClass),
2526    .abstract = true,
2527};
2528
2529static void megasas_register_types(void)
2530{
2531    int i;
2532
2533    type_register_static(&megasas_info);
2534    for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2535        const MegasasInfo *info = &megasas_devices[i];
2536        TypeInfo type_info = {};
2537
2538        type_info.name = info->name;
2539        type_info.parent = TYPE_MEGASAS_BASE;
2540        type_info.class_data = (void *)info;
2541        type_info.class_init = megasas_class_init;
2542
2543        type_register(&type_info);
2544    }
2545}
2546
2547type_init(megasas_register_types)
2548