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22#ifndef HW_Q35_H
23#define HW_Q35_H
24
25#include "hw/hw.h"
26#include "hw/isa/isa.h"
27#include "hw/sysbus.h"
28#include "hw/i386/pc.h"
29#include "hw/isa/apm.h"
30#include "hw/pci/pci.h"
31#include "hw/pci/pcie_host.h"
32#include "hw/acpi/acpi.h"
33#include "hw/acpi/ich9.h"
34#include "hw/pci-host/pam.h"
35#include "hw/i386/intel_iommu.h"
36
37#define TYPE_Q35_HOST_DEVICE "q35-pcihost"
38#define Q35_HOST_DEVICE(obj) \
39 OBJECT_CHECK(Q35PCIHost, (obj), TYPE_Q35_HOST_DEVICE)
40
41#define TYPE_MCH_PCI_DEVICE "mch"
42#define MCH_PCI_DEVICE(obj) \
43 OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE)
44
45typedef struct MCHPCIState {
46
47 PCIDevice parent_obj;
48
49
50 MemoryRegion *ram_memory;
51 MemoryRegion *pci_address_space;
52 MemoryRegion *system_memory;
53 MemoryRegion *address_space_io;
54 PAMMemoryRegion pam_regions[13];
55 MemoryRegion smram_region, open_high_smram;
56 MemoryRegion smram, low_smram, high_smram;
57 MemoryRegion tseg_blackhole, tseg_window;
58 Range pci_hole;
59 uint64_t below_4g_mem_size;
60 uint64_t above_4g_mem_size;
61 uint64_t pci_hole64_size;
62 uint32_t short_root_bus;
63} MCHPCIState;
64
65typedef struct Q35PCIHost {
66
67 PCIExpressHost parent_obj;
68
69
70 MCHPCIState mch;
71} Q35PCIHost;
72
73#define Q35_MASK(bit, ms_bit, ls_bit) \
74((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
75
76
77
78
79
80#define MCH_HOST_PROP_RAM_MEM "ram-mem"
81#define MCH_HOST_PROP_PCI_MEM "pci-mem"
82#define MCH_HOST_PROP_SYSTEM_MEM "system-mem"
83#define MCH_HOST_PROP_IO_MEM "io-mem"
84
85
86#define MCH_HOST_BRIDGE "MCH"
87
88#define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
89#define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
90
91
92#define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0
93
94#define MCH_HOST_BRIDGE_PCIEXBAR 0x60
95#define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8
96#define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000
97#define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000)
98#define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28)
99#define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26))
100#define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25))
101#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1))
102#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1))
103#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))
104#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1))
105#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1))
106#define MCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
107
108#define MCH_HOST_BRIDGE_PAM_NB 7
109#define MCH_HOST_BRIDGE_PAM_SIZE 7
110#define MCH_HOST_BRIDGE_PAM0 0x90
111#define MCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
112#define MCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000
113#define MCH_HOST_BRIDGE_PAM1 0x91
114#define MCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
115#define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000
116#define MCH_HOST_BRIDGE_PAM2 0x92
117#define MCH_HOST_BRIDGE_PAM3 0x93
118#define MCH_HOST_BRIDGE_PAM4 0x94
119#define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
120#define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000
121#define MCH_HOST_BRIDGE_PAM5 0x95
122#define MCH_HOST_BRIDGE_PAM6 0x96
123#define MCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
124#define MCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
125#define MCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
126#define MCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
127#define MCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
128#define MCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
129#define MCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
130#define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
131#define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
132
133#define MCH_HOST_BRIDGE_SMRAM 0x9d
134#define MCH_HOST_BRIDGE_SMRAM_SIZE 2
135#define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
136#define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
137#define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4))
138#define MCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3))
139#define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
140#define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2)
141#define MCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000
142#define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000
143#define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
144#define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
145#define MCH_HOST_BRIDGE_SMRAM_DEFAULT \
146 MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG
147#define MCH_HOST_BRIDGE_SMRAM_WMASK \
148 (MCH_HOST_BRIDGE_SMRAM_D_OPEN | \
149 MCH_HOST_BRIDGE_SMRAM_D_CLS | \
150 MCH_HOST_BRIDGE_SMRAM_D_LCK | \
151 MCH_HOST_BRIDGE_SMRAM_G_SMRAME)
152#define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK \
153 MCH_HOST_BRIDGE_SMRAM_D_CLS
154
155#define MCH_HOST_BRIDGE_ESMRAMC 0x9e
156#define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7))
157#define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 6))
158#define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 5))
159#define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 4))
160#define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 3))
161#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
162#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
163#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
164#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
165#define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1)
166#define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \
167 (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \
168 MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \
169 MCH_HOST_BRIDGE_ESMRAMC_SM_L2)
170#define MCH_HOST_BRIDGE_ESMRAMC_WMASK \
171 (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \
172 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \
173 MCH_HOST_BRIDGE_ESMRAMC_T_EN)
174#define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK 0
175
176
177#define MCH_PCIE_DEV 1
178#define MCH_PCIE_FUNC 0
179
180uint64_t mch_mcfg_base(void);
181
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185
186
187#define Q35_PSEUDO_BUS_PLATFORM (0xff)
188#define Q35_PSEUDO_DEVFN_IOAPIC (0x00)
189
190#endif
191
