1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef QEMU_ARM_CPU_QOM_H
21#define QEMU_ARM_CPU_QOM_H
22
23#include "qom/cpu.h"
24
25struct arm_boot_info;
26
27#define TYPE_ARM_CPU "arm-cpu"
28
29#define ARM_CPU_CLASS(klass) \
30 OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
31#define ARM_CPU(obj) \
32 OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
33#define ARM_CPU_GET_CLASS(obj) \
34 OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
35
36
37
38
39
40
41
42
43typedef struct ARMCPUClass {
44
45 CPUClass parent_class;
46
47
48 DeviceRealize parent_realize;
49 void (*parent_reset)(CPUState *cpu);
50} ARMCPUClass;
51
52typedef struct ARMCPU ARMCPU;
53
54#define TYPE_AARCH64_CPU "aarch64-cpu"
55#define AARCH64_CPU_CLASS(klass) \
56 OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
57#define AARCH64_CPU_GET_CLASS(obj) \
58 OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
59
60typedef struct AArch64CPUClass {
61
62 ARMCPUClass parent_class;
63
64} AArch64CPUClass;
65
66void register_cp_regs_for_features(ARMCPU *cpu);
67void init_cpreg_list(ARMCPU *cpu);
68
69
70void arm_gt_ptimer_cb(void *opaque);
71void arm_gt_vtimer_cb(void *opaque);
72void arm_gt_htimer_cb(void *opaque);
73void arm_gt_stimer_cb(void *opaque);
74
75#define ARM_AFF0_SHIFT 0
76#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
77#define ARM_AFF1_SHIFT 8
78#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
79#define ARM_AFF2_SHIFT 16
80#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
81#define ARM_AFF3_SHIFT 32
82#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
83
84#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
85#define ARM64_AFFINITY_MASK \
86 (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
87
88#endif
89