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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "cpu.h"
27#include "qemu-common.h"
28#include "hw/qdev-properties.h"
29#include "migration/vmstate.h"
30#include "exec/exec-all.h"
31
32static const struct {
33 const char *name;
34 uint8_t version_id;
35} mb_cpu_lookup[] = {
36
37 {"5.00.a", 0x01},
38 {"5.00.b", 0x02},
39 {"5.00.c", 0x03},
40 {"6.00.a", 0x04},
41 {"6.00.b", 0x06},
42 {"7.00.a", 0x05},
43 {"7.00.b", 0x07},
44 {"7.10.a", 0x08},
45 {"7.10.b", 0x09},
46 {"7.10.c", 0x0a},
47 {"7.10.d", 0x0b},
48 {"7.20.a", 0x0c},
49 {"7.20.b", 0x0d},
50 {"7.20.c", 0x0e},
51 {"7.20.d", 0x0f},
52 {"7.30.a", 0x10},
53 {"7.30.b", 0x11},
54 {"8.00.a", 0x12},
55 {"8.00.b", 0x13},
56 {"8.10.a", 0x14},
57 {"8.20.a", 0x15},
58 {"8.20.b", 0x16},
59 {"8.30.a", 0x17},
60 {"8.40.a", 0x18},
61 {"8.40.b", 0x19},
62 {"8.50.a", 0x1A},
63 {"9.0", 0x1B},
64 {"9.1", 0x1D},
65 {"9.2", 0x1F},
66 {"9.3", 0x20},
67 {NULL, 0},
68};
69
70static void mb_cpu_set_pc(CPUState *cs, vaddr value)
71{
72 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
73
74 cpu->env.sregs[SR_PC] = value;
75}
76
77static bool mb_cpu_has_work(CPUState *cs)
78{
79 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
80}
81
82#ifndef CONFIG_USER_ONLY
83static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
84{
85 MicroBlazeCPU *cpu = opaque;
86 CPUState *cs = CPU(cpu);
87 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
88
89 if (level) {
90 cpu_interrupt(cs, type);
91 } else {
92 cpu_reset_interrupt(cs, type);
93 }
94}
95#endif
96
97
98static void mb_cpu_reset(CPUState *s)
99{
100 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
101 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
102 CPUMBState *env = &cpu->env;
103
104 mcc->parent_reset(s);
105
106 memset(env, 0, offsetof(CPUMBState, pvr));
107 env->res_addr = RES_ADDR_NONE;
108 tlb_flush(s, 1);
109
110
111 env->shr = ~0;
112
113 env->sregs[SR_PC] = cpu->cfg.base_vectors;
114
115#if defined(CONFIG_USER_ONLY)
116
117 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
118#else
119 env->sregs[SR_MSR] = 0;
120 mmu_init(&env->mmu);
121 env->mmu.c_mmu = 3;
122 env->mmu.c_mmu_tlb_access = 3;
123 env->mmu.c_mmu_zones = 16;
124#endif
125}
126
127static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
128{
129 info->mach = bfd_arch_microblaze;
130 info->print_insn = print_insn_microblaze;
131}
132
133static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
134{
135 CPUState *cs = CPU(dev);
136 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
137 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
138 CPUMBState *env = &cpu->env;
139 uint8_t version_code = 0;
140 int i = 0;
141
142 qemu_init_vcpu(cs);
143
144 env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
145 | PVR0_USE_DIV_MASK \
146 | PVR0_USE_HW_MUL_MASK \
147 | PVR0_USE_EXC_MASK \
148 | PVR0_USE_ICACHE_MASK \
149 | PVR0_USE_DCACHE_MASK \
150 | (0xb << 8);
151 env->pvr.regs[2] = PVR2_D_OPB_MASK \
152 | PVR2_D_LMB_MASK \
153 | PVR2_I_OPB_MASK \
154 | PVR2_I_LMB_MASK \
155 | PVR2_USE_MSR_INSTR \
156 | PVR2_USE_PCMP_INSTR \
157 | PVR2_USE_BARREL_MASK \
158 | PVR2_USE_DIV_MASK \
159 | PVR2_USE_HW_MUL_MASK \
160 | PVR2_USE_MUL64_MASK \
161 | PVR2_FPU_EXC_MASK \
162 | 0;
163
164 for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
165 if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
166 version_code = mb_cpu_lookup[i].version_id;
167 break;
168 }
169 }
170
171 if (!version_code) {
172 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
173 }
174
175 env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
176 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
177 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
178 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
179 (version_code << 16) |
180 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
181
182 env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
183 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
184
185 env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
186 PVR5_DCACHE_WRITEBACK_MASK : 0;
187
188 env->pvr.regs[10] = 0x0c000000;
189 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
190
191 mcc->parent_realize(dev, errp);
192}
193
194static void mb_cpu_initfn(Object *obj)
195{
196 CPUState *cs = CPU(obj);
197 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
198 CPUMBState *env = &cpu->env;
199 static bool tcg_initialized;
200
201 cs->env_ptr = env;
202 cpu_exec_init(cs, &error_abort);
203
204 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
205
206#ifndef CONFIG_USER_ONLY
207
208 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
209#endif
210
211 if (tcg_enabled() && !tcg_initialized) {
212 tcg_initialized = true;
213 mb_tcg_init();
214 }
215}
216
217static const VMStateDescription vmstate_mb_cpu = {
218 .name = "cpu",
219 .unmigratable = 1,
220};
221
222static Property mb_properties[] = {
223 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
224 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
225 false),
226
227
228
229
230 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
231 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
232 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
233 false),
234 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
235 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
236 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
237 DEFINE_PROP_END_OF_LIST(),
238};
239
240static void mb_cpu_class_init(ObjectClass *oc, void *data)
241{
242 DeviceClass *dc = DEVICE_CLASS(oc);
243 CPUClass *cc = CPU_CLASS(oc);
244 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
245
246 mcc->parent_realize = dc->realize;
247 dc->realize = mb_cpu_realizefn;
248
249 mcc->parent_reset = cc->reset;
250 cc->reset = mb_cpu_reset;
251
252 cc->has_work = mb_cpu_has_work;
253 cc->do_interrupt = mb_cpu_do_interrupt;
254 cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
255 cc->dump_state = mb_cpu_dump_state;
256 cc->set_pc = mb_cpu_set_pc;
257 cc->gdb_read_register = mb_cpu_gdb_read_register;
258 cc->gdb_write_register = mb_cpu_gdb_write_register;
259#ifdef CONFIG_USER_ONLY
260 cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
261#else
262 cc->do_unassigned_access = mb_cpu_unassigned_access;
263 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
264#endif
265 dc->vmsd = &vmstate_mb_cpu;
266 dc->props = mb_properties;
267 cc->gdb_num_core_regs = 32 + 5;
268
269 cc->disas_set_info = mb_disas_set_info;
270
271
272
273
274
275 dc->cannot_destroy_with_object_finalize_yet = true;
276}
277
278static const TypeInfo mb_cpu_type_info = {
279 .name = TYPE_MICROBLAZE_CPU,
280 .parent = TYPE_CPU,
281 .instance_size = sizeof(MicroBlazeCPU),
282 .instance_init = mb_cpu_initfn,
283 .class_size = sizeof(MicroBlazeCPUClass),
284 .class_init = mb_cpu_class_init,
285};
286
287static void mb_cpu_register_types(void)
288{
289 type_register_static(&mb_cpu_type_info);
290}
291
292type_init(mb_cpu_register_types)
293
