LXR qemu/target-ppc/cpu-qom.h

   1/*
   2 * QEMU PowerPC CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20#ifndef QEMU_PPC_CPU_QOM_H
  21#define QEMU_PPC_CPU_QOM_H
  22
  23#include "qom/cpu.h"
  24
  25#ifdef TARGET_PPC64
  26#define TYPE_POWERPC_CPU "powerpc64-cpu"
  27#elif defined(TARGET_PPCEMB)
  28#define TYPE_POWERPC_CPU "embedded-powerpc-cpu"
  29#else
  30#define TYPE_POWERPC_CPU "powerpc-cpu"
  31#endif
  32
  33#define POWERPC_CPU_CLASS(klass) \
  34    OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
  35#define POWERPC_CPU(obj) \
  36    OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
  37#define POWERPC_CPU_GET_CLASS(obj) \
  38    OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
  39
  40typedef struct PowerPCCPU PowerPCCPU;
  41typedef struct CPUPPCState CPUPPCState;
  42typedef struct ppc_tb_t ppc_tb_t;
  43typedef struct ppc_dcr_t ppc_dcr_t;
  44
  45/*****************************************************************************/
  46/* MMU model                                                                 */
  47typedef enum powerpc_mmu_t powerpc_mmu_t;
  48enum powerpc_mmu_t {
  49    POWERPC_MMU_UNKNOWN    = 0x00000000,
  50    /* Standard 32 bits PowerPC MMU                            */
  51    POWERPC_MMU_32B        = 0x00000001,
  52    /* PowerPC 6xx MMU with software TLB                       */
  53    POWERPC_MMU_SOFT_6xx   = 0x00000002,
  54    /* PowerPC 74xx MMU with software TLB                      */
  55    POWERPC_MMU_SOFT_74xx  = 0x00000003,
  56    /* PowerPC 4xx MMU with software TLB                       */
  57    POWERPC_MMU_SOFT_4xx   = 0x00000004,
  58    /* PowerPC 4xx MMU with software TLB and zones protections */
  59    POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
  60    /* PowerPC MMU in real mode only                           */
  61    POWERPC_MMU_REAL       = 0x00000006,
  62    /* Freescale MPC8xx MMU model                              */
  63    POWERPC_MMU_MPC8xx     = 0x00000007,
  64    /* BookE MMU model                                         */
  65    POWERPC_MMU_BOOKE      = 0x00000008,
  66    /* BookE 2.06 MMU model                                    */
  67    POWERPC_MMU_BOOKE206   = 0x00000009,
  68    /* PowerPC 601 MMU model (specific BATs format)            */
  69    POWERPC_MMU_601        = 0x0000000A,
  70#define POWERPC_MMU_64       0x00010000
  71#define POWERPC_MMU_1TSEG    0x00020000
  72#define POWERPC_MMU_AMR      0x00040000
  73#define POWERPC_MMU_64K      0x00080000
  74    /* 64 bits PowerPC MMU                                     */
  75    POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
  76    /* Architecture 2.03 and later (has LPCR) */
  77    POWERPC_MMU_2_03       = POWERPC_MMU_64 | 0x00000002,
  78    /* Architecture 2.06 variant                               */
  79    POWERPC_MMU_2_06       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
  80                             | POWERPC_MMU_64K
  81                             | POWERPC_MMU_AMR | 0x00000003,
  82    /* Architecture 2.06 "degraded" (no 1T segments)           */
  83    POWERPC_MMU_2_06a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
  84                             | 0x00000003,
  85    /* Architecture 2.07 variant                               */
  86    POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
  87                             | POWERPC_MMU_64K
  88                             | POWERPC_MMU_AMR | 0x00000004,
  89    /* Architecture 2.07 "degraded" (no 1T segments)           */
  90    POWERPC_MMU_2_07a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
  91                             | 0x00000004,
  92};
  93
  94/*****************************************************************************/
  95/* Exception model                                                           */
  96typedef enum powerpc_excp_t powerpc_excp_t;
  97enum powerpc_excp_t {
  98    POWERPC_EXCP_UNKNOWN   = 0,
  99    /* Standard PowerPC exception model */
 100    POWERPC_EXCP_STD,
 101    /* PowerPC 40x exception model      */
 102    POWERPC_EXCP_40x,
 103    /* PowerPC 601 exception model      */
 104    POWERPC_EXCP_601,
 105    /* PowerPC 602 exception model      */
 106    POWERPC_EXCP_602,
 107    /* PowerPC 603 exception model      */
 108    POWERPC_EXCP_603,
 109    /* PowerPC 603e exception model     */
 110    POWERPC_EXCP_603E,
 111    /* PowerPC G2 exception model       */
 112    POWERPC_EXCP_G2,
 113    /* PowerPC 604 exception model      */
 114    POWERPC_EXCP_604,
 115    /* PowerPC 7x0 exception model      */
 116    POWERPC_EXCP_7x0,
 117    /* PowerPC 7x5 exception model      */
 118    POWERPC_EXCP_7x5,
 119    /* PowerPC 74xx exception model     */
 120    POWERPC_EXCP_74xx,
 121    /* BookE exception model            */
 122    POWERPC_EXCP_BOOKE,
 123    /* PowerPC 970 exception model      */
 124    POWERPC_EXCP_970,
 125    /* POWER7 exception model           */
 126    POWERPC_EXCP_POWER7,
 127    /* POWER8 exception model           */
 128    POWERPC_EXCP_POWER8,
 129};
 130
 131/*****************************************************************************/
 132/* PM instructions */
 133typedef enum {
 134    PPC_PM_DOZE,
 135    PPC_PM_NAP,
 136    PPC_PM_SLEEP,
 137    PPC_PM_RVWINKLE,
 138} powerpc_pm_insn_t;
 139
 140/*****************************************************************************/
 141/* Input pins model                                                          */
 142typedef enum powerpc_input_t powerpc_input_t;
 143enum powerpc_input_t {
 144    PPC_FLAGS_INPUT_UNKNOWN = 0,
 145    /* PowerPC 6xx bus                  */
 146    PPC_FLAGS_INPUT_6xx,
 147    /* BookE bus                        */
 148    PPC_FLAGS_INPUT_BookE,
 149    /* PowerPC 405 bus                  */
 150    PPC_FLAGS_INPUT_405,
 151    /* PowerPC 970 bus                  */
 152    PPC_FLAGS_INPUT_970,
 153    /* PowerPC POWER7 bus               */
 154    PPC_FLAGS_INPUT_POWER7,
 155    /* PowerPC 401 bus                  */
 156    PPC_FLAGS_INPUT_401,
 157    /* Freescale RCPU bus               */
 158    PPC_FLAGS_INPUT_RCPU,
 159};
 160
 161struct ppc_segment_page_sizes;
 162
 163/**
 164 * PowerPCCPUClass:
 165 * @parent_realize: The parent class' realize handler.
 166 * @parent_reset: The parent class' reset handler.
 167 *
 168 * A PowerPC CPU model.
 169 */
 170typedef struct PowerPCCPUClass {
 171    /*< private >*/
 172    CPUClass parent_class;
 173    /*< public >*/
 174
 175    DeviceRealize parent_realize;
 176    void (*parent_reset)(CPUState *cpu);
 177
 178    uint32_t pvr;
 179    bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
 180    uint64_t pcr_mask;          /* Available bits in PCR register */
 181    uint64_t pcr_supported;     /* Bits for supported PowerISA versions */
 182    uint32_t svr;
 183    uint64_t insns_flags;
 184    uint64_t insns_flags2;
 185    uint64_t msr_mask;
 186    powerpc_mmu_t   mmu_model;
 187    powerpc_excp_t  excp_model;
 188    powerpc_input_t bus_model;
 189    uint32_t flags;
 190    int bfd_mach;
 191    uint32_t l1_dcache_size, l1_icache_size;
 192    const struct ppc_segment_page_sizes *sps;
 193    void (*init_proc)(CPUPPCState *env);
 194    int  (*check_pow)(CPUPPCState *env);
 195    int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx);
 196    bool (*interrupts_big_endian)(PowerPCCPU *cpu);
 197} PowerPCCPUClass;
 198
 199#ifndef CONFIG_USER_ONLY
 200typedef struct PPCTimebase {
 201    uint64_t guest_timebase;
 202    int64_t time_of_the_day_ns;
 203} PPCTimebase;
 204
 205extern const struct VMStateDescription vmstate_ppc_timebase;
 206
 207#define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) {            \
 208    .name       = (stringify(_field)),                                \
 209    .version_id = (_version),                                         \
 210    .size       = sizeof(PPCTimebase),                                \
 211    .vmsd       = &vmstate_ppc_timebase,                              \
 212    .flags      = VMS_STRUCT,                                         \
 213    .offset     = vmstate_offset_value(_state, _field, PPCTimebase),  \
 214}
 215#endif
 216
 217#endif
 218