1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef S390X_CPU_H
24#define S390X_CPU_H
25
26#include "qemu-common.h"
27#include "cpu-qom.h"
28
29#define TARGET_LONG_BITS 64
30
31#define ELF_MACHINE_UNAME "S390X"
32
33#define CPUArchState struct CPUS390XState
34
35#include "exec/cpu-defs.h"
36#define TARGET_PAGE_BITS 12
37
38#define TARGET_PHYS_ADDR_SPACE_BITS 64
39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
41#include "exec/cpu-all.h"
42
43#include "fpu/softfloat.h"
44
45#define NB_MMU_MODES 3
46#define TARGET_INSN_START_EXTRA_WORDS 1
47
48#define MMU_MODE0_SUFFIX _primary
49#define MMU_MODE1_SUFFIX _secondary
50#define MMU_MODE2_SUFFIX _home
51
52#define MMU_USER_IDX 0
53
54#define MAX_EXT_QUEUE 16
55#define MAX_IO_QUEUE 16
56#define MAX_MCHK_QUEUE 16
57
58#define PSW_MCHK_MASK 0x0004000000000000
59#define PSW_IO_MASK 0x0200000000000000
60
61typedef struct PSW {
62 uint64_t mask;
63 uint64_t addr;
64} PSW;
65
66typedef struct ExtQueue {
67 uint32_t code;
68 uint32_t param;
69 uint32_t param64;
70} ExtQueue;
71
72typedef struct IOIntQueue {
73 uint16_t id;
74 uint16_t nr;
75 uint32_t parm;
76 uint32_t word;
77} IOIntQueue;
78
79typedef struct MchkQueue {
80 uint16_t type;
81} MchkQueue;
82
83typedef struct CPUS390XState {
84 uint64_t regs[16];
85
86
87
88
89 CPU_DoubleU vregs[32][2];
90 uint32_t aregs[16];
91
92 uint32_t fpc;
93 uint32_t cc_op;
94
95 float_status fpu_status;
96
97
98 uint64_t retxl;
99
100 PSW psw;
101
102 uint64_t cc_src;
103 uint64_t cc_dst;
104 uint64_t cc_vr;
105
106 uint64_t __excp_addr;
107 uint64_t psa;
108
109 uint32_t int_pgm_code;
110 uint32_t int_pgm_ilen;
111
112 uint32_t int_svc_code;
113 uint32_t int_svc_ilen;
114
115 uint64_t per_address;
116 uint16_t per_perc_atmid;
117
118 uint64_t cregs[16];
119
120 ExtQueue ext_queue[MAX_EXT_QUEUE];
121 IOIntQueue io_queue[MAX_IO_QUEUE][8];
122 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
123
124 int pending_int;
125 int ext_index;
126 int io_index[8];
127 int mchk_index;
128
129 uint64_t ckc;
130 uint64_t cputm;
131 uint32_t todpr;
132
133 uint64_t pfault_token;
134 uint64_t pfault_compare;
135 uint64_t pfault_select;
136
137 uint64_t gbea;
138 uint64_t pp;
139
140 uint8_t riccb[64];
141
142 CPU_COMMON
143
144
145
146 uint32_t cpu_num;
147 uint32_t machine_type;
148
149 uint64_t tod_offset;
150 uint64_t tod_basetime;
151 QEMUTimer *tod_timer;
152
153 QEMUTimer *cpu_timer;
154
155
156
157
158
159
160
161#define CPU_STATE_UNINITIALIZED 0x00
162#define CPU_STATE_STOPPED 0x01
163#define CPU_STATE_CHECK_STOP 0x02
164#define CPU_STATE_OPERATING 0x03
165#define CPU_STATE_LOAD 0x04
166 uint8_t cpu_state;
167
168
169 uint8_t sigp_order;
170
171} CPUS390XState;
172
173static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
174{
175 return &cs->vregs[nr][0];
176}
177
178
179
180
181
182
183
184struct S390CPU {
185
186 CPUState parent_obj;
187
188
189 CPUS390XState env;
190 int64_t id;
191
192 void *irqstate;
193 uint32_t irqstate_saved_size;
194};
195
196static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
197{
198 return container_of(env, S390CPU, env);
199}
200
201#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
202
203#define ENV_OFFSET offsetof(S390CPU, env)
204
205#ifndef CONFIG_USER_ONLY
206extern const struct VMStateDescription vmstate_s390_cpu;
207#endif
208
209void s390_cpu_do_interrupt(CPUState *cpu);
210bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
211void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
212 int flags);
213int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
214 int cpuid, void *opaque);
215
216hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
217hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
218int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
219int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
220void s390_cpu_gdb_init(CPUState *cs);
221void s390x_cpu_debug_excp_handler(CPUState *cs);
222
223#include "sysemu/kvm.h"
224
225
226#define HIGH_ORDER_BIT 0x80000000
227
228
229
230#define PGM_OPERATION 0x0001
231#define PGM_PRIVILEGED 0x0002
232#define PGM_EXECUTE 0x0003
233#define PGM_PROTECTION 0x0004
234#define PGM_ADDRESSING 0x0005
235#define PGM_SPECIFICATION 0x0006
236#define PGM_DATA 0x0007
237#define PGM_FIXPT_OVERFLOW 0x0008
238#define PGM_FIXPT_DIVIDE 0x0009
239#define PGM_DEC_OVERFLOW 0x000a
240#define PGM_DEC_DIVIDE 0x000b
241#define PGM_HFP_EXP_OVERFLOW 0x000c
242#define PGM_HFP_EXP_UNDERFLOW 0x000d
243#define PGM_HFP_SIGNIFICANCE 0x000e
244#define PGM_HFP_DIVIDE 0x000f
245#define PGM_SEGMENT_TRANS 0x0010
246#define PGM_PAGE_TRANS 0x0011
247#define PGM_TRANS_SPEC 0x0012
248#define PGM_SPECIAL_OP 0x0013
249#define PGM_OPERAND 0x0015
250#define PGM_TRACE_TABLE 0x0016
251#define PGM_SPACE_SWITCH 0x001c
252#define PGM_HFP_SQRT 0x001d
253#define PGM_PC_TRANS_SPEC 0x001f
254#define PGM_AFX_TRANS 0x0020
255#define PGM_ASX_TRANS 0x0021
256#define PGM_LX_TRANS 0x0022
257#define PGM_EX_TRANS 0x0023
258#define PGM_PRIM_AUTH 0x0024
259#define PGM_SEC_AUTH 0x0025
260#define PGM_ALET_SPEC 0x0028
261#define PGM_ALEN_SPEC 0x0029
262#define PGM_ALE_SEQ 0x002a
263#define PGM_ASTE_VALID 0x002b
264#define PGM_ASTE_SEQ 0x002c
265#define PGM_EXT_AUTH 0x002d
266#define PGM_STACK_FULL 0x0030
267#define PGM_STACK_EMPTY 0x0031
268#define PGM_STACK_SPEC 0x0032
269#define PGM_STACK_TYPE 0x0033
270#define PGM_STACK_OP 0x0034
271#define PGM_ASCE_TYPE 0x0038
272#define PGM_REG_FIRST_TRANS 0x0039
273#define PGM_REG_SEC_TRANS 0x003a
274#define PGM_REG_THIRD_TRANS 0x003b
275#define PGM_MONITOR 0x0040
276#define PGM_PER 0x0080
277#define PGM_CRYPTO 0x0119
278
279
280#define EXT_INTERRUPT_KEY 0x0040
281#define EXT_CLOCK_COMP 0x1004
282#define EXT_CPU_TIMER 0x1005
283#define EXT_MALFUNCTION 0x1200
284#define EXT_EMERGENCY 0x1201
285#define EXT_EXTERNAL_CALL 0x1202
286#define EXT_ETR 0x1406
287#define EXT_SERVICE 0x2401
288#define EXT_VIRTIO 0x2603
289
290
291#undef PSW_MASK_PER
292#undef PSW_MASK_DAT
293#undef PSW_MASK_IO
294#undef PSW_MASK_EXT
295#undef PSW_MASK_KEY
296#undef PSW_SHIFT_KEY
297#undef PSW_MASK_MCHECK
298#undef PSW_MASK_WAIT
299#undef PSW_MASK_PSTATE
300#undef PSW_MASK_ASC
301#undef PSW_MASK_CC
302#undef PSW_MASK_PM
303#undef PSW_MASK_64
304#undef PSW_MASK_32
305#undef PSW_MASK_ESA_ADDR
306
307#define PSW_MASK_PER 0x4000000000000000ULL
308#define PSW_MASK_DAT 0x0400000000000000ULL
309#define PSW_MASK_IO 0x0200000000000000ULL
310#define PSW_MASK_EXT 0x0100000000000000ULL
311#define PSW_MASK_KEY 0x00F0000000000000ULL
312#define PSW_SHIFT_KEY 56
313#define PSW_MASK_MCHECK 0x0004000000000000ULL
314#define PSW_MASK_WAIT 0x0002000000000000ULL
315#define PSW_MASK_PSTATE 0x0001000000000000ULL
316#define PSW_MASK_ASC 0x0000C00000000000ULL
317#define PSW_MASK_CC 0x0000300000000000ULL
318#define PSW_MASK_PM 0x00000F0000000000ULL
319#define PSW_MASK_64 0x0000000100000000ULL
320#define PSW_MASK_32 0x0000000080000000ULL
321#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
322
323#undef PSW_ASC_PRIMARY
324#undef PSW_ASC_ACCREG
325#undef PSW_ASC_SECONDARY
326#undef PSW_ASC_HOME
327
328#define PSW_ASC_PRIMARY 0x0000000000000000ULL
329#define PSW_ASC_ACCREG 0x0000400000000000ULL
330#define PSW_ASC_SECONDARY 0x0000800000000000ULL
331#define PSW_ASC_HOME 0x0000C00000000000ULL
332
333
334
335#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
336#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
337#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
338#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
339#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
340#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
341#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
342#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
343#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
344#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
345#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
346#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
347#define FLAG_MASK_32 0x00001000
348
349
350#define CR0_LOWPROT 0x0000000010000000ULL
351#define CR0_EDAT 0x0000000000800000ULL
352
353
354#define MMU_PRIMARY_IDX 0
355#define MMU_SECONDARY_IDX 1
356#define MMU_HOME_IDX 2
357
358static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
359{
360 switch (env->psw.mask & PSW_MASK_ASC) {
361 case PSW_ASC_PRIMARY:
362 return MMU_PRIMARY_IDX;
363 case PSW_ASC_SECONDARY:
364 return MMU_SECONDARY_IDX;
365 case PSW_ASC_HOME:
366 return MMU_HOME_IDX;
367 case PSW_ASC_ACCREG:
368
369 default:
370 abort();
371 }
372}
373
374static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
375{
376 switch (mmu_idx) {
377 case MMU_PRIMARY_IDX:
378 return PSW_ASC_PRIMARY;
379 case MMU_SECONDARY_IDX:
380 return PSW_ASC_SECONDARY;
381 case MMU_HOME_IDX:
382 return PSW_ASC_HOME;
383 default:
384 abort();
385 }
386}
387
388static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
389 target_ulong *cs_base, uint32_t *flags)
390{
391 *pc = env->psw.addr;
392 *cs_base = 0;
393 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
394 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
395}
396
397
398
399
400
401
402static inline int get_ilen(uint8_t opc)
403{
404 switch (opc >> 6) {
405 case 0:
406 return 2;
407 case 1:
408 case 2:
409 return 4;
410 default:
411 return 6;
412 }
413}
414
415
416#define PER_CR9_EVENT_BRANCH 0x80000000
417#define PER_CR9_EVENT_IFETCH 0x40000000
418#define PER_CR9_EVENT_STORE 0x20000000
419#define PER_CR9_EVENT_STORE_REAL 0x08000000
420#define PER_CR9_EVENT_NULLIFICATION 0x01000000
421#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
422#define PER_CR9_CONTROL_ALTERATION 0x00200000
423
424
425#define PER_CODE_EVENT_BRANCH 0x8000
426#define PER_CODE_EVENT_IFETCH 0x4000
427#define PER_CODE_EVENT_STORE 0x2000
428#define PER_CODE_EVENT_STORE_REAL 0x0800
429#define PER_CODE_EVENT_NULLIFICATION 0x0100
430
431
432
433static inline uint8_t get_per_atmid(CPUS390XState *env)
434{
435 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
436 ( (1 << 6) ) |
437 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
438 ((env->psw.mask & PSW_MASK_DAT)? (1 << 4) : 0) |
439 ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
440 ((env->psw.mask & PSW_ASC_ACCREG)? (1 << 2) : 0);
441}
442
443
444
445static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
446{
447 if (env->cregs[10] <= env->cregs[11]) {
448 return env->cregs[10] <= addr && addr <= env->cregs[11];
449 } else {
450 return env->cregs[10] <= addr || addr <= env->cregs[11];
451 }
452}
453
454#ifndef CONFIG_USER_ONLY
455
456
457
458#define ILEN_LATER 0x20
459#define ILEN_LATER_INC 0x21
460void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
461#endif
462
463S390CPU *cpu_s390x_init(const char *cpu_model);
464S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
465S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp);
466void s390x_translate_init(void);
467
468
469
470
471int cpu_s390x_signal_handler(int host_signum, void *pinfo,
472 void *puc);
473int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
474 int mmu_idx);
475
476
477#ifndef CONFIG_USER_ONLY
478void do_restart_interrupt(CPUS390XState *env);
479
480static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
481 uint8_t *ar)
482{
483 hwaddr addr = 0;
484 uint8_t reg;
485
486 reg = ipb >> 28;
487 if (reg > 0) {
488 addr = env->regs[reg];
489 }
490 addr += (ipb >> 16) & 0xfff;
491 if (ar) {
492 *ar = reg;
493 }
494
495 return addr;
496}
497
498
499#define decode_basedisp_rs decode_basedisp_s
500
501
502static inline void s390_do_cpu_reset(void *arg)
503{
504 CPUState *cs = arg;
505 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
506
507 scc->cpu_reset(cs);
508}
509static inline void s390_do_cpu_full_reset(void *arg)
510{
511 CPUState *cs = arg;
512
513 cpu_reset(cs);
514}
515
516void s390x_tod_timer(void *opaque);
517void s390x_cpu_timer(void *opaque);
518
519int s390_virtio_hypercall(CPUS390XState *env);
520
521#ifdef CONFIG_KVM
522void kvm_s390_service_interrupt(uint32_t parm);
523void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
524void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
525int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
526void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
527int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
528 int len, bool is_write);
529int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
530int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
531#else
532static inline void kvm_s390_service_interrupt(uint32_t parm)
533{
534}
535static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
536{
537 return -ENOSYS;
538}
539static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
540{
541 return -ENOSYS;
542}
543static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
544 void *hostbuf, int len, bool is_write)
545{
546 return -ENOSYS;
547}
548static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
549 uint64_t te_code)
550{
551}
552#endif
553
554static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
555{
556 if (kvm_enabled()) {
557 return kvm_s390_get_clock(tod_high, tod_low);
558 }
559
560 *tod_high = 0;
561 *tod_low = 0;
562 return 0;
563}
564
565static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
566{
567 if (kvm_enabled()) {
568 return kvm_s390_set_clock(tod_high, tod_low);
569 }
570
571 return 0;
572}
573
574S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
575unsigned int s390_cpu_halt(S390CPU *cpu);
576void s390_cpu_unhalt(S390CPU *cpu);
577unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
578static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
579{
580 return cpu->env.cpu_state;
581}
582
583void gtod_save(QEMUFile *f, void *opaque);
584int gtod_load(QEMUFile *f, void *opaque, int version_id);
585
586void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
587 uint64_t param64);
588
589
590void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1);
591void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1);
592void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1);
593void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
594void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
595void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb);
596void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
597int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
598void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb);
599int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb);
600void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
601 uint32_t ipb);
602void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1);
603void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1);
604void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1);
605
606
607void s390_sclp_extint(uint32_t parm);
608
609#else
610static inline unsigned int s390_cpu_halt(S390CPU *cpu)
611{
612 return 0;
613}
614
615static inline void s390_cpu_unhalt(S390CPU *cpu)
616{
617}
618
619static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
620{
621 return 0;
622}
623#endif
624void cpu_lock(void);
625void cpu_unlock(void);
626
627extern void subsystem_reset(void);
628
629#define cpu_init(model) CPU(cpu_s390x_init(model))
630#define cpu_signal_handler cpu_s390x_signal_handler
631
632void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
633#define cpu_list s390_cpu_list
634
635#define EXCP_EXT 1
636#define EXCP_SVC 2
637#define EXCP_PGM 3
638#define EXCP_IO 7
639#define EXCP_MCHK 8
640
641#define INTERRUPT_EXT (1 << 0)
642#define INTERRUPT_TOD (1 << 1)
643#define INTERRUPT_CPUTIMER (1 << 2)
644#define INTERRUPT_IO (1 << 3)
645#define INTERRUPT_MCHK (1 << 4)
646
647
648#define S390_PSWM_REGNUM 0
649#define S390_PSWA_REGNUM 1
650
651#define S390_R0_REGNUM 2
652#define S390_R1_REGNUM 3
653#define S390_R2_REGNUM 4
654#define S390_R3_REGNUM 5
655#define S390_R4_REGNUM 6
656#define S390_R5_REGNUM 7
657#define S390_R6_REGNUM 8
658#define S390_R7_REGNUM 9
659#define S390_R8_REGNUM 10
660#define S390_R9_REGNUM 11
661#define S390_R10_REGNUM 12
662#define S390_R11_REGNUM 13
663#define S390_R12_REGNUM 14
664#define S390_R13_REGNUM 15
665#define S390_R14_REGNUM 16
666#define S390_R15_REGNUM 17
667
668#define S390_NUM_CORE_REGS 18
669
670
671
672enum cc_op {
673 CC_OP_CONST0 = 0,
674 CC_OP_CONST1,
675 CC_OP_CONST2,
676 CC_OP_CONST3,
677
678 CC_OP_DYNAMIC,
679 CC_OP_STATIC,
680
681 CC_OP_NZ,
682 CC_OP_LTGT_32,
683 CC_OP_LTGT_64,
684 CC_OP_LTUGTU_32,
685 CC_OP_LTUGTU_64,
686 CC_OP_LTGT0_32,
687 CC_OP_LTGT0_64,
688
689 CC_OP_ADD_64,
690 CC_OP_ADDU_64,
691 CC_OP_ADDC_64,
692 CC_OP_SUB_64,
693 CC_OP_SUBU_64,
694 CC_OP_SUBB_64,
695 CC_OP_ABS_64,
696 CC_OP_NABS_64,
697
698 CC_OP_ADD_32,
699 CC_OP_ADDU_32,
700 CC_OP_ADDC_32,
701 CC_OP_SUB_32,
702 CC_OP_SUBU_32,
703 CC_OP_SUBB_32,
704 CC_OP_ABS_32,
705 CC_OP_NABS_32,
706
707 CC_OP_COMP_32,
708 CC_OP_COMP_64,
709
710 CC_OP_TM_32,
711 CC_OP_TM_64,
712
713 CC_OP_NZ_F32,
714 CC_OP_NZ_F64,
715 CC_OP_NZ_F128,
716
717 CC_OP_ICM,
718 CC_OP_SLA_32,
719 CC_OP_SLA_64,
720 CC_OP_FLOGR,
721 CC_OP_MAX
722};
723
724static const char *cc_names[] = {
725 [CC_OP_CONST0] = "CC_OP_CONST0",
726 [CC_OP_CONST1] = "CC_OP_CONST1",
727 [CC_OP_CONST2] = "CC_OP_CONST2",
728 [CC_OP_CONST3] = "CC_OP_CONST3",
729 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
730 [CC_OP_STATIC] = "CC_OP_STATIC",
731 [CC_OP_NZ] = "CC_OP_NZ",
732 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
733 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
734 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
735 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
736 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
737 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
738 [CC_OP_ADD_64] = "CC_OP_ADD_64",
739 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
740 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
741 [CC_OP_SUB_64] = "CC_OP_SUB_64",
742 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
743 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
744 [CC_OP_ABS_64] = "CC_OP_ABS_64",
745 [CC_OP_NABS_64] = "CC_OP_NABS_64",
746 [CC_OP_ADD_32] = "CC_OP_ADD_32",
747 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
748 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
749 [CC_OP_SUB_32] = "CC_OP_SUB_32",
750 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
751 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
752 [CC_OP_ABS_32] = "CC_OP_ABS_32",
753 [CC_OP_NABS_32] = "CC_OP_NABS_32",
754 [CC_OP_COMP_32] = "CC_OP_COMP_32",
755 [CC_OP_COMP_64] = "CC_OP_COMP_64",
756 [CC_OP_TM_32] = "CC_OP_TM_32",
757 [CC_OP_TM_64] = "CC_OP_TM_64",
758 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
759 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
760 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
761 [CC_OP_ICM] = "CC_OP_ICM",
762 [CC_OP_SLA_32] = "CC_OP_SLA_32",
763 [CC_OP_SLA_64] = "CC_OP_SLA_64",
764 [CC_OP_FLOGR] = "CC_OP_FLOGR",
765};
766
767static inline const char *cc_name(int cc_op)
768{
769 return cc_names[cc_op];
770}
771
772static inline void setcc(S390CPU *cpu, uint64_t cc)
773{
774 CPUS390XState *env = &cpu->env;
775
776 env->psw.mask &= ~(3ull << 44);
777 env->psw.mask |= (cc & 3) << 44;
778 env->cc_op = cc;
779}
780
781typedef struct LowCore
782{
783
784 uint32_t ccw1[2];
785 uint32_t ccw2[4];
786 uint8_t pad1[0x80-0x18];
787 uint32_t ext_params;
788 uint16_t cpu_addr;
789 uint16_t ext_int_code;
790 uint16_t svc_ilen;
791 uint16_t svc_code;
792 uint16_t pgm_ilen;
793 uint16_t pgm_code;
794 uint32_t data_exc_code;
795 uint16_t mon_class_num;
796 uint16_t per_perc_atmid;
797 uint64_t per_address;
798 uint8_t exc_access_id;
799 uint8_t per_access_id;
800 uint8_t op_access_id;
801 uint8_t ar_access_id;
802 uint8_t pad2[0xA8-0xA4];
803 uint64_t trans_exc_code;
804 uint64_t monitor_code;
805 uint16_t subchannel_id;
806 uint16_t subchannel_nr;
807 uint32_t io_int_parm;
808 uint32_t io_int_word;
809 uint8_t pad3[0xc8-0xc4];
810 uint32_t stfl_fac_list;
811 uint8_t pad4[0xe8-0xcc];
812 uint32_t mcck_interruption_code[2];
813 uint8_t pad5[0xf4-0xf0];
814 uint32_t external_damage_code;
815 uint64_t failing_storage_address;
816 uint8_t pad6[0x110-0x100];
817 uint64_t per_breaking_event_addr;
818 uint8_t pad7[0x120-0x118];
819 PSW restart_old_psw;
820 PSW external_old_psw;
821 PSW svc_old_psw;
822 PSW program_old_psw;
823 PSW mcck_old_psw;
824 PSW io_old_psw;
825 uint8_t pad8[0x1a0-0x180];
826 PSW restart_new_psw;
827 PSW external_new_psw;
828 PSW svc_new_psw;
829 PSW program_new_psw;
830 PSW mcck_new_psw;
831 PSW io_new_psw;
832 PSW return_psw;
833 uint8_t irb[64];
834 uint64_t sync_enter_timer;
835 uint64_t async_enter_timer;
836 uint64_t exit_timer;
837 uint64_t last_update_timer;
838 uint64_t user_timer;
839 uint64_t system_timer;
840 uint64_t last_update_clock;
841 uint64_t steal_clock;
842 PSW return_mcck_psw;
843 uint8_t pad9[0xc00-0x2a0];
844
845 uint64_t save_area[16];
846 uint8_t pad10[0xd40-0xc80];
847 uint64_t kernel_stack;
848 uint64_t thread_info;
849 uint64_t async_stack;
850 uint64_t kernel_asce;
851 uint64_t user_asce;
852 uint64_t panic_stack;
853 uint64_t user_exec_asce;
854 uint8_t pad11[0xdc0-0xd78];
855
856
857 uint64_t clock_comparator;
858 uint64_t ext_call_fast;
859 uint64_t percpu_offset;
860 uint64_t current_task;
861 uint32_t softirq_pending;
862 uint32_t pad_0x0de4;
863 uint64_t int_clock;
864 uint8_t pad12[0xe00-0xdf0];
865
866
867
868 uint32_t panic_magic;
869
870 uint8_t pad13[0x11b8-0xe04];
871
872
873 uint64_t ext_params2;
874
875 uint8_t pad14[0x1200-0x11C0];
876
877
878
879 uint64_t floating_pt_save_area[16];
880 uint64_t gpregs_save_area[16];
881 uint32_t st_status_fixed_logout[4];
882 uint8_t pad15[0x1318-0x1310];
883 uint32_t prefixreg_save_area;
884 uint32_t fpt_creg_save_area;
885 uint8_t pad16[0x1324-0x1320];
886 uint32_t tod_progreg_save_area;
887 uint32_t cpu_timer_save_area[2];
888 uint32_t clock_comp_save_area[2];
889 uint8_t pad17[0x1340-0x1338];
890 uint32_t access_regs_save_area[16];
891 uint64_t cregs_save_area[16];
892
893
894
895 uint8_t pad18[0x2000-0x1400];
896} QEMU_PACKED LowCore;
897
898
899#define STSI_LEVEL_MASK 0x00000000f0000000ULL
900#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
901#define STSI_LEVEL_1 0x0000000010000000ULL
902#define STSI_LEVEL_2 0x0000000020000000ULL
903#define STSI_LEVEL_3 0x0000000030000000ULL
904#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
905#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
906#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
907#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
908
909
910struct sysib_111 {
911 uint32_t res1[8];
912 uint8_t manuf[16];
913 uint8_t type[4];
914 uint8_t res2[12];
915 uint8_t model[16];
916 uint8_t sequence[16];
917 uint8_t plant[4];
918 uint8_t res3[156];
919};
920
921
922struct sysib_121 {
923 uint32_t res1[80];
924 uint8_t sequence[16];
925 uint8_t plant[4];
926 uint8_t res2[2];
927 uint16_t cpu_addr;
928 uint8_t res3[152];
929};
930
931
932struct sysib_122 {
933 uint8_t res1[32];
934 uint32_t capability;
935 uint16_t total_cpus;
936 uint16_t active_cpus;
937 uint16_t standby_cpus;
938 uint16_t reserved_cpus;
939 uint16_t adjustments[2026];
940};
941
942
943struct sysib_221 {
944 uint32_t res1[80];
945 uint8_t sequence[16];
946 uint8_t plant[4];
947 uint16_t cpu_id;
948 uint16_t cpu_addr;
949 uint8_t res3[152];
950};
951
952
953struct sysib_222 {
954 uint32_t res1[32];
955 uint16_t lpar_num;
956 uint8_t res2;
957 uint8_t lcpuc;
958 uint16_t total_cpus;
959 uint16_t conf_cpus;
960 uint16_t standby_cpus;
961 uint16_t reserved_cpus;
962 uint8_t name[8];
963 uint32_t caf;
964 uint8_t res3[16];
965 uint16_t dedicated_cpus;
966 uint16_t shared_cpus;
967 uint8_t res4[180];
968};
969
970
971struct sysib_322 {
972 uint8_t res1[31];
973 uint8_t count;
974 struct {
975 uint8_t res2[4];
976 uint16_t total_cpus;
977 uint16_t conf_cpus;
978 uint16_t standby_cpus;
979 uint16_t reserved_cpus;
980 uint8_t name[8];
981 uint32_t caf;
982 uint8_t cpi[16];
983 uint8_t res5[3];
984 uint8_t ext_name_encoding;
985 uint32_t res3;
986 uint8_t uuid[16];
987 } vm[8];
988 uint8_t res4[1504];
989 uint8_t ext_names[8][256];
990};
991
992
993#define _ASCE_ORIGIN ~0xfffULL
994#define _ASCE_SUBSPACE 0x200
995#define _ASCE_PRIVATE_SPACE 0x100
996#define _ASCE_ALT_EVENT 0x80
997#define _ASCE_SPACE_SWITCH 0x40
998#define _ASCE_REAL_SPACE 0x20
999#define _ASCE_TYPE_MASK 0x0c
1000#define _ASCE_TYPE_REGION1 0x0c
1001#define _ASCE_TYPE_REGION2 0x08
1002#define _ASCE_TYPE_REGION3 0x04
1003#define _ASCE_TYPE_SEGMENT 0x00
1004#define _ASCE_TABLE_LENGTH 0x03
1005
1006#define _REGION_ENTRY_ORIGIN ~0xfffULL
1007#define _REGION_ENTRY_RO 0x200
1008#define _REGION_ENTRY_TF 0xc0
1009#define _REGION_ENTRY_INV 0x20
1010#define _REGION_ENTRY_TYPE_MASK 0x0c
1011#define _REGION_ENTRY_TYPE_R1 0x0c
1012#define _REGION_ENTRY_TYPE_R2 0x08
1013#define _REGION_ENTRY_TYPE_R3 0x04
1014#define _REGION_ENTRY_LENGTH 0x03
1015
1016#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL
1017#define _SEGMENT_ENTRY_FC 0x400
1018#define _SEGMENT_ENTRY_RO 0x200
1019#define _SEGMENT_ENTRY_INV 0x20
1020
1021#define _PAGE_RO 0x200
1022#define _PAGE_INVALID 0x400
1023#define _PAGE_RES0 0x800
1024
1025#define SK_C (0x1 << 1)
1026#define SK_R (0x1 << 2)
1027#define SK_F (0x1 << 3)
1028#define SK_ACC_MASK (0xf << 4)
1029
1030
1031#define SIGP_SENSE 0x01
1032#define SIGP_EXTERNAL_CALL 0x02
1033#define SIGP_EMERGENCY 0x03
1034#define SIGP_START 0x04
1035#define SIGP_STOP 0x05
1036#define SIGP_RESTART 0x06
1037#define SIGP_STOP_STORE_STATUS 0x09
1038#define SIGP_INITIAL_CPU_RESET 0x0b
1039#define SIGP_CPU_RESET 0x0c
1040#define SIGP_SET_PREFIX 0x0d
1041#define SIGP_STORE_STATUS_ADDR 0x0e
1042#define SIGP_SET_ARCH 0x12
1043#define SIGP_STORE_ADTL_STATUS 0x17
1044
1045
1046#define SIGP_CC_ORDER_CODE_ACCEPTED 0
1047#define SIGP_CC_STATUS_STORED 1
1048#define SIGP_CC_BUSY 2
1049#define SIGP_CC_NOT_OPERATIONAL 3
1050
1051
1052#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
1053#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
1054#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1055#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
1056#define SIGP_STAT_STOPPED 0x00000040UL
1057#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
1058#define SIGP_STAT_CHECK_STOP 0x00000010UL
1059#define SIGP_STAT_INOPERATIVE 0x00000004UL
1060#define SIGP_STAT_INVALID_ORDER 0x00000002UL
1061#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
1062
1063
1064#define SIGP_MODE_ESA_S390 0
1065#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1066#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1067
1068void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1069int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1070 target_ulong *raddr, int *flags, bool exc);
1071int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1072uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1073 uint64_t vr);
1074void s390_cpu_recompute_watchpoints(CPUState *cs);
1075
1076int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1077 int len, bool is_write);
1078
1079#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
1080 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1081#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
1082 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1083#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
1084 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1085
1086
1087#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1088
1089
1090static inline uint64_t time2tod(uint64_t ns) {
1091 return (ns << 9) / 125;
1092}
1093
1094
1095static inline uint64_t tod2time(uint64_t t) {
1096 return (t * 125) >> 9;
1097}
1098
1099
1100#define MEM_SECTION_SIZE 0x10000000UL
1101#define MAX_AVAIL_SLOTS 32
1102
1103
1104uint32_t set_cc_nz_f32(float32 v);
1105uint32_t set_cc_nz_f64(float64 v);
1106uint32_t set_cc_nz_f128(float128 v);
1107
1108
1109#ifndef CONFIG_USER_ONLY
1110int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1111void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1112#endif
1113void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1114void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1115 uintptr_t retaddr);
1116
1117#ifdef CONFIG_KVM
1118void kvm_s390_io_interrupt(uint16_t subchannel_id,
1119 uint16_t subchannel_nr, uint32_t io_int_parm,
1120 uint32_t io_int_word);
1121void kvm_s390_crw_mchk(void);
1122void kvm_s390_enable_css_support(S390CPU *cpu);
1123int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1124 int vq, bool assign);
1125int kvm_s390_cpu_restart(S390CPU *cpu);
1126int kvm_s390_get_memslot_count(KVMState *s);
1127void kvm_s390_cmma_reset(void);
1128int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1129void kvm_s390_reset_vcpu(S390CPU *cpu);
1130int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1131void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1132int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1133int kvm_s390_get_ri(void);
1134void kvm_s390_crypto_reset(void);
1135#else
1136static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1137 uint16_t subchannel_nr,
1138 uint32_t io_int_parm,
1139 uint32_t io_int_word)
1140{
1141}
1142static inline void kvm_s390_crw_mchk(void)
1143{
1144}
1145static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1146{
1147}
1148static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1149 uint32_t sch, int vq,
1150 bool assign)
1151{
1152 return -ENOSYS;
1153}
1154static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1155{
1156 return -ENOSYS;
1157}
1158static inline void kvm_s390_cmma_reset(void)
1159{
1160}
1161static inline int kvm_s390_get_memslot_count(KVMState *s)
1162{
1163 return MAX_AVAIL_SLOTS;
1164}
1165static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1166{
1167 return -ENOSYS;
1168}
1169static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1170{
1171}
1172static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1173 uint64_t *hw_limit)
1174{
1175 return 0;
1176}
1177static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1178{
1179}
1180static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1181{
1182 return 0;
1183}
1184static inline int kvm_s390_get_ri(void)
1185{
1186 return 0;
1187}
1188static inline void kvm_s390_crypto_reset(void)
1189{
1190}
1191#endif
1192
1193static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1194{
1195 if (kvm_enabled()) {
1196 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1197 }
1198 return 0;
1199}
1200
1201static inline void s390_cmma_reset(void)
1202{
1203 if (kvm_enabled()) {
1204 kvm_s390_cmma_reset();
1205 }
1206}
1207
1208static inline int s390_cpu_restart(S390CPU *cpu)
1209{
1210 if (kvm_enabled()) {
1211 return kvm_s390_cpu_restart(cpu);
1212 }
1213 return -ENOSYS;
1214}
1215
1216static inline int s390_get_memslot_count(KVMState *s)
1217{
1218 if (kvm_enabled()) {
1219 return kvm_s390_get_memslot_count(s);
1220 } else {
1221 return MAX_AVAIL_SLOTS;
1222 }
1223}
1224
1225void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1226 uint32_t io_int_parm, uint32_t io_int_word);
1227void s390_crw_mchk(void);
1228
1229static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1230 uint32_t sch_id, int vq,
1231 bool assign)
1232{
1233 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1234}
1235
1236static inline void s390_crypto_reset(void)
1237{
1238 if (kvm_enabled()) {
1239 kvm_s390_crypto_reset();
1240 }
1241}
1242
1243
1244
1245
1246#define MCIC_SC_SD 0x8000000000000000ULL
1247#define MCIC_SC_PD 0x4000000000000000ULL
1248#define MCIC_SC_SR 0x2000000000000000ULL
1249#define MCIC_SC_CD 0x0800000000000000ULL
1250#define MCIC_SC_ED 0x0400000000000000ULL
1251#define MCIC_SC_DG 0x0100000000000000ULL
1252#define MCIC_SC_W 0x0080000000000000ULL
1253#define MCIC_SC_CP 0x0040000000000000ULL
1254#define MCIC_SC_SP 0x0020000000000000ULL
1255#define MCIC_SC_CK 0x0010000000000000ULL
1256
1257
1258#define MCIC_SCM_B 0x0002000000000000ULL
1259#define MCIC_SCM_DA 0x0000000020000000ULL
1260#define MCIC_SCM_AP 0x0000000000080000ULL
1261
1262
1263#define MCIC_SE_SE 0x0000800000000000ULL
1264#define MCIC_SE_SC 0x0000400000000000ULL
1265#define MCIC_SE_KE 0x0000200000000000ULL
1266#define MCIC_SE_DS 0x0000100000000000ULL
1267#define MCIC_SE_IE 0x0000000080000000ULL
1268
1269
1270#define MCIC_VB_WP 0x0000080000000000ULL
1271#define MCIC_VB_MS 0x0000040000000000ULL
1272#define MCIC_VB_PM 0x0000020000000000ULL
1273#define MCIC_VB_IA 0x0000010000000000ULL
1274#define MCIC_VB_FA 0x0000008000000000ULL
1275#define MCIC_VB_VR 0x0000004000000000ULL
1276#define MCIC_VB_EC 0x0000002000000000ULL
1277#define MCIC_VB_FP 0x0000001000000000ULL
1278#define MCIC_VB_GR 0x0000000800000000ULL
1279#define MCIC_VB_CR 0x0000000400000000ULL
1280#define MCIC_VB_ST 0x0000000100000000ULL
1281#define MCIC_VB_AR 0x0000000040000000ULL
1282#define MCIC_VB_PR 0x0000000000200000ULL
1283#define MCIC_VB_FC 0x0000000000100000ULL
1284#define MCIC_VB_CT 0x0000000000020000ULL
1285#define MCIC_VB_CC 0x0000000000010000ULL
1286
1287#endif
1288
