LXR qemu/target-sh4/cpu.h

   1/*
   2 *  SH4 emulation
   3 *
   4 *  Copyright (c) 2005 Samuel Tardieu
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef SH4_CPU_H
  21#define SH4_CPU_H
  22
  23#include "qemu-common.h"
  24#include "cpu-qom.h"
  25
  26#define TARGET_LONG_BITS 32
  27
  28/* CPU Subtypes */
  29#define SH_CPU_SH7750  (1 << 0)
  30#define SH_CPU_SH7750S (1 << 1)
  31#define SH_CPU_SH7750R (1 << 2)
  32#define SH_CPU_SH7751  (1 << 3)
  33#define SH_CPU_SH7751R (1 << 4)
  34#define SH_CPU_SH7785  (1 << 5)
  35#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
  36#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
  37
  38#define CPUArchState struct CPUSH4State
  39
  40#include "exec/cpu-defs.h"
  41
  42#include "fpu/softfloat.h"
  43
  44#define TARGET_PAGE_BITS 12     /* 4k XXXXX */
  45
  46#define TARGET_PHYS_ADDR_SPACE_BITS 32
  47#define TARGET_VIRT_ADDR_SPACE_BITS 32
  48
  49#define SR_MD 30
  50#define SR_RB 29
  51#define SR_BL 28
  52#define SR_FD 15
  53#define SR_M  9
  54#define SR_Q  8
  55#define SR_I3 7
  56#define SR_I2 6
  57#define SR_I1 5
  58#define SR_I0 4
  59#define SR_S  1
  60#define SR_T  0
  61
  62#define FPSCR_MASK             (0x003fffff)
  63#define FPSCR_FR               (1 << 21)
  64#define FPSCR_SZ               (1 << 20)
  65#define FPSCR_PR               (1 << 19)
  66#define FPSCR_DN               (1 << 18)
  67#define FPSCR_CAUSE_MASK       (0x3f << 12)
  68#define FPSCR_CAUSE_SHIFT      (12)
  69#define FPSCR_CAUSE_E          (1 << 17)
  70#define FPSCR_CAUSE_V          (1 << 16)
  71#define FPSCR_CAUSE_Z          (1 << 15)
  72#define FPSCR_CAUSE_O          (1 << 14)
  73#define FPSCR_CAUSE_U          (1 << 13)
  74#define FPSCR_CAUSE_I          (1 << 12)
  75#define FPSCR_ENABLE_MASK      (0x1f << 7)
  76#define FPSCR_ENABLE_SHIFT     (7)
  77#define FPSCR_ENABLE_V         (1 << 11)
  78#define FPSCR_ENABLE_Z         (1 << 10)
  79#define FPSCR_ENABLE_O         (1 << 9)
  80#define FPSCR_ENABLE_U         (1 << 8)
  81#define FPSCR_ENABLE_I         (1 << 7)
  82#define FPSCR_FLAG_MASK        (0x1f << 2)
  83#define FPSCR_FLAG_SHIFT       (2)
  84#define FPSCR_FLAG_V           (1 << 6)
  85#define FPSCR_FLAG_Z           (1 << 5)
  86#define FPSCR_FLAG_O           (1 << 4)
  87#define FPSCR_FLAG_U           (1 << 3)
  88#define FPSCR_FLAG_I           (1 << 2)
  89#define FPSCR_RM_MASK          (0x03 << 0)
  90#define FPSCR_RM_NEAREST       (0 << 0)
  91#define FPSCR_RM_ZERO          (1 << 0)
  92
  93#define DELAY_SLOT             (1 << 0)
  94#define DELAY_SLOT_CONDITIONAL (1 << 1)
  95#define DELAY_SLOT_TRUE        (1 << 2)
  96#define DELAY_SLOT_CLEARME     (1 << 3)
  97/* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
  98 * after the delay slot should be taken or not. It is calculated from SR_T.
  99 *
 100 * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
 101 * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
 102 */
 103
 104typedef struct tlb_t {
 105    uint32_t vpn;               /* virtual page number */
 106    uint32_t ppn;               /* physical page number */
 107    uint32_t size;              /* mapped page size in bytes */
 108    uint8_t asid;               /* address space identifier */
 109    uint8_t v:1;                /* validity */
 110    uint8_t sz:2;               /* page size */
 111    uint8_t sh:1;               /* share status */
 112    uint8_t c:1;                /* cacheability */
 113    uint8_t pr:2;               /* protection key */
 114    uint8_t d:1;                /* dirty */
 115    uint8_t wt:1;               /* write through */
 116    uint8_t sa:3;               /* space attribute (PCMCIA) */
 117    uint8_t tc:1;               /* timing control */
 118} tlb_t;
 119
 120#define UTLB_SIZE 64
 121#define ITLB_SIZE 4
 122
 123#define NB_MMU_MODES 2
 124#define TARGET_INSN_START_EXTRA_WORDS 1
 125
 126enum sh_features {
 127    SH_FEATURE_SH4A = 1,
 128    SH_FEATURE_BCR3_AND_BCR4 = 2,
 129};
 130
 131typedef struct memory_content {
 132    uint32_t address;
 133    uint32_t value;
 134    struct memory_content *next;
 135} memory_content;
 136
 137typedef struct CPUSH4State {
 138    uint32_t flags;             /* general execution flags */
 139    uint32_t gregs[24];         /* general registers */
 140    float32 fregs[32];          /* floating point registers */
 141    uint32_t sr;                /* status register (with T split out) */
 142    uint32_t sr_m;              /* M bit of status register */
 143    uint32_t sr_q;              /* Q bit of status register */
 144    uint32_t sr_t;              /* T bit of status register */
 145    uint32_t ssr;               /* saved status register */
 146    uint32_t spc;               /* saved program counter */
 147    uint32_t gbr;               /* global base register */
 148    uint32_t vbr;               /* vector base register */
 149    uint32_t sgr;               /* saved global register 15 */
 150    uint32_t dbr;               /* debug base register */
 151    uint32_t pc;                /* program counter */
 152    uint32_t delayed_pc;        /* target of delayed jump */
 153    uint32_t mach;              /* multiply and accumulate high */
 154    uint32_t macl;              /* multiply and accumulate low */
 155    uint32_t pr;                /* procedure register */
 156    uint32_t fpscr;             /* floating point status/control register */
 157    uint32_t fpul;              /* floating point communication register */
 158
 159    /* float point status register */
 160    float_status fp_status;
 161
 162    /* Those belong to the specific unit (SH7750) but are handled here */
 163    uint32_t mmucr;             /* MMU control register */
 164    uint32_t pteh;              /* page table entry high register */
 165    uint32_t ptel;              /* page table entry low register */
 166    uint32_t ptea;              /* page table entry assistance register */
 167    uint32_t ttb;               /* tranlation table base register */
 168    uint32_t tea;               /* TLB exception address register */
 169    uint32_t tra;               /* TRAPA exception register */
 170    uint32_t expevt;            /* exception event register */
 171    uint32_t intevt;            /* interrupt event register */
 172
 173    tlb_t itlb[ITLB_SIZE];      /* instruction translation table */
 174    tlb_t utlb[UTLB_SIZE];      /* unified translation table */
 175
 176    uint32_t ldst;
 177
 178    CPU_COMMON
 179
 180    /* Fields from here on are preserved over CPU reset. */
 181    int id;                     /* CPU model */
 182
 183    /* The features that we should emulate. See sh_features above.  */
 184    uint32_t features;
 185
 186    void *intc_handle;
 187    int in_sleep;               /* SR_BL ignored during sleep */
 188    memory_content *movcal_backup;
 189    memory_content **movcal_backup_tail;
 190} CPUSH4State;
 191
 192/**
 193 * SuperHCPU:
 194 * @env: #CPUSH4State
 195 *
 196 * A SuperH CPU.
 197 */
 198struct SuperHCPU {
 199    /*< private >*/
 200    CPUState parent_obj;
 201    /*< public >*/
 202
 203    CPUSH4State env;
 204};
 205
 206static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env)
 207{
 208    return container_of(env, SuperHCPU, env);
 209}
 210
 211#define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e))
 212
 213#define ENV_OFFSET offsetof(SuperHCPU, env)
 214
 215void superh_cpu_do_interrupt(CPUState *cpu);
 216bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
 217void superh_cpu_dump_state(CPUState *cpu, FILE *f,
 218                           fprintf_function cpu_fprintf, int flags);
 219hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 220int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 221int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 222
 223void sh4_translate_init(void);
 224SuperHCPU *cpu_sh4_init(const char *cpu_model);
 225int cpu_sh4_signal_handler(int host_signum, void *pinfo,
 226                           void *puc);
 227int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 228                                int mmu_idx);
 229
 230void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 231#if !defined(CONFIG_USER_ONLY)
 232void cpu_sh4_invalidate_tlb(CPUSH4State *s);
 233uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
 234                                       hwaddr addr);
 235void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
 236                                    uint32_t mem_value);
 237uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
 238                                       hwaddr addr);
 239void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
 240                                    uint32_t mem_value);
 241uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
 242                                       hwaddr addr);
 243void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
 244                                    uint32_t mem_value);
 245uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
 246                                       hwaddr addr);
 247void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
 248                                    uint32_t mem_value);
 249#endif
 250
 251int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
 252
 253void cpu_load_tlb(CPUSH4State * env);
 254
 255#define cpu_init(cpu_model) CPU(cpu_sh4_init(cpu_model))
 256
 257#define cpu_signal_handler cpu_sh4_signal_handler
 258#define cpu_list sh4_cpu_list
 259
 260/* MMU modes definitions */
 261#define MMU_MODE0_SUFFIX _kernel
 262#define MMU_MODE1_SUFFIX _user
 263#define MMU_USER_IDX 1
 264static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
 265{
 266    return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
 267}
 268
 269#include "exec/cpu-all.h"
 270
 271/* Memory access type */
 272enum {
 273    /* Privilege */
 274    ACCESS_PRIV = 0x01,
 275    /* Direction */
 276    ACCESS_WRITE = 0x02,
 277    /* Type of instruction */
 278    ACCESS_CODE = 0x10,
 279    ACCESS_INT = 0x20
 280};
 281
 282/* MMU control register */
 283#define MMUCR    0x1F000010
 284#define MMUCR_AT (1<<0)
 285#define MMUCR_TI (1<<2)
 286#define MMUCR_SV (1<<8)
 287#define MMUCR_URC_BITS (6)
 288#define MMUCR_URC_OFFSET (10)
 289#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
 290#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
 291static inline int cpu_mmucr_urc (uint32_t mmucr)
 292{
 293    return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
 294}
 295
 296/* PTEH : Page Translation Entry High register */
 297#define PTEH_ASID_BITS (8)
 298#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
 299#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
 300#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
 301#define PTEH_VPN_BITS (22)
 302#define PTEH_VPN_OFFSET (10)
 303#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
 304#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
 305static inline int cpu_pteh_vpn (uint32_t pteh)
 306{
 307    return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
 308}
 309
 310/* PTEL : Page Translation Entry Low register */
 311#define PTEL_V        (1 << 8)
 312#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
 313#define PTEL_C        (1 << 3)
 314#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
 315#define PTEL_D        (1 << 2)
 316#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
 317#define PTEL_SH       (1 << 1)
 318#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
 319#define PTEL_WT       (1 << 0)
 320#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
 321
 322#define PTEL_SZ_HIGH_OFFSET  (7)
 323#define PTEL_SZ_HIGH  (1 << PTEL_SZ_HIGH_OFFSET)
 324#define PTEL_SZ_LOW_OFFSET   (4)
 325#define PTEL_SZ_LOW   (1 << PTEL_SZ_LOW_OFFSET)
 326static inline int cpu_ptel_sz (uint32_t ptel)
 327{
 328    int sz;
 329    sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
 330    sz <<= 1;
 331    sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
 332    return sz;
 333}
 334
 335#define PTEL_PPN_BITS (19)
 336#define PTEL_PPN_OFFSET (10)
 337#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
 338#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
 339static inline int cpu_ptel_ppn (uint32_t ptel)
 340{
 341    return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
 342}
 343
 344#define PTEL_PR_BITS   (2)
 345#define PTEL_PR_OFFSET (5)
 346#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
 347#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
 348static inline int cpu_ptel_pr (uint32_t ptel)
 349{
 350    return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
 351}
 352
 353/* PTEA : Page Translation Entry Assistance register */
 354#define PTEA_SA_BITS (3)
 355#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
 356#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
 357#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
 358#define PTEA_TC        (1 << 3)
 359#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
 360
 361#define TB_FLAG_PENDING_MOVCA  (1 << 4)
 362
 363static inline target_ulong cpu_read_sr(CPUSH4State *env)
 364{
 365    return env->sr | (env->sr_m << SR_M) |
 366                     (env->sr_q << SR_Q) |
 367                     (env->sr_t << SR_T);
 368}
 369
 370static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
 371{
 372    env->sr_m = (sr >> SR_M) & 1;
 373    env->sr_q = (sr >> SR_Q) & 1;
 374    env->sr_t = (sr >> SR_T) & 1;
 375    env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
 376}
 377
 378static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
 379                                        target_ulong *cs_base, uint32_t *flags)
 380{
 381    *pc = env->pc;
 382    *cs_base = 0;
 383    *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
 384                    | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME))   /* Bits  0- 3 */
 385            | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 */
 386            | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))      /* Bits 29-30 */
 387            | (env->sr & (1u << SR_FD))                        /* Bit 15 */
 388            | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
 389}
 390
 391#endif /* SH4_CPU_H */
 392