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25#include "qemu/osdep.h"
26#include <getopt.h>
27
28#include "libqtest.h"
29#include "libqos/libqos-pc.h"
30#include "libqos/ahci.h"
31#include "libqos/pci-pc.h"
32
33#include "qemu-common.h"
34#include "qemu/host-utils.h"
35
36#include "hw/pci/pci_ids.h"
37#include "hw/pci/pci_regs.h"
38
39
40#define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
41#define TEST_IMAGE_SIZE_MB_SMALL 64
42
43
44static char tmp_path[] = "/tmp/qtest.XXXXXX";
45static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
46static char mig_socket[] = "/tmp/qtest-migration.XXXXXX";
47static bool ahci_pedantic;
48static const char *imgfmt;
49static unsigned test_image_size_mb;
50
51
52static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
53static void ahci_test_pci_spec(AHCIQState *ahci);
54static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
55 uint8_t offset);
56static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
57static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
58static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
59
60
61
62static uint64_t mb_to_sectors(uint64_t image_size_mb)
63{
64 return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE;
65}
66
67static void string_bswap16(uint16_t *s, size_t bytes)
68{
69 g_assert_cmphex((bytes & 1), ==, 0);
70 bytes /= 2;
71
72 while (bytes--) {
73 *s = bswap16(*s);
74 s++;
75 }
76}
77
78
79
80
81static void verify_state(AHCIQState *ahci)
82{
83 int i, j;
84 uint32_t ahci_fingerprint;
85 uint64_t hba_base;
86 uint64_t hba_stored;
87 AHCICommandHeader cmd;
88
89 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID);
90 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint);
91
92
93 if (!ahci->hba_base) {
94 return;
95 }
96
97 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
98 hba_stored = (uint64_t)(uintptr_t)ahci->hba_base;
99 g_assert_cmphex(hba_base, ==, hba_stored);
100
101 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap);
102 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2);
103
104 for (i = 0; i < 32; i++) {
105 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==,
106 ahci->port[i].fb);
107 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==,
108 ahci->port[i].clb);
109 for (j = 0; j < 32; j++) {
110 ahci_get_command_header(ahci, i, j, &cmd);
111 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]);
112 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]);
113 }
114 }
115}
116
117static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri)
118{
119 QOSState *tmp = to->parent;
120 QPCIDevice *dev = to->dev;
121 char *uri_local = NULL;
122
123 if (uri == NULL) {
124 uri_local = g_strdup_printf("%s%s", "unix:", mig_socket);
125 uri = uri_local;
126 }
127
128
129 migrate(from->parent, to->parent, uri);
130
131
132
133
134 memcpy(to, from, sizeof(AHCIQState));
135 to->parent = tmp;
136 to->dev = dev;
137
138 tmp = from->parent;
139 dev = from->dev;
140 memset(from, 0x00, sizeof(AHCIQState));
141 from->parent = tmp;
142 from->dev = dev;
143
144 verify_state(to);
145 g_free(uri_local);
146}
147
148
149
150
151
152
153static AHCIQState *ahci_vboot(const char *cli, va_list ap)
154{
155 AHCIQState *s;
156
157 s = g_malloc0(sizeof(AHCIQState));
158 s->parent = qtest_pc_vboot(cli, ap);
159 alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT);
160
161
162 s->dev = get_ahci_device(&s->fingerprint);
163
164 return s;
165}
166
167
168
169
170static AHCIQState *ahci_boot(const char *cli, ...)
171{
172 AHCIQState *s;
173 va_list ap;
174
175 if (cli) {
176 va_start(ap, cli);
177 s = ahci_vboot(cli, ap);
178 va_end(ap);
179 } else {
180 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
181 ",format=%s"
182 " -M q35 "
183 "-device ide-hd,drive=drive0 "
184 "-global ide-hd.ver=%s";
185 s = ahci_boot(cli, tmp_path, "testdisk", imgfmt, "version");
186 }
187
188 return s;
189}
190
191
192
193
194static void ahci_shutdown(AHCIQState *ahci)
195{
196 QOSState *qs = ahci->parent;
197
198 set_context(qs);
199 ahci_clean_mem(ahci);
200 free_ahci_device(ahci->dev);
201 g_free(ahci);
202 qtest_shutdown(qs);
203}
204
205
206
207
208
209static AHCIQState *ahci_boot_and_enable(const char *cli, ...)
210{
211 AHCIQState *ahci;
212 va_list ap;
213 uint16_t buff[256];
214 uint8_t port;
215 uint8_t hello;
216
217 if (cli) {
218 va_start(ap, cli);
219 ahci = ahci_vboot(cli, ap);
220 va_end(ap);
221 } else {
222 ahci = ahci_boot(NULL);
223 }
224
225 ahci_pci_enable(ahci);
226 ahci_hba_enable(ahci);
227
228 port = ahci_port_select(ahci);
229 ahci_port_clear(ahci, port);
230 if (is_atapi(ahci, port)) {
231 hello = CMD_PACKET_ID;
232 } else {
233 hello = CMD_IDENTIFY;
234 }
235 ahci_io(ahci, port, hello, &buff, sizeof(buff), 0);
236
237 return ahci;
238}
239
240
241
242
243
244
245static void ahci_test_pci_spec(AHCIQState *ahci)
246{
247 uint8_t datab;
248 uint16_t data;
249 uint32_t datal;
250
251
252 data = qpci_config_readw(ahci->dev, PCI_COMMAND);
253 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
254 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
255 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL);
256 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE);
257 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
258 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT);
259 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
260 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
261 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
262 ASSERT_BIT_CLEAR(data, 0xF800);
263
264 data = qpci_config_readw(ahci->dev, PCI_STATUS);
265 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04);
266 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
267 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST);
268 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF);
269 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
270 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
271 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
272 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
273 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
274 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
275
276
277 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
278 if (ahci_pedantic) {
279
280
281 ASSERT_BIT_CLEAR(datal, 0xFF);
282 }
283
284
285 g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
286 if (PCI_SCC(datal) == 0x01) {
287
288 ASSERT_BIT_SET(0x80000000, datal);
289 ASSERT_BIT_CLEAR(0x60000000, datal);
290 } else if (PCI_SCC(datal) == 0x04) {
291
292 g_assert_cmphex(PCI_PI(datal), ==, 0);
293 } else if (PCI_SCC(datal) == 0x06) {
294
295 g_assert_cmphex(PCI_PI(datal), ==, 0x01);
296 } else {
297 g_assert_not_reached();
298 }
299
300 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
301 g_assert_cmphex(datab, ==, 0);
302
303 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
304 g_assert_cmphex(datab, ==, 0);
305
306
307 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
308 ASSERT_BIT_CLEAR(datab, 0x7F);
309
310
311 datab = qpci_config_readb(ahci->dev, PCI_BIST);
312 ASSERT_BIT_CLEAR(datab, 0x7F);
313
314
315 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
316 g_assert_cmphex(datal, ==, 0);
317
318 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
319 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
320
321
322 ASSERT_BIT_CLEAR(datal, 0xFF);
323
324
325 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
326
327 ASSERT_BIT_CLEAR(datal, ~0xFF);
328 g_assert_cmphex(datal, !=, 0);
329
330
331 data = qpci_config_readw(ahci->dev, datal);
332
333 switch (ahci->fingerprint) {
334 case AHCI_INTEL_ICH9:
335
336 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
337 break;
338 default:
339
340 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
341 }
342
343 ahci_test_pci_caps(ahci, data, (uint8_t)datal);
344
345
346 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
347 g_assert_cmphex(datal, ==, 0);
348
349
350 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
351 g_assert_cmphex(datab, ==, 0);
352}
353
354
355
356
357static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
358 uint8_t offset)
359{
360 uint8_t cid = header & 0xFF;
361 uint8_t next = header >> 8;
362
363 g_test_message("CID: %02x; next: %02x", cid, next);
364
365 switch (cid) {
366 case PCI_CAP_ID_PM:
367 ahci_test_pmcap(ahci, offset);
368 break;
369 case PCI_CAP_ID_MSI:
370 ahci_test_msicap(ahci, offset);
371 break;
372 case PCI_CAP_ID_SATA:
373 ahci_test_satacap(ahci, offset);
374 break;
375
376 default:
377 g_test_message("Unknown CAP 0x%02x", cid);
378 }
379
380 if (next) {
381 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
382 }
383}
384
385
386
387
388static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
389{
390 uint16_t dataw;
391 uint32_t datal;
392
393 g_test_message("Verifying SATACAP");
394
395
396 dataw = qpci_config_readw(ahci->dev, offset + 2);
397 g_assert_cmphex(dataw, ==, 0x10);
398
399
400 datal = qpci_config_readw(ahci->dev, offset + 4);
401
402 switch (datal & 0x0F) {
403 case 0x04:
404 case 0x05:
405 case 0x06:
406 case 0x07:
407 case 0x08:
408 case 0x09:
409 case 0x0F:
410 break;
411 default:
412
413 g_assert_not_reached();
414 }
415
416
417 g_assert_cmphex((datal >> 24), ==, 0x00);
418}
419
420
421
422
423static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
424{
425 uint16_t dataw;
426 uint32_t datal;
427
428 g_test_message("Verifying MSICAP");
429
430 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
431 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
432 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
433 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
434
435 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
436 g_assert_cmphex(datal, ==, 0);
437
438 if (dataw & PCI_MSI_FLAGS_64BIT) {
439 g_test_message("MSICAP is 64bit");
440 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
441 g_assert_cmphex(datal, ==, 0);
442 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
443 g_assert_cmphex(dataw, ==, 0);
444 } else {
445 g_test_message("MSICAP is 32bit");
446 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
447 g_assert_cmphex(dataw, ==, 0);
448 }
449}
450
451
452
453
454static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
455{
456 uint16_t dataw;
457
458 g_test_message("Verifying PMCAP");
459
460 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
461 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
462 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
463 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
464 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
465
466 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
467 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
468 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
469 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
470 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
471}
472
473static void ahci_test_hba_spec(AHCIQState *ahci)
474{
475 unsigned i;
476 uint32_t reg;
477 uint32_t ports;
478 uint8_t nports_impl;
479 uint8_t maxports;
480
481 g_assert(ahci != NULL);
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
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498
499
500
501
502
503
504 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
505 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
506
507
508 reg = ahci_rreg(ahci, AHCI_GHC);
509 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
510 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
511 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
512 if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
513 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
514 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
515 } else {
516 g_test_message("Supports AHCI/Legacy mix.");
517 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
518 }
519
520
521 reg = ahci_rreg(ahci, AHCI_IS);
522 g_assert_cmphex(reg, ==, 0);
523
524
525 ports = ahci_rreg(ahci, AHCI_PI);
526
527 g_assert_cmphex(ports, !=, 0);
528
529 nports_impl = ctpopl(ports);
530 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
531
532
533
534
535 g_assert_cmphex(ahci->barsize, >, 0);
536 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
537
538 g_assert_cmphex((reg >> maxports), ==, 0);
539
540
541 reg = ahci_rreg(ahci, AHCI_VS);
542 switch (reg) {
543 case AHCI_VERSION_0_95:
544 case AHCI_VERSION_1_0:
545 case AHCI_VERSION_1_1:
546 case AHCI_VERSION_1_2:
547 case AHCI_VERSION_1_3:
548 break;
549 default:
550 g_assert_not_reached();
551 }
552
553
554 reg = ahci_rreg(ahci, AHCI_CCCCTL);
555 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
556 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
557 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
558 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
559 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
560 } else {
561 g_assert_cmphex(reg, ==, 0);
562 }
563
564
565 reg = ahci_rreg(ahci, AHCI_CCCPORTS);
566
567 g_assert_cmphex(reg, ==, 0);
568
569
570 reg = ahci_rreg(ahci, AHCI_EMLOC);
571 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
572 g_assert_cmphex(reg, ==, 0);
573 }
574
575
576 reg = ahci_rreg(ahci, AHCI_EMCTL);
577 if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
578 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
579 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
580 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
581 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
582 } else {
583 g_assert_cmphex(reg, ==, 0);
584 }
585
586
587 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
588 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
589
590
591 reg = ahci_rreg(ahci, AHCI_BOHC);
592 g_assert_cmphex(reg, ==, 0);
593
594
595 g_test_message("Verifying HBA reserved area is empty.");
596 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
597 reg = ahci_rreg(ahci, i);
598 g_assert_cmphex(reg, ==, 0);
599 }
600
601
602 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
603 g_test_message("Verifying HBA/NVMHCI area is empty.");
604 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
605 reg = ahci_rreg(ahci, i);
606 g_assert_cmphex(reg, ==, 0);
607 }
608 }
609
610
611 g_test_message("Verifying HBA/Vendor area is empty.");
612 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
613 reg = ahci_rreg(ahci, i);
614 g_assert_cmphex(reg, ==, 0);
615 }
616
617
618 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
619 if (BITSET(ports, 0x1)) {
620 g_test_message("Testing port %u for spec", i);
621 ahci_test_port_spec(ahci, i);
622 } else {
623 uint16_t j;
624 uint16_t low = AHCI_PORTS + (32 * i);
625 uint16_t high = AHCI_PORTS + (32 * (i + 1));
626 g_test_message("Asserting unimplemented port %u "
627 "(reg [%u-%u]) is empty.",
628 i, low, high - 1);
629 for (j = low; j < high; ++j) {
630 reg = ahci_rreg(ahci, j);
631 g_assert_cmphex(reg, ==, 0);
632 }
633 }
634 }
635}
636
637
638
639
640static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
641{
642 uint32_t reg;
643 unsigned i;
644
645
646 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
647 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
648
649
650 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
651 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
652 g_assert_cmphex(reg, ==, 0);
653 }
654
655
656 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
657 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
658
659
660 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
661 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
662 g_assert_cmphex(reg, ==, 0);
663 }
664
665
666 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
667 g_assert_cmphex(reg, ==, 0);
668
669
670 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
671 g_assert_cmphex(reg, ==, 0);
672
673
674 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
675 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
676 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
677 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
678 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
679 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
680 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA);
681 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE);
682 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
683 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
684 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE);
685 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP);
686 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
687
688 if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
690 }
691
692 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
693 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
694 }
695
696 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
697 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
698 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
699 }
700
701 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
702 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
703 }
704
705 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
706
707 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
708 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
709 }
710
711
712 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
713 g_assert_cmphex(reg, ==, 0);
714
715
716 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
717
718
719 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
720 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
721 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
722 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
723 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
724 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
725 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
726
727
728
729
730
731
732
733
734 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
735 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
736
737
738
739
740 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
741 g_assert_cmphex(reg, ==, 0);
742
743
744 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
745 g_assert_cmphex(reg, ==, 0);
746
747
748 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
749 g_assert_cmphex(reg, ==, 0);
750
751
752 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
753 g_assert_cmphex(reg, ==, 0);
754
755
756 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
757 g_assert_cmphex(reg, ==, 0);
758
759
760 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
761 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
762 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
763 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
764 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
765 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
766 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
767 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
768
769 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
770 }
771
772
773 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
774 reg = ahci_px_rreg(ahci, port, i);
775 g_assert_cmphex(reg, ==, 0);
776 }
777
778
779 for (i = AHCI_PX_VS; i < 32; ++i) {
780 reg = ahci_px_rreg(ahci, port, i);
781 if (reg) {
782 g_test_message("INFO: Vendor register %u non-empty", i);
783 }
784 }
785}
786
787
788
789
790
791static void ahci_test_identify(AHCIQState *ahci)
792{
793 uint16_t buff[256];
794 unsigned px;
795 int rc;
796 uint16_t sect_size;
797 const size_t buffsize = 512;
798
799 g_assert(ahci != NULL);
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823 px = ahci_port_select(ahci);
824 g_test_message("Selected port %u for test", px);
825
826
827 ahci_port_clear(ahci, px);
828
829
830 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0);
831
832
833
834
835
836
837 string_bswap16(&buff[10], 20);
838 rc = memcmp(&buff[10], "testdisk ", 20);
839 g_assert_cmphex(rc, ==, 0);
840
841 string_bswap16(&buff[23], 8);
842 rc = memcmp(&buff[23], "version ", 8);
843 g_assert_cmphex(rc, ==, 0);
844
845 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
846 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE);
847}
848
849static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
850 uint64_t sector, uint8_t read_cmd,
851 uint8_t write_cmd)
852{
853 uint64_t ptr;
854 uint8_t port;
855 unsigned char *tx = g_malloc(bufsize);
856 unsigned char *rx = g_malloc0(bufsize);
857
858 g_assert(ahci != NULL);
859
860
861 port = ahci_port_select(ahci);
862 ahci_port_clear(ahci, port);
863
864
865
866 ptr = ahci_alloc(ahci, bufsize);
867 g_assert(ptr);
868
869
870 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
871 bufwrite(ptr, tx, bufsize);
872
873
874 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector);
875 qmemset(ptr, 0x00, bufsize);
876 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector);
877
878
879 bufread(ptr, rx, bufsize);
880 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
881
882 ahci_free(ahci, ptr);
883 g_free(tx);
884 g_free(rx);
885}
886
887static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd)
888{
889 uint8_t port;
890
891
892 port = ahci_port_select(ahci);
893 ahci_port_clear(ahci, port);
894
895 ahci_io(ahci, port, ide_cmd, NULL, 0, 0);
896
897 return port;
898}
899
900static void ahci_test_flush(AHCIQState *ahci)
901{
902 ahci_test_nondata(ahci, CMD_FLUSH_CACHE);
903}
904
905static void ahci_test_max(AHCIQState *ahci)
906{
907 RegD2HFIS *d2h = g_malloc0(0x20);
908 uint64_t nsect;
909 uint8_t port;
910 uint8_t cmd;
911 uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1;
912
913 if (config_sect > 0xFFFFFF) {
914 cmd = CMD_READ_MAX_EXT;
915 } else {
916 cmd = CMD_READ_MAX;
917 }
918
919 port = ahci_test_nondata(ahci, cmd);
920 memread(ahci->port[port].fb + 0x40, d2h, 0x20);
921 nsect = (uint64_t)d2h->lba_hi[2] << 40 |
922 (uint64_t)d2h->lba_hi[1] << 32 |
923 (uint64_t)d2h->lba_hi[0] << 24 |
924 (uint64_t)d2h->lba_lo[2] << 16 |
925 (uint64_t)d2h->lba_lo[1] << 8 |
926 (uint64_t)d2h->lba_lo[0];
927
928 g_assert_cmphex(nsect, ==, config_sect);
929 g_free(d2h);
930}
931
932
933
934
935
936
937
938
939
940static void test_sanity(void)
941{
942 AHCIQState *ahci;
943 ahci = ahci_boot(NULL);
944 ahci_shutdown(ahci);
945}
946
947
948
949
950
951static void test_pci_spec(void)
952{
953 AHCIQState *ahci;
954 ahci = ahci_boot(NULL);
955 ahci_test_pci_spec(ahci);
956 ahci_shutdown(ahci);
957}
958
959
960
961
962
963static void test_pci_enable(void)
964{
965 AHCIQState *ahci;
966 ahci = ahci_boot(NULL);
967 ahci_pci_enable(ahci);
968 ahci_shutdown(ahci);
969}
970
971
972
973
974
975static void test_hba_spec(void)
976{
977 AHCIQState *ahci;
978
979 ahci = ahci_boot(NULL);
980 ahci_pci_enable(ahci);
981 ahci_test_hba_spec(ahci);
982 ahci_shutdown(ahci);
983}
984
985
986
987
988
989static void test_hba_enable(void)
990{
991 AHCIQState *ahci;
992
993 ahci = ahci_boot(NULL);
994 ahci_pci_enable(ahci);
995 ahci_hba_enable(ahci);
996 ahci_shutdown(ahci);
997}
998
999
1000
1001
1002
1003static void test_identify(void)
1004{
1005 AHCIQState *ahci;
1006
1007 ahci = ahci_boot_and_enable(NULL);
1008 ahci_test_identify(ahci);
1009 ahci_shutdown(ahci);
1010}
1011
1012
1013
1014
1015
1016
1017
1018static void test_dma_fragmented(void)
1019{
1020 AHCIQState *ahci;
1021 AHCICommand *cmd;
1022 uint8_t px;
1023 size_t bufsize = 4096;
1024 unsigned char *tx = g_malloc(bufsize);
1025 unsigned char *rx = g_malloc0(bufsize);
1026 uint64_t ptr;
1027
1028 ahci = ahci_boot_and_enable(NULL);
1029 px = ahci_port_select(ahci);
1030 ahci_port_clear(ahci, px);
1031
1032
1033 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1034
1035
1036 ptr = guest_alloc(ahci->parent->alloc, bufsize);
1037 g_assert(ptr);
1038 bufwrite(ptr, tx, bufsize);
1039
1040 cmd = ahci_command_create(CMD_WRITE_DMA);
1041 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1042 ahci_command_commit(ahci, cmd, px);
1043 ahci_command_issue(ahci, cmd);
1044 ahci_command_verify(ahci, cmd);
1045 ahci_command_free(cmd);
1046
1047 cmd = ahci_command_create(CMD_READ_DMA);
1048 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1049 ahci_command_commit(ahci, cmd, px);
1050 ahci_command_issue(ahci, cmd);
1051 ahci_command_verify(ahci, cmd);
1052 ahci_command_free(cmd);
1053
1054
1055 bufread(ptr, rx, bufsize);
1056 guest_free(ahci->parent->alloc, ptr);
1057
1058 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1059
1060 ahci_shutdown(ahci);
1061
1062 g_free(rx);
1063 g_free(tx);
1064}
1065
1066
1067
1068
1069
1070static void make_dirty(AHCIQState* ahci, uint8_t port)
1071{
1072 uint64_t ptr;
1073 unsigned bufsize = 512;
1074
1075 ptr = ahci_alloc(ahci, bufsize);
1076 g_assert(ptr);
1077
1078 ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize, 1);
1079 ahci_free(ahci, ptr);
1080}
1081
1082static void test_flush(void)
1083{
1084 AHCIQState *ahci;
1085 uint8_t port;
1086
1087 ahci = ahci_boot_and_enable(NULL);
1088
1089 port = ahci_port_select(ahci);
1090 ahci_port_clear(ahci, port);
1091
1092 make_dirty(ahci, port);
1093
1094 ahci_test_flush(ahci);
1095 ahci_shutdown(ahci);
1096}
1097
1098static void test_flush_retry(void)
1099{
1100 AHCIQState *ahci;
1101 AHCICommand *cmd;
1102 uint8_t port;
1103
1104 prepare_blkdebug_script(debug_path, "flush_to_disk");
1105 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1106 "format=%s,cache=writeback,"
1107 "rerror=stop,werror=stop "
1108 "-M q35 "
1109 "-device ide-hd,drive=drive0 ",
1110 debug_path,
1111 tmp_path, imgfmt);
1112
1113 port = ahci_port_select(ahci);
1114 ahci_port_clear(ahci, port);
1115
1116
1117 make_dirty(ahci, port);
1118
1119
1120 cmd = ahci_guest_io_halt(ahci, port, CMD_FLUSH_CACHE, 0, 0, 0);
1121 ahci_guest_io_resume(ahci, cmd);
1122
1123 ahci_shutdown(ahci);
1124}
1125
1126
1127
1128
1129static void test_migrate_sanity(void)
1130{
1131 AHCIQState *src, *dst;
1132 char *uri = g_strdup_printf("unix:%s", mig_socket);
1133
1134 src = ahci_boot("-m 1024 -M q35 "
1135 "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt);
1136 dst = ahci_boot("-m 1024 -M q35 "
1137 "-drive if=ide,file=%s,format=%s "
1138 "-incoming %s", tmp_path, imgfmt, uri);
1139
1140 ahci_migrate(src, dst, uri);
1141
1142 ahci_shutdown(src);
1143 ahci_shutdown(dst);
1144 g_free(uri);
1145}
1146
1147
1148
1149
1150static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write)
1151{
1152 AHCIQState *src, *dst;
1153 uint8_t px;
1154 size_t bufsize = 4096;
1155 unsigned char *tx = g_malloc(bufsize);
1156 unsigned char *rx = g_malloc0(bufsize);
1157 char *uri = g_strdup_printf("unix:%s", mig_socket);
1158
1159 src = ahci_boot_and_enable("-m 1024 -M q35 "
1160 "-drive if=ide,format=%s,file=%s ",
1161 imgfmt, tmp_path);
1162 dst = ahci_boot("-m 1024 -M q35 "
1163 "-drive if=ide,format=%s,file=%s "
1164 "-incoming %s", imgfmt, tmp_path, uri);
1165
1166 set_context(src->parent);
1167
1168
1169 px = ahci_port_select(src);
1170 ahci_port_clear(src, px);
1171
1172
1173 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1174
1175
1176 ahci_io(src, px, cmd_write, tx, bufsize, 0);
1177 ahci_migrate(src, dst, uri);
1178 ahci_io(dst, px, cmd_read, rx, bufsize, 0);
1179
1180
1181 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1182
1183 ahci_shutdown(src);
1184 ahci_shutdown(dst);
1185 g_free(rx);
1186 g_free(tx);
1187 g_free(uri);
1188}
1189
1190static void test_migrate_dma(void)
1191{
1192 ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA);
1193}
1194
1195static void test_migrate_ncq(void)
1196{
1197 ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1198}
1199
1200
1201
1202
1203
1204
1205
1206
1207static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write)
1208{
1209 AHCIQState *ahci;
1210 uint8_t port;
1211 size_t bufsize = 4096;
1212 unsigned char *tx = g_malloc(bufsize);
1213 unsigned char *rx = g_malloc0(bufsize);
1214 uint64_t ptr;
1215 AHCICommand *cmd;
1216
1217 prepare_blkdebug_script(debug_path, "write_aio");
1218
1219 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1220 "format=%s,cache=writeback,"
1221 "rerror=stop,werror=stop "
1222 "-M q35 "
1223 "-device ide-hd,drive=drive0 ",
1224 debug_path,
1225 tmp_path, imgfmt);
1226
1227
1228 port = ahci_port_select(ahci);
1229 ahci_port_clear(ahci, port);
1230
1231
1232 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1233 ptr = ahci_alloc(ahci, bufsize);
1234 g_assert(ptr);
1235 memwrite(ptr, tx, bufsize);
1236
1237
1238 cmd = ahci_guest_io_halt(ahci, port, cmd_write,
1239 ptr, bufsize, 0);
1240
1241
1242 ahci_guest_io_resume(ahci, cmd);
1243 ahci_free(ahci, ptr);
1244
1245
1246 ahci_io(ahci, port, cmd_read, rx, bufsize, 0);
1247 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1248
1249
1250 ahci_shutdown(ahci);
1251 g_free(rx);
1252 g_free(tx);
1253}
1254
1255static void test_halted_dma(void)
1256{
1257 ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA);
1258}
1259
1260static void test_halted_ncq(void)
1261{
1262 ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1263}
1264
1265
1266
1267
1268
1269
1270
1271
1272static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write)
1273{
1274 AHCIQState *src, *dst;
1275 uint8_t port;
1276 size_t bufsize = 4096;
1277 unsigned char *tx = g_malloc(bufsize);
1278 unsigned char *rx = g_malloc0(bufsize);
1279 uint64_t ptr;
1280 AHCICommand *cmd;
1281 char *uri = g_strdup_printf("unix:%s", mig_socket);
1282
1283 prepare_blkdebug_script(debug_path, "write_aio");
1284
1285 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1286 "format=%s,cache=writeback,"
1287 "rerror=stop,werror=stop "
1288 "-M q35 "
1289 "-device ide-hd,drive=drive0 ",
1290 debug_path,
1291 tmp_path, imgfmt);
1292
1293 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1294 "format=%s,cache=writeback,"
1295 "rerror=stop,werror=stop "
1296 "-M q35 "
1297 "-device ide-hd,drive=drive0 "
1298 "-incoming %s",
1299 tmp_path, imgfmt, uri);
1300
1301 set_context(src->parent);
1302
1303
1304 port = ahci_port_select(src);
1305 ahci_port_clear(src, port);
1306 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1307
1308
1309 ptr = ahci_alloc(src, bufsize);
1310 g_assert(ptr);
1311 memwrite(ptr, tx, bufsize);
1312
1313
1314 cmd = ahci_guest_io_halt(src, port, cmd_write,
1315 ptr, bufsize, 0);
1316 ahci_migrate(src, dst, uri);
1317 ahci_guest_io_resume(dst, cmd);
1318 ahci_free(dst, ptr);
1319
1320
1321 ahci_io(dst, port, cmd_read, rx, bufsize, 0);
1322
1323
1324 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1325
1326
1327 ahci_shutdown(src);
1328 ahci_shutdown(dst);
1329 g_free(rx);
1330 g_free(tx);
1331 g_free(uri);
1332}
1333
1334static void test_migrate_halted_dma(void)
1335{
1336 ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA);
1337}
1338
1339static void test_migrate_halted_ncq(void)
1340{
1341 ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1342}
1343
1344
1345
1346
1347static void test_flush_migrate(void)
1348{
1349 AHCIQState *src, *dst;
1350 AHCICommand *cmd;
1351 uint8_t px;
1352 const char *s;
1353 char *uri = g_strdup_printf("unix:%s", mig_socket);
1354
1355 prepare_blkdebug_script(debug_path, "flush_to_disk");
1356
1357 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1358 "cache=writeback,rerror=stop,werror=stop,"
1359 "format=%s "
1360 "-M q35 "
1361 "-device ide-hd,drive=drive0 ",
1362 debug_path, tmp_path, imgfmt);
1363 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1364 "cache=writeback,rerror=stop,werror=stop,"
1365 "format=%s "
1366 "-M q35 "
1367 "-device ide-hd,drive=drive0 "
1368 "-incoming %s", tmp_path, imgfmt, uri);
1369
1370 set_context(src->parent);
1371
1372 px = ahci_port_select(src);
1373 ahci_port_clear(src, px);
1374
1375
1376 make_dirty(src, px);
1377
1378
1379 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1380 ahci_command_commit(src, cmd, px);
1381 ahci_command_issue_async(src, cmd);
1382 qmp_eventwait("STOP");
1383
1384
1385 ahci_migrate(src, dst, uri);
1386
1387
1388 s = "{'execute':'cont' }";
1389 qmp_async(s);
1390 qmp_eventwait("RESUME");
1391 ahci_command_wait(dst, cmd);
1392 ahci_command_verify(dst, cmd);
1393
1394 ahci_command_free(cmd);
1395 ahci_shutdown(src);
1396 ahci_shutdown(dst);
1397 g_free(uri);
1398}
1399
1400static void test_max(void)
1401{
1402 AHCIQState *ahci;
1403
1404 ahci = ahci_boot_and_enable(NULL);
1405 ahci_test_max(ahci);
1406 ahci_shutdown(ahci);
1407}
1408
1409static void test_reset(void)
1410{
1411 AHCIQState *ahci;
1412 int i;
1413
1414 ahci = ahci_boot(NULL);
1415 ahci_test_pci_spec(ahci);
1416 ahci_pci_enable(ahci);
1417
1418 for (i = 0; i < 2; i++) {
1419 ahci_test_hba_spec(ahci);
1420 ahci_hba_enable(ahci);
1421 ahci_test_identify(ahci);
1422 ahci_test_io_rw_simple(ahci, 4096, 0,
1423 CMD_READ_DMA_EXT,
1424 CMD_WRITE_DMA_EXT);
1425 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
1426 ahci_clean_mem(ahci);
1427 }
1428
1429 ahci_shutdown(ahci);
1430}
1431
1432static void test_ncq_simple(void)
1433{
1434 AHCIQState *ahci;
1435
1436 ahci = ahci_boot_and_enable(NULL);
1437 ahci_test_io_rw_simple(ahci, 4096, 0,
1438 READ_FPDMA_QUEUED,
1439 WRITE_FPDMA_QUEUED);
1440 ahci_shutdown(ahci);
1441}
1442
1443static int prepare_iso(size_t size, unsigned char **buf, char **name)
1444{
1445 char cdrom_path[] = "/tmp/qtest.iso.XXXXXX";
1446 unsigned char *patt;
1447 ssize_t ret;
1448 int fd = mkstemp(cdrom_path);
1449
1450 g_assert(buf);
1451 g_assert(name);
1452 patt = g_malloc(size);
1453
1454
1455 generate_pattern(patt, size, ATAPI_SECTOR_SIZE);
1456 ret = write(fd, patt, size);
1457 g_assert(ret == size);
1458
1459 *name = g_strdup(cdrom_path);
1460 *buf = patt;
1461 return fd;
1462}
1463
1464static void remove_iso(int fd, char *name)
1465{
1466 unlink(name);
1467 g_free(name);
1468 close(fd);
1469}
1470
1471static int ahci_cb_cmp_buff(AHCIQState *ahci, AHCICommand *cmd,
1472 const AHCIOpts *opts)
1473{
1474 unsigned char *tx = opts->opaque;
1475 unsigned char *rx = g_malloc0(opts->size);
1476
1477 bufread(opts->buffer, rx, opts->size);
1478 g_assert_cmphex(memcmp(tx, rx, opts->size), ==, 0);
1479 g_free(rx);
1480
1481 return 0;
1482}
1483
1484static void ahci_test_cdrom(int nsectors, bool dma)
1485{
1486 AHCIQState *ahci;
1487 unsigned char *tx;
1488 char *iso;
1489 int fd;
1490 AHCIOpts opts = {
1491 .size = (ATAPI_SECTOR_SIZE * nsectors),
1492 .atapi = true,
1493 .atapi_dma = dma,
1494 .post_cb = ahci_cb_cmp_buff,
1495 };
1496
1497
1498 fd = prepare_iso(1024 * 1024, &tx, &iso);
1499 opts.opaque = tx;
1500
1501
1502 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1503 "-M q35 "
1504 "-device ide-cd,drive=drive0 ", iso);
1505
1506
1507 ahci_exec(ahci, ahci_port_select(ahci), CMD_ATAPI_READ_10, &opts);
1508
1509
1510 g_free(tx);
1511 ahci_shutdown(ahci);
1512 remove_iso(fd, iso);
1513}
1514
1515static void test_cdrom_dma(void)
1516{
1517 ahci_test_cdrom(1, true);
1518}
1519
1520static void test_cdrom_dma_multi(void)
1521{
1522 ahci_test_cdrom(3, true);
1523}
1524
1525static void test_cdrom_pio(void)
1526{
1527 ahci_test_cdrom(1, false);
1528}
1529
1530static void test_cdrom_pio_multi(void)
1531{
1532 ahci_test_cdrom(3, false);
1533}
1534
1535
1536
1537
1538enum BuffLen {
1539 LEN_BEGIN = 0,
1540 LEN_SIMPLE = LEN_BEGIN,
1541 LEN_DOUBLE,
1542 LEN_LONG,
1543 LEN_SHORT,
1544 NUM_LENGTHS
1545};
1546
1547static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
1548 "long", "short" };
1549
1550enum AddrMode {
1551 ADDR_MODE_BEGIN = 0,
1552 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
1553 ADDR_MODE_LBA48,
1554 NUM_ADDR_MODES
1555};
1556
1557static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
1558
1559enum IOMode {
1560 MODE_BEGIN = 0,
1561 MODE_PIO = MODE_BEGIN,
1562 MODE_DMA,
1563 NUM_MODES
1564};
1565
1566static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
1567
1568enum IOOps {
1569 IO_BEGIN = 0,
1570 IO_READ = IO_BEGIN,
1571 IO_WRITE,
1572 NUM_IO_OPS
1573};
1574
1575enum OffsetType {
1576 OFFSET_BEGIN = 0,
1577 OFFSET_ZERO = OFFSET_BEGIN,
1578 OFFSET_LOW,
1579 OFFSET_HIGH,
1580 NUM_OFFSETS
1581};
1582
1583static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" };
1584
1585typedef struct AHCIIOTestOptions {
1586 enum BuffLen length;
1587 enum AddrMode address_type;
1588 enum IOMode io_type;
1589 enum OffsetType offset;
1590} AHCIIOTestOptions;
1591
1592static uint64_t offset_sector(enum OffsetType ofst,
1593 enum AddrMode addr_type,
1594 uint64_t buffsize)
1595{
1596 uint64_t ceil;
1597 uint64_t nsectors;
1598
1599 switch (ofst) {
1600 case OFFSET_ZERO:
1601 return 0;
1602 case OFFSET_LOW:
1603 return 1;
1604 case OFFSET_HIGH:
1605 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff;
1606 ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1);
1607 nsectors = buffsize / AHCI_SECTOR_SIZE;
1608 return ceil - nsectors + 1;
1609 default:
1610 g_assert_not_reached();
1611 }
1612}
1613
1614
1615
1616
1617static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
1618 [MODE_PIO] = {
1619 [ADDR_MODE_LBA28] = {
1620 [IO_READ] = CMD_READ_PIO,
1621 [IO_WRITE] = CMD_WRITE_PIO },
1622 [ADDR_MODE_LBA48] = {
1623 [IO_READ] = CMD_READ_PIO_EXT,
1624 [IO_WRITE] = CMD_WRITE_PIO_EXT }
1625 },
1626 [MODE_DMA] = {
1627 [ADDR_MODE_LBA28] = {
1628 [IO_READ] = CMD_READ_DMA,
1629 [IO_WRITE] = CMD_WRITE_DMA },
1630 [ADDR_MODE_LBA48] = {
1631 [IO_READ] = CMD_READ_DMA_EXT,
1632 [IO_WRITE] = CMD_WRITE_DMA_EXT }
1633 }
1634};
1635
1636
1637
1638
1639
1640static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
1641 unsigned bufsize, uint64_t sector)
1642{
1643 AHCIQState *ahci;
1644
1645 ahci = ahci_boot_and_enable(NULL);
1646 ahci_test_io_rw_simple(ahci, bufsize, sector,
1647 io_cmds[dma][lba48][IO_READ],
1648 io_cmds[dma][lba48][IO_WRITE]);
1649 ahci_shutdown(ahci);
1650}
1651
1652
1653
1654
1655static void test_io_interface(gconstpointer opaque)
1656{
1657 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
1658 unsigned bufsize;
1659 uint64_t sector;
1660
1661 switch (opts->length) {
1662 case LEN_SIMPLE:
1663 bufsize = 4096;
1664 break;
1665 case LEN_DOUBLE:
1666 bufsize = 8192;
1667 break;
1668 case LEN_LONG:
1669 bufsize = 4096 * 64;
1670 break;
1671 case LEN_SHORT:
1672 bufsize = 512;
1673 break;
1674 default:
1675 g_assert_not_reached();
1676 }
1677
1678 sector = offset_sector(opts->offset, opts->address_type, bufsize);
1679 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector);
1680 g_free(opts);
1681 return;
1682}
1683
1684static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
1685 enum BuffLen len, enum OffsetType offset)
1686{
1687 char *name;
1688 AHCIIOTestOptions *opts;
1689
1690 opts = g_malloc(sizeof(AHCIIOTestOptions));
1691 opts->length = len;
1692 opts->address_type = addr;
1693 opts->io_type = type;
1694 opts->offset = offset;
1695
1696 name = g_strdup_printf("ahci/io/%s/%s/%s/%s",
1697 io_mode_str[type],
1698 addr_mode_str[addr],
1699 buff_len_str[len],
1700 offset_str[offset]);
1701
1702 if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) &&
1703 (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) {
1704 g_test_message("%s: skipped; test image too small", name);
1705 g_free(name);
1706 return;
1707 }
1708
1709 qtest_add_data_func(name, opts, test_io_interface);
1710 g_free(name);
1711}
1712
1713
1714
1715int main(int argc, char **argv)
1716{
1717 const char *arch;
1718 int ret;
1719 int fd;
1720 int c;
1721 int i, j, k, m;
1722
1723 static struct option long_options[] = {
1724 {"pedantic", no_argument, 0, 'p' },
1725 {0, 0, 0, 0},
1726 };
1727
1728
1729 g_test_init(&argc, &argv, NULL);
1730
1731 while (1) {
1732 c = getopt_long(argc, argv, "", long_options, NULL);
1733 if (c == -1) {
1734 break;
1735 }
1736 switch (c) {
1737 case -1:
1738 break;
1739 case 'p':
1740 ahci_pedantic = 1;
1741 break;
1742 default:
1743 fprintf(stderr, "Unrecognized ahci_test option.\n");
1744 g_assert_not_reached();
1745 }
1746 }
1747
1748
1749 arch = qtest_get_arch();
1750 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1751 g_test_message("Skipping test for non-x86");
1752 return 0;
1753 }
1754
1755
1756 fd = mkstemp(tmp_path);
1757 g_assert(fd >= 0);
1758 if (have_qemu_img()) {
1759 imgfmt = "qcow2";
1760 test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE;
1761 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE);
1762 } else {
1763 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
1764 "skipping LBA48 high-sector tests");
1765 imgfmt = "raw";
1766 test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL;
1767 ret = ftruncate(fd, test_image_size_mb * 1024 * 1024);
1768 g_assert(ret == 0);
1769 }
1770 close(fd);
1771
1772
1773 fd = mkstemp(debug_path);
1774 g_assert(fd >= 0);
1775 close(fd);
1776
1777
1778 fd = mkstemp(mig_socket);
1779 g_assert(fd >= 0);
1780 close(fd);
1781
1782
1783 qtest_add_func("/ahci/sanity", test_sanity);
1784 qtest_add_func("/ahci/pci_spec", test_pci_spec);
1785 qtest_add_func("/ahci/pci_enable", test_pci_enable);
1786 qtest_add_func("/ahci/hba_spec", test_hba_spec);
1787 qtest_add_func("/ahci/hba_enable", test_hba_enable);
1788 qtest_add_func("/ahci/identify", test_identify);
1789
1790 for (i = MODE_BEGIN; i < NUM_MODES; i++) {
1791 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
1792 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
1793 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) {
1794 create_ahci_io_test(i, j, k, m);
1795 }
1796 }
1797 }
1798 }
1799
1800 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
1801
1802 qtest_add_func("/ahci/flush/simple", test_flush);
1803 qtest_add_func("/ahci/flush/retry", test_flush_retry);
1804 qtest_add_func("/ahci/flush/migrate", test_flush_migrate);
1805
1806 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity);
1807 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma);
1808 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma);
1809 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma);
1810
1811 qtest_add_func("/ahci/max", test_max);
1812 qtest_add_func("/ahci/reset", test_reset);
1813
1814 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple);
1815 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq);
1816 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq);
1817 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq);
1818
1819 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma);
1820 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi);
1821 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio);
1822 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi);
1823
1824 ret = g_test_run();
1825
1826
1827 unlink(tmp_path);
1828 unlink(debug_path);
1829 unlink(mig_socket);
1830
1831 return ret;
1832}
1833