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25#include "qemu/osdep.h"
26
27#include "libqtest.h"
28#include "libqos/ahci.h"
29#include "libqos/pci-pc.h"
30
31#include "qemu-common.h"
32#include "qemu/host-utils.h"
33
34#include "hw/pci/pci_ids.h"
35#include "hw/pci/pci_regs.h"
36
37typedef struct AHCICommandProp {
38 uint8_t cmd;
39 bool data;
40 bool pio;
41 bool dma;
42 bool lba28;
43 bool lba48;
44 bool read;
45 bool write;
46 bool atapi;
47 bool ncq;
48 uint64_t size;
49 uint32_t interrupts;
50} AHCICommandProp;
51
52AHCICommandProp ahci_command_properties[] = {
53 { .cmd = CMD_READ_PIO, .data = true, .pio = true,
54 .lba28 = true, .read = true },
55 { .cmd = CMD_WRITE_PIO, .data = true, .pio = true,
56 .lba28 = true, .write = true },
57 { .cmd = CMD_READ_PIO_EXT, .data = true, .pio = true,
58 .lba48 = true, .read = true },
59 { .cmd = CMD_WRITE_PIO_EXT, .data = true, .pio = true,
60 .lba48 = true, .write = true },
61 { .cmd = CMD_READ_DMA, .data = true, .dma = true,
62 .lba28 = true, .read = true },
63 { .cmd = CMD_WRITE_DMA, .data = true, .dma = true,
64 .lba28 = true, .write = true },
65 { .cmd = CMD_READ_DMA_EXT, .data = true, .dma = true,
66 .lba48 = true, .read = true },
67 { .cmd = CMD_WRITE_DMA_EXT, .data = true, .dma = true,
68 .lba48 = true, .write = true },
69 { .cmd = CMD_IDENTIFY, .data = true, .pio = true,
70 .size = 512, .read = true },
71 { .cmd = READ_FPDMA_QUEUED, .data = true, .dma = true,
72 .lba48 = true, .read = true, .ncq = true },
73 { .cmd = WRITE_FPDMA_QUEUED, .data = true, .dma = true,
74 .lba48 = true, .write = true, .ncq = true },
75 { .cmd = CMD_READ_MAX, .lba28 = true },
76 { .cmd = CMD_READ_MAX_EXT, .lba48 = true },
77 { .cmd = CMD_FLUSH_CACHE, .data = false },
78 { .cmd = CMD_PACKET, .data = true, .size = 16,
79 .atapi = true, .pio = true },
80 { .cmd = CMD_PACKET_ID, .data = true, .pio = true,
81 .size = 512, .read = true }
82};
83
84struct AHCICommand {
85
86 uint8_t name;
87 uint8_t port;
88 uint8_t slot;
89 uint32_t interrupts;
90 uint64_t xbytes;
91 uint32_t prd_size;
92 uint64_t buffer;
93 AHCICommandProp *props;
94
95 AHCICommandHeader header;
96 RegH2DFIS fis;
97 unsigned char *atapi_cmd;
98};
99
100
101
102
103uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes)
104{
105 g_assert(ahci);
106 g_assert(ahci->parent);
107 return qmalloc(ahci->parent, bytes);
108}
109
110void ahci_free(AHCIQState *ahci, uint64_t addr)
111{
112 g_assert(ahci);
113 g_assert(ahci->parent);
114 qfree(ahci->parent, addr);
115}
116
117bool is_atapi(AHCIQState *ahci, uint8_t port)
118{
119 return ahci_px_rreg(ahci, port, AHCI_PX_SIG) == AHCI_SIGNATURE_CDROM;
120}
121
122
123
124
125QPCIDevice *get_ahci_device(uint32_t *fingerprint)
126{
127 QPCIDevice *ahci;
128 uint32_t ahci_fingerprint;
129 QPCIBus *pcibus;
130
131 pcibus = qpci_init_pc();
132
133
134 ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
135 g_assert(ahci != NULL);
136
137 ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID);
138
139 switch (ahci_fingerprint) {
140 case AHCI_INTEL_ICH9:
141 break;
142 default:
143
144 g_assert_not_reached();
145 }
146
147 if (fingerprint) {
148 *fingerprint = ahci_fingerprint;
149 }
150 return ahci;
151}
152
153void free_ahci_device(QPCIDevice *dev)
154{
155 QPCIBus *pcibus = dev ? dev->bus : NULL;
156
157
158 g_free(dev);
159 qpci_free_pc(pcibus);
160}
161
162
163void ahci_clean_mem(AHCIQState *ahci)
164{
165 uint8_t port, slot;
166
167 for (port = 0; port < 32; ++port) {
168 if (ahci->port[port].fb) {
169 ahci_free(ahci, ahci->port[port].fb);
170 ahci->port[port].fb = 0;
171 }
172 if (ahci->port[port].clb) {
173 for (slot = 0; slot < 32; slot++) {
174 ahci_destroy_command(ahci, port, slot);
175 }
176 ahci_free(ahci, ahci->port[port].clb);
177 ahci->port[port].clb = 0;
178 }
179 }
180}
181
182
183
184
185
186
187void ahci_pci_enable(AHCIQState *ahci)
188{
189 uint8_t reg;
190
191 start_ahci_device(ahci);
192
193 switch (ahci->fingerprint) {
194 case AHCI_INTEL_ICH9:
195
196
197 reg = qpci_config_readb(ahci->dev, 0x92);
198 reg |= 0x3F;
199 qpci_config_writeb(ahci->dev, 0x92, reg);
200
201 ASSERT_BIT_SET(qpci_config_readb(ahci->dev, 0x92), 0x3F);
202 break;
203 }
204
205}
206
207
208
209
210void start_ahci_device(AHCIQState *ahci)
211{
212
213 ahci->hba_base = qpci_iomap(ahci->dev, 5, &ahci->barsize);
214 g_assert(ahci->hba_base);
215
216
217 qpci_device_enable(ahci->dev);
218}
219
220
221
222
223
224
225void ahci_hba_enable(AHCIQState *ahci)
226{
227
228
229
230
231
232
233
234
235
236 uint32_t reg, ports_impl;
237 uint16_t i;
238 uint8_t num_cmd_slots;
239
240 g_assert(ahci != NULL);
241
242
243 ahci_set(ahci, AHCI_GHC, AHCI_GHC_AE);
244 reg = ahci_rreg(ahci, AHCI_GHC);
245 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
246
247
248 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
249 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
250
251
252 num_cmd_slots = ((ahci->cap & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
253 g_test_message("Number of Command Slots: %u", num_cmd_slots);
254
255
256 ports_impl = ahci_rreg(ahci, AHCI_PI);
257
258 for (i = 0; ports_impl; ports_impl >>= 1, ++i) {
259 if (!(ports_impl & 0x01)) {
260 continue;
261 }
262
263 g_test_message("Initializing port %u", i);
264
265 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
266 if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR |
267 AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) {
268 g_test_message("port is idle");
269 } else {
270 g_test_message("port needs to be idled");
271 ahci_px_clr(ahci, i, AHCI_PX_CMD,
272 (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE));
273
274 usleep(500000);
275 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
276 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
277 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
278 g_test_message("port is now idle");
279
280
281 }
282
283
284
285 ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20);
286 qmemset(ahci->port[i].clb, 0x00, num_cmd_slots * 0x20);
287 g_test_message("CLB: 0x%08" PRIx64, ahci->port[i].clb);
288 ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb);
289 g_assert_cmphex(ahci->port[i].clb, ==,
290 ahci_px_rreg(ahci, i, AHCI_PX_CLB));
291
292
293 ahci->port[i].fb = ahci_alloc(ahci, 0x100);
294 qmemset(ahci->port[i].fb, 0x00, 0x100);
295 g_test_message("FB: 0x%08" PRIx64, ahci->port[i].fb);
296 ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb);
297 g_assert_cmphex(ahci->port[i].fb, ==,
298 ahci_px_rreg(ahci, i, AHCI_PX_FB));
299
300
301 ahci_px_wreg(ahci, i, AHCI_PX_SERR, 0xFFFFFFFF);
302 ahci_px_wreg(ahci, i, AHCI_PX_IS, 0xFFFFFFFF);
303 ahci_wreg(ahci, AHCI_IS, (1 << i));
304
305
306 reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
307 g_assert_cmphex(reg, ==, 0);
308
309 reg = ahci_px_rreg(ahci, i, AHCI_PX_IS);
310 g_assert_cmphex(reg, ==, 0);
311
312 reg = ahci_rreg(ahci, AHCI_IS);
313 ASSERT_BIT_CLEAR(reg, (1 << i));
314
315
316 ahci_px_wreg(ahci, i, AHCI_PX_IE, 0xFFFFFFFF);
317 reg = ahci_px_rreg(ahci, i, AHCI_PX_IE);
318 g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED));
319
320
321 ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_FRE);
322 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
323 ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR);
324
325
326
327
328 reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
329 if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) {
330 ahci_px_set(ahci, i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X);
331 }
332
333 reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD);
334 if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) {
335 reg = ahci_px_rreg(ahci, i, AHCI_PX_SSTS);
336 if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) {
337
338 ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_ST);
339 ASSERT_BIT_SET(ahci_px_rreg(ahci, i, AHCI_PX_CMD),
340 AHCI_PX_CMD_CR);
341 g_test_message("Started Device %u", i);
342 } else if ((reg & AHCI_PX_SSTS_DET)) {
343
344 g_assert_not_reached();
345 }
346 }
347 }
348
349
350 ahci_set(ahci, AHCI_GHC, AHCI_GHC_IE);
351 reg = ahci_rreg(ahci, AHCI_GHC);
352 ASSERT_BIT_SET(reg, AHCI_GHC_IE);
353
354
355
356
357}
358
359
360
361
362unsigned ahci_port_select(AHCIQState *ahci)
363{
364 uint32_t ports, reg;
365 unsigned i;
366
367 ports = ahci_rreg(ahci, AHCI_PI);
368 for (i = 0; i < 32; ports >>= 1, ++i) {
369 if (ports == 0) {
370 i = 32;
371 }
372
373 if (!(ports & 0x01)) {
374 continue;
375 }
376
377 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
378 if (BITSET(reg, AHCI_PX_CMD_ST)) {
379 break;
380 }
381 }
382 g_assert(i < 32);
383 return i;
384}
385
386
387
388
389void ahci_port_clear(AHCIQState *ahci, uint8_t port)
390{
391 uint32_t reg;
392
393
394 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
395 ahci_px_wreg(ahci, port, AHCI_PX_IS, reg);
396 g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
397
398
399 qmemset(ahci->port[port].fb, 0x00, 0x100);
400}
401
402
403
404
405void ahci_port_check_error(AHCIQState *ahci, uint8_t port)
406{
407 uint32_t reg;
408
409
410 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
411 reg >>= 23;
412 g_assert_cmphex(reg, ==, 0);
413
414
415 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
416 g_assert_cmphex(reg, ==, 0);
417
418
419 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
420 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
421 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
422}
423
424void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port,
425 uint32_t intr_mask)
426{
427 uint32_t reg;
428
429
430 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
431 ASSERT_BIT_SET(reg, intr_mask);
432
433
434 ahci_px_wreg(ahci, port, AHCI_PX_IS, intr_mask);
435 g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
436}
437
438void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot)
439{
440 uint32_t reg;
441
442
443 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
444 ASSERT_BIT_CLEAR(reg, (1 << slot));
445
446
447 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
448 ASSERT_BIT_CLEAR(reg, (1 << slot));
449
450
451 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
452 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
453 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_DRQ);
454}
455
456void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot)
457{
458 RegD2HFIS *d2h = g_malloc0(0x20);
459 uint32_t reg;
460
461 memread(ahci->port[port].fb + 0x40, d2h, 0x20);
462 g_assert_cmphex(d2h->fis_type, ==, 0x34);
463
464 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
465 g_assert_cmphex((reg & AHCI_PX_TFD_ERR) >> 8, ==, d2h->error);
466 g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, d2h->status);
467
468 g_free(d2h);
469}
470
471void ahci_port_check_pio_sanity(AHCIQState *ahci, uint8_t port,
472 uint8_t slot, size_t buffsize)
473{
474 PIOSetupFIS *pio = g_malloc0(0x20);
475
476
477
478
479 memread(ahci->port[port].fb + 0x20, pio, 0x20);
480 g_assert_cmphex(pio->fis_type, ==, 0x5f);
481
482
483
484
485
486
487 if (buffsize <= UINT16_MAX) {
488 g_assert_cmphex(le16_to_cpu(pio->tx_count), ==, buffsize);
489 }
490
491 g_free(pio);
492}
493
494void ahci_port_check_cmd_sanity(AHCIQState *ahci, AHCICommand *cmd)
495{
496 AHCICommandHeader cmdh;
497
498 ahci_get_command_header(ahci, cmd->port, cmd->slot, &cmdh);
499
500 if (!cmd->props->ncq) {
501 g_assert_cmphex(cmd->xbytes, ==, cmdh.prdbc);
502 }
503}
504
505
506void ahci_get_command_header(AHCIQState *ahci, uint8_t port,
507 uint8_t slot, AHCICommandHeader *cmd)
508{
509 uint64_t ba = ahci->port[port].clb;
510 ba += slot * sizeof(AHCICommandHeader);
511 memread(ba, cmd, sizeof(AHCICommandHeader));
512
513 cmd->flags = le16_to_cpu(cmd->flags);
514 cmd->prdtl = le16_to_cpu(cmd->prdtl);
515 cmd->prdbc = le32_to_cpu(cmd->prdbc);
516 cmd->ctba = le64_to_cpu(cmd->ctba);
517}
518
519
520void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
521 uint8_t slot, AHCICommandHeader *cmd)
522{
523 AHCICommandHeader tmp = { .flags = 0 };
524 uint64_t ba = ahci->port[port].clb;
525 ba += slot * sizeof(AHCICommandHeader);
526
527 tmp.flags = cpu_to_le16(cmd->flags);
528 tmp.prdtl = cpu_to_le16(cmd->prdtl);
529 tmp.prdbc = cpu_to_le32(cmd->prdbc);
530 tmp.ctba = cpu_to_le64(cmd->ctba);
531
532 memwrite(ba, &tmp, sizeof(AHCICommandHeader));
533}
534
535void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot)
536{
537 AHCICommandHeader cmd;
538
539
540 ahci_get_command_header(ahci, port, slot, &cmd);
541 if (cmd.ctba == 0) {
542
543 goto tidy;
544 }
545
546
547 ahci_free(ahci, cmd.ctba);
548
549 tidy:
550
551 memset(&cmd, 0x00, sizeof(cmd));
552 ahci_set_command_header(ahci, port, slot, &cmd);
553 ahci->port[port].ctba[slot] = 0;
554 ahci->port[port].prdtl[slot] = 0;
555}
556
557void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd)
558{
559 RegH2DFIS tmp = cmd->fis;
560 uint64_t addr = cmd->header.ctba;
561
562
563
564
565
566 if (!cmd->props->ncq) {
567 tmp.count = cpu_to_le16(tmp.count);
568 }
569
570 memwrite(addr, &tmp, sizeof(tmp));
571}
572
573unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port)
574{
575 unsigned i;
576 unsigned j;
577 uint32_t reg;
578
579 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
580
581
582 for (i = 0; i < 32; ++i) {
583 j = ((ahci->port[port].next + i) % 32);
584 if (reg & (1 << j)) {
585 continue;
586 }
587 ahci_destroy_command(ahci, port, j);
588 ahci->port[port].next = (j + 1) % 32;
589 return j;
590 }
591
592 g_test_message("All command slots were busy.");
593 g_assert_not_reached();
594}
595
596inline unsigned size_to_prdtl(unsigned bytes, unsigned bytes_per_prd)
597{
598
599 g_assert_cmphex(bytes_per_prd, <=, 4096 * 1024);
600 g_assert_cmphex(bytes_per_prd & 0x01, ==, 0x00);
601 return (bytes + bytes_per_prd - 1) / bytes_per_prd;
602}
603
604const AHCIOpts default_opts = { .size = 0 };
605
606
607
608
609
610
611
612
613
614
615
616
617void ahci_exec(AHCIQState *ahci, uint8_t port,
618 uint8_t op, const AHCIOpts *opts_in)
619{
620 AHCICommand *cmd;
621 int rc;
622 AHCIOpts *opts;
623
624 opts = g_memdup((opts_in == NULL ? &default_opts : opts_in),
625 sizeof(AHCIOpts));
626
627
628 if (opts->size && !opts->buffer) {
629 opts->buffer = ahci_alloc(ahci, opts->size);
630 g_assert(opts->buffer);
631 qmemset(opts->buffer, 0x00, opts->size);
632 }
633
634
635 if (opts->atapi) {
636 cmd = ahci_atapi_command_create(op);
637 if (opts->atapi_dma) {
638 ahci_command_enable_atapi_dma(cmd);
639 }
640 } else {
641 cmd = ahci_command_create(op);
642 }
643 ahci_command_adjust(cmd, opts->lba, opts->buffer,
644 opts->size, opts->prd_size);
645
646 if (opts->pre_cb) {
647 rc = opts->pre_cb(ahci, cmd, opts);
648 g_assert_cmpint(rc, ==, 0);
649 }
650
651
652 ahci_command_commit(ahci, cmd, port);
653 ahci_command_issue_async(ahci, cmd);
654 if (opts->error) {
655 qmp_eventwait("STOP");
656 }
657 if (opts->mid_cb) {
658 rc = opts->mid_cb(ahci, cmd, opts);
659 g_assert_cmpint(rc, ==, 0);
660 }
661 if (opts->error) {
662 qmp_async("{'execute':'cont' }");
663 qmp_eventwait("RESUME");
664 }
665
666
667 ahci_command_wait(ahci, cmd);
668 ahci_command_verify(ahci, cmd);
669 if (opts->post_cb) {
670 rc = opts->post_cb(ahci, cmd, opts);
671 g_assert_cmpint(rc, ==, 0);
672 }
673 ahci_command_free(cmd);
674 if (opts->buffer != opts_in->buffer) {
675 ahci_free(ahci, opts->buffer);
676 }
677 g_free(opts);
678}
679
680
681AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port,
682 uint8_t ide_cmd, uint64_t buffer,
683 size_t bufsize, uint64_t sector)
684{
685 AHCICommand *cmd;
686
687 cmd = ahci_command_create(ide_cmd);
688 ahci_command_adjust(cmd, sector, buffer, bufsize, 0);
689 ahci_command_commit(ahci, cmd, port);
690 ahci_command_issue_async(ahci, cmd);
691 qmp_eventwait("STOP");
692
693 return cmd;
694}
695
696
697void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd)
698{
699
700 qmp_async("{'execute':'cont' }");
701 qmp_eventwait("RESUME");
702 ahci_command_wait(ahci, cmd);
703 ahci_command_verify(ahci, cmd);
704 ahci_command_free(cmd);
705}
706
707
708void ahci_guest_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
709 uint64_t buffer, size_t bufsize, uint64_t sector)
710{
711 AHCICommand *cmd;
712 cmd = ahci_command_create(ide_cmd);
713 ahci_command_set_buffer(cmd, buffer);
714 ahci_command_set_size(cmd, bufsize);
715 if (sector) {
716 ahci_command_set_offset(cmd, sector);
717 }
718 ahci_command_commit(ahci, cmd, port);
719 ahci_command_issue(ahci, cmd);
720 ahci_command_verify(ahci, cmd);
721 ahci_command_free(cmd);
722}
723
724static AHCICommandProp *ahci_command_find(uint8_t command_name)
725{
726 int i;
727
728 for (i = 0; i < ARRAY_SIZE(ahci_command_properties); i++) {
729 if (ahci_command_properties[i].cmd == command_name) {
730 return &ahci_command_properties[i];
731 }
732 }
733
734 return NULL;
735}
736
737
738void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
739 void *buffer, size_t bufsize, uint64_t sector)
740{
741 uint64_t ptr;
742 AHCICommandProp *props;
743
744 props = ahci_command_find(ide_cmd);
745 g_assert(props);
746 ptr = ahci_alloc(ahci, bufsize);
747 g_assert(!bufsize || ptr);
748 qmemset(ptr, 0x00, bufsize);
749
750 if (bufsize && props->write) {
751 bufwrite(ptr, buffer, bufsize);
752 }
753
754 ahci_guest_io(ahci, port, ide_cmd, ptr, bufsize, sector);
755
756 if (bufsize && props->read) {
757 bufread(ptr, buffer, bufsize);
758 }
759
760 ahci_free(ahci, ptr);
761}
762
763
764
765
766
767static void command_header_init(AHCICommand *cmd)
768{
769 AHCICommandHeader *hdr = &cmd->header;
770 AHCICommandProp *props = cmd->props;
771
772 hdr->flags = 5;
773 hdr->flags |= CMDH_CLR_BSY;
774 if (props->write) {
775 hdr->flags |= CMDH_WRITE;
776 }
777 if (props->atapi) {
778 hdr->flags |= CMDH_ATAPI;
779 }
780
781 hdr->prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
782 hdr->prdbc = 0;
783 hdr->ctba = 0;
784}
785
786static void command_table_init(AHCICommand *cmd)
787{
788 RegH2DFIS *fis = &(cmd->fis);
789 uint16_t sect_count = (cmd->xbytes / AHCI_SECTOR_SIZE);
790
791 fis->fis_type = REG_H2D_FIS;
792 fis->flags = REG_H2D_FIS_CMD;
793 fis->command = cmd->name;
794
795 if (cmd->props->ncq) {
796 NCQFIS *ncqfis = (NCQFIS *)fis;
797
798
799 ncqfis->sector_low = sect_count & 0xFF;
800 ncqfis->sector_hi = (sect_count >> 8) & 0xFF;
801 ncqfis->device = NCQ_DEVICE_MAGIC;
802
803 ncqfis->tag = 0;
804 ncqfis->prio = 0;
805
806 } else {
807 fis->feature_low = 0x00;
808 fis->feature_high = 0x00;
809 if (cmd->props->lba28 || cmd->props->lba48) {
810 fis->device = ATA_DEVICE_LBA;
811 }
812 fis->count = (cmd->xbytes / AHCI_SECTOR_SIZE);
813 }
814 fis->icc = 0x00;
815 fis->control = 0x00;
816 memset(fis->aux, 0x00, ARRAY_SIZE(fis->aux));
817}
818
819void ahci_command_enable_atapi_dma(AHCICommand *cmd)
820{
821 RegH2DFIS *fis = &(cmd->fis);
822 g_assert(cmd->props->atapi);
823 fis->feature_low |= 0x01;
824 cmd->interrupts &= ~AHCI_PX_IS_PSS;
825 cmd->props->dma = true;
826 cmd->props->pio = false;
827
828
829}
830
831AHCICommand *ahci_command_create(uint8_t command_name)
832{
833 AHCICommandProp *props = ahci_command_find(command_name);
834 AHCICommand *cmd;
835
836 g_assert(props);
837 cmd = g_malloc0(sizeof(AHCICommand));
838 g_assert(!(props->dma && props->pio));
839 g_assert(!(props->lba28 && props->lba48));
840 g_assert(!(props->read && props->write));
841 g_assert(!props->size || props->data);
842 g_assert(!props->ncq || props->lba48);
843
844
845 cmd->props = g_memdup(props, sizeof(AHCICommandProp));
846 cmd->name = command_name;
847 cmd->xbytes = props->size;
848 cmd->prd_size = 4096;
849 cmd->buffer = 0xabad1dea;
850
851 if (!cmd->props->ncq) {
852 cmd->interrupts = AHCI_PX_IS_DHRS;
853 }
854
855
856
857
858 cmd->interrupts |= props->pio ? AHCI_PX_IS_PSS : 0;
859 cmd->interrupts |= props->ncq ? AHCI_PX_IS_SDBS : 0;
860
861 command_header_init(cmd);
862 command_table_init(cmd);
863
864 return cmd;
865}
866
867AHCICommand *ahci_atapi_command_create(uint8_t scsi_cmd)
868{
869 AHCICommand *cmd = ahci_command_create(CMD_PACKET);
870 cmd->atapi_cmd = g_malloc0(16);
871 cmd->atapi_cmd[0] = scsi_cmd;
872
873
874 cmd->fis.lba_lo[1] = ATAPI_SECTOR_SIZE >> 8 & 0xFF;
875 cmd->fis.lba_lo[2] = ATAPI_SECTOR_SIZE & 0xFF;
876
877 return cmd;
878}
879
880void ahci_command_free(AHCICommand *cmd)
881{
882 g_free(cmd->atapi_cmd);
883 g_free(cmd->props);
884 g_free(cmd);
885}
886
887void ahci_command_set_flags(AHCICommand *cmd, uint16_t cmdh_flags)
888{
889 cmd->header.flags |= cmdh_flags;
890}
891
892void ahci_command_clr_flags(AHCICommand *cmd, uint16_t cmdh_flags)
893{
894 cmd->header.flags &= ~cmdh_flags;
895}
896
897static void ahci_atapi_command_set_offset(AHCICommand *cmd, uint64_t lba)
898{
899 unsigned char *cbd = cmd->atapi_cmd;
900 g_assert(cbd);
901
902 switch (cbd[0]) {
903 case CMD_ATAPI_READ_10:
904 g_assert_cmpuint(lba, <=, UINT32_MAX);
905 stl_be_p(&cbd[2], lba);
906 break;
907 default:
908
909
910 g_assert_not_reached();
911 }
912}
913
914void ahci_command_set_offset(AHCICommand *cmd, uint64_t lba_sect)
915{
916 RegH2DFIS *fis = &(cmd->fis);
917
918 if (cmd->props->atapi) {
919 ahci_atapi_command_set_offset(cmd, lba_sect);
920 return;
921 } else if (!cmd->props->data && !lba_sect) {
922
923 return;
924 } else if (cmd->props->lba28) {
925 g_assert_cmphex(lba_sect, <=, 0xFFFFFFF);
926 } else if (cmd->props->lba48 || cmd->props->ncq) {
927 g_assert_cmphex(lba_sect, <=, 0xFFFFFFFFFFFF);
928 } else {
929
930 g_assert_not_reached();
931 }
932
933
934 fis->lba_lo[0] = (lba_sect & 0xFF);
935 fis->lba_lo[1] = (lba_sect >> 8) & 0xFF;
936 fis->lba_lo[2] = (lba_sect >> 16) & 0xFF;
937 if (cmd->props->lba28) {
938 fis->device = (fis->device & 0xF0) | ((lba_sect >> 24) & 0x0F);
939 }
940 fis->lba_hi[0] = (lba_sect >> 24) & 0xFF;
941 fis->lba_hi[1] = (lba_sect >> 32) & 0xFF;
942 fis->lba_hi[2] = (lba_sect >> 40) & 0xFF;
943}
944
945void ahci_command_set_buffer(AHCICommand *cmd, uint64_t buffer)
946{
947 cmd->buffer = buffer;
948}
949
950static void ahci_atapi_set_size(AHCICommand *cmd, uint64_t xbytes)
951{
952 unsigned char *cbd = cmd->atapi_cmd;
953 uint64_t nsectors = xbytes / 2048;
954 g_assert(cbd);
955
956 switch (cbd[0]) {
957 case CMD_ATAPI_READ_10:
958 g_assert_cmpuint(nsectors, <=, UINT16_MAX);
959 stw_be_p(&cbd[7], nsectors);
960 break;
961 default:
962
963
964 g_assert_not_reached();
965 }
966}
967
968void ahci_command_set_sizes(AHCICommand *cmd, uint64_t xbytes,
969 unsigned prd_size)
970{
971 uint16_t sect_count;
972
973
974 g_assert_cmphex(prd_size, <=, 4096 * 1024);
975 g_assert_cmphex(prd_size & 0x01, ==, 0x00);
976 if (prd_size) {
977 cmd->prd_size = prd_size;
978 }
979 cmd->xbytes = xbytes;
980 sect_count = (cmd->xbytes / AHCI_SECTOR_SIZE);
981
982 if (cmd->props->ncq) {
983 NCQFIS *nfis = (NCQFIS *)&(cmd->fis);
984 nfis->sector_low = sect_count & 0xFF;
985 nfis->sector_hi = (sect_count >> 8) & 0xFF;
986 } else if (cmd->props->atapi) {
987 ahci_atapi_set_size(cmd, xbytes);
988 } else {
989 cmd->fis.count = sect_count;
990 }
991 cmd->header.prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
992}
993
994void ahci_command_set_size(AHCICommand *cmd, uint64_t xbytes)
995{
996 ahci_command_set_sizes(cmd, xbytes, cmd->prd_size);
997}
998
999void ahci_command_set_prd_size(AHCICommand *cmd, unsigned prd_size)
1000{
1001 ahci_command_set_sizes(cmd, cmd->xbytes, prd_size);
1002}
1003
1004void ahci_command_adjust(AHCICommand *cmd, uint64_t offset, uint64_t buffer,
1005 uint64_t xbytes, unsigned prd_size)
1006{
1007 ahci_command_set_sizes(cmd, xbytes, prd_size);
1008 ahci_command_set_buffer(cmd, buffer);
1009 ahci_command_set_offset(cmd, offset);
1010}
1011
1012void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)
1013{
1014 uint16_t i, prdtl;
1015 uint64_t table_size, table_ptr, remaining;
1016 PRD prd;
1017
1018
1019 cmd->port = port;
1020 cmd->slot = ahci_pick_cmd(ahci, port);
1021
1022 if (cmd->props->ncq) {
1023 NCQFIS *nfis = (NCQFIS *)&cmd->fis;
1024 nfis->tag = (cmd->slot << 3) & 0xFC;
1025 }
1026
1027
1028 prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
1029 table_size = CMD_TBL_SIZ(prdtl);
1030 table_ptr = ahci_alloc(ahci, table_size);
1031 g_assert(table_ptr);
1032
1033 g_assert((table_ptr & 0x7F) == 0x00);
1034 cmd->header.ctba = table_ptr;
1035
1036
1037 ahci_set_command_header(ahci, port, cmd->slot, &(cmd->header));
1038
1039 ahci_write_fis(ahci, cmd);
1040
1041 if (cmd->props->atapi) {
1042 memwrite(table_ptr + 0x40, cmd->atapi_cmd, 16);
1043 }
1044
1045
1046 g_assert_cmphex(prdtl, ==, cmd->header.prdtl);
1047 remaining = cmd->xbytes;
1048 for (i = 0; i < prdtl; ++i) {
1049 prd.dba = cpu_to_le64(cmd->buffer + (cmd->prd_size * i));
1050 prd.res = 0;
1051 if (remaining > cmd->prd_size) {
1052
1053 prd.dbc = cpu_to_le32(cmd->prd_size - 1);
1054 remaining -= cmd->prd_size;
1055 } else {
1056
1057 prd.dbc = cpu_to_le32(remaining - 1);
1058 remaining = 0;
1059 }
1060 prd.dbc |= cpu_to_le32(0x80000000);
1061
1062
1063 memwrite(table_ptr + 0x80 + (i * sizeof(PRD)),
1064 &prd, sizeof(PRD));
1065 }
1066
1067
1068 ahci->port[port].ctba[cmd->slot] = table_ptr;
1069 ahci->port[port].prdtl[cmd->slot] = prdtl;
1070}
1071
1072void ahci_command_issue_async(AHCIQState *ahci, AHCICommand *cmd)
1073{
1074 if (cmd->props->ncq) {
1075 ahci_px_wreg(ahci, cmd->port, AHCI_PX_SACT, (1 << cmd->slot));
1076 }
1077
1078 ahci_px_wreg(ahci, cmd->port, AHCI_PX_CI, (1 << cmd->slot));
1079}
1080
1081void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd)
1082{
1083
1084
1085
1086
1087#define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK)))
1088
1089 while (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) ||
1090 RSET(AHCI_PX_CI, 1 << cmd->slot) ||
1091 (cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot))) {
1092 usleep(50);
1093 }
1094
1095}
1096
1097void ahci_command_issue(AHCIQState *ahci, AHCICommand *cmd)
1098{
1099 ahci_command_issue_async(ahci, cmd);
1100 ahci_command_wait(ahci, cmd);
1101}
1102
1103void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd)
1104{
1105 uint8_t slot = cmd->slot;
1106 uint8_t port = cmd->port;
1107
1108 ahci_port_check_error(ahci, port);
1109 ahci_port_check_interrupts(ahci, port, cmd->interrupts);
1110 ahci_port_check_nonbusy(ahci, port, slot);
1111 ahci_port_check_cmd_sanity(ahci, cmd);
1112 if (cmd->interrupts & AHCI_PX_IS_DHRS) {
1113 ahci_port_check_d2h_sanity(ahci, port, slot);
1114 }
1115 if (cmd->props->pio) {
1116 ahci_port_check_pio_sanity(ahci, port, slot, cmd->xbytes);
1117 }
1118}
1119
1120uint8_t ahci_command_slot(AHCICommand *cmd)
1121{
1122 return cmd->slot;
1123}
1124