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10#include "qemu/osdep.h"
11#include "libqtest.h"
12#include "libqos/virtio.h"
13#include "libqos/virtio-pci.h"
14#include "libqos/pci.h"
15#include "libqos/pci-pc.h"
16#include "libqos/malloc.h"
17#include "libqos/malloc-pc.h"
18#include "standard-headers/linux/virtio_ring.h"
19#include "standard-headers/linux/virtio_pci.h"
20
21#include "hw/pci/pci.h"
22#include "hw/pci/pci_regs.h"
23
24typedef struct QVirtioPCIForeachData {
25 void (*func)(QVirtioDevice *d, void *data);
26 uint16_t device_type;
27 void *user_data;
28} QVirtioPCIForeachData;
29
30static QVirtioPCIDevice *qpcidevice_to_qvirtiodevice(QPCIDevice *pdev)
31{
32 QVirtioPCIDevice *vpcidev;
33 vpcidev = g_malloc0(sizeof(*vpcidev));
34
35 if (pdev) {
36 vpcidev->pdev = pdev;
37 vpcidev->vdev.device_type =
38 qpci_config_readw(vpcidev->pdev, PCI_SUBSYSTEM_ID);
39 }
40
41 vpcidev->config_msix_entry = -1;
42
43 return vpcidev;
44}
45
46static void qvirtio_pci_foreach_callback(
47 QPCIDevice *dev, int devfn, void *data)
48{
49 QVirtioPCIForeachData *d = data;
50 QVirtioPCIDevice *vpcidev = qpcidevice_to_qvirtiodevice(dev);
51
52 if (vpcidev->vdev.device_type == d->device_type) {
53 d->func(&vpcidev->vdev, d->user_data);
54 } else {
55 g_free(vpcidev);
56 }
57}
58
59static void qvirtio_pci_assign_device(QVirtioDevice *d, void *data)
60{
61 QVirtioPCIDevice **vpcidev = data;
62 *vpcidev = (QVirtioPCIDevice *)d;
63}
64
65static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d, uint64_t addr)
66{
67 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
68 return qpci_io_readb(dev->pdev, (void *)(uintptr_t)addr);
69}
70
71static uint16_t qvirtio_pci_config_readw(QVirtioDevice *d, uint64_t addr)
72{
73 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
74 return qpci_io_readw(dev->pdev, (void *)(uintptr_t)addr);
75}
76
77static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t addr)
78{
79 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
80 return qpci_io_readl(dev->pdev, (void *)(uintptr_t)addr);
81}
82
83static uint64_t qvirtio_pci_config_readq(QVirtioDevice *d, uint64_t addr)
84{
85 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
86 int i;
87 uint64_t u64 = 0;
88
89 if (qtest_big_endian()) {
90 for (i = 0; i < 8; ++i) {
91 u64 |= (uint64_t)qpci_io_readb(dev->pdev,
92 (void *)(uintptr_t)addr + i) << (7 - i) * 8;
93 }
94 } else {
95 for (i = 0; i < 8; ++i) {
96 u64 |= (uint64_t)qpci_io_readb(dev->pdev,
97 (void *)(uintptr_t)addr + i) << i * 8;
98 }
99 }
100
101 return u64;
102}
103
104static uint32_t qvirtio_pci_get_features(QVirtioDevice *d)
105{
106 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
107 return qpci_io_readl(dev->pdev, dev->addr + VIRTIO_PCI_HOST_FEATURES);
108}
109
110static void qvirtio_pci_set_features(QVirtioDevice *d, uint32_t features)
111{
112 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
113 qpci_io_writel(dev->pdev, dev->addr + VIRTIO_PCI_GUEST_FEATURES, features);
114}
115
116static uint32_t qvirtio_pci_get_guest_features(QVirtioDevice *d)
117{
118 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
119 return qpci_io_readl(dev->pdev, dev->addr + VIRTIO_PCI_GUEST_FEATURES);
120}
121
122static uint8_t qvirtio_pci_get_status(QVirtioDevice *d)
123{
124 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
125 return qpci_io_readb(dev->pdev, dev->addr + VIRTIO_PCI_STATUS);
126}
127
128static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status)
129{
130 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
131 qpci_io_writeb(dev->pdev, dev->addr + VIRTIO_PCI_STATUS, status);
132}
133
134static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
135{
136 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
137 QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
138 uint32_t data;
139
140 if (dev->pdev->msix_enabled) {
141 g_assert_cmpint(vqpci->msix_entry, !=, -1);
142 if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
143
144 return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
145 } else {
146 data = readl(vqpci->msix_addr);
147 if (data == vqpci->msix_data) {
148 writel(vqpci->msix_addr, 0);
149 return true;
150 } else {
151 return false;
152 }
153 }
154 } else {
155 return qpci_io_readb(dev->pdev, dev->addr + VIRTIO_PCI_ISR) & 1;
156 }
157}
158
159static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
160{
161 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
162 uint32_t data;
163
164 if (dev->pdev->msix_enabled) {
165 g_assert_cmpint(dev->config_msix_entry, !=, -1);
166 if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
167
168 return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
169 } else {
170 data = readl(dev->config_msix_addr);
171 if (data == dev->config_msix_data) {
172 writel(dev->config_msix_addr, 0);
173 return true;
174 } else {
175 return false;
176 }
177 }
178 } else {
179 return qpci_io_readb(dev->pdev, dev->addr + VIRTIO_PCI_ISR) & 2;
180 }
181}
182
183static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index)
184{
185 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
186 qpci_io_writeb(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_SEL, index);
187}
188
189static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice *d)
190{
191 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
192 return qpci_io_readw(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_NUM);
193}
194
195static void qvirtio_pci_set_queue_address(QVirtioDevice *d, uint32_t pfn)
196{
197 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
198 qpci_io_writel(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_PFN, pfn);
199}
200
201static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirtioDevice *d,
202 QGuestAllocator *alloc, uint16_t index)
203{
204 uint32_t feat;
205 uint64_t addr;
206 QVirtQueuePCI *vqpci;
207
208 vqpci = g_malloc0(sizeof(*vqpci));
209 feat = qvirtio_pci_get_guest_features(d);
210
211 qvirtio_pci_queue_select(d, index);
212 vqpci->vq.index = index;
213 vqpci->vq.size = qvirtio_pci_get_queue_size(d);
214 vqpci->vq.free_head = 0;
215 vqpci->vq.num_free = vqpci->vq.size;
216 vqpci->vq.align = VIRTIO_PCI_VRING_ALIGN;
217 vqpci->vq.indirect = (feat & (1u << VIRTIO_RING_F_INDIRECT_DESC)) != 0;
218 vqpci->vq.event = (feat & (1u << VIRTIO_RING_F_EVENT_IDX)) != 0;
219
220 vqpci->msix_entry = -1;
221 vqpci->msix_addr = 0;
222 vqpci->msix_data = 0x12345678;
223
224
225 g_assert_cmpint(vqpci->vq.size, !=, 0);
226
227
228 g_assert_cmpint(vqpci->vq.size & (vqpci->vq.size - 1), ==, 0);
229
230 addr = guest_alloc(alloc, qvring_size(vqpci->vq.size,
231 VIRTIO_PCI_VRING_ALIGN));
232 qvring_init(alloc, &vqpci->vq, addr);
233 qvirtio_pci_set_queue_address(d, vqpci->vq.desc / VIRTIO_PCI_VRING_ALIGN);
234
235 return &vqpci->vq;
236}
237
238static void qvirtio_pci_virtqueue_cleanup(QVirtQueue *vq,
239 QGuestAllocator *alloc)
240{
241 QVirtQueuePCI *vqpci = container_of(vq, QVirtQueuePCI, vq);
242
243 guest_free(alloc, vq->desc);
244 g_free(vqpci);
245}
246
247static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
248{
249 QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
250 qpci_io_writew(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_NOTIFY, vq->index);
251}
252
253const QVirtioBus qvirtio_pci = {
254 .config_readb = qvirtio_pci_config_readb,
255 .config_readw = qvirtio_pci_config_readw,
256 .config_readl = qvirtio_pci_config_readl,
257 .config_readq = qvirtio_pci_config_readq,
258 .get_features = qvirtio_pci_get_features,
259 .set_features = qvirtio_pci_set_features,
260 .get_guest_features = qvirtio_pci_get_guest_features,
261 .get_status = qvirtio_pci_get_status,
262 .set_status = qvirtio_pci_set_status,
263 .get_queue_isr_status = qvirtio_pci_get_queue_isr_status,
264 .get_config_isr_status = qvirtio_pci_get_config_isr_status,
265 .queue_select = qvirtio_pci_queue_select,
266 .get_queue_size = qvirtio_pci_get_queue_size,
267 .set_queue_address = qvirtio_pci_set_queue_address,
268 .virtqueue_setup = qvirtio_pci_virtqueue_setup,
269 .virtqueue_cleanup = qvirtio_pci_virtqueue_cleanup,
270 .virtqueue_kick = qvirtio_pci_virtqueue_kick,
271};
272
273void qvirtio_pci_foreach(QPCIBus *bus, uint16_t device_type,
274 void (*func)(QVirtioDevice *d, void *data), void *data)
275{
276 QVirtioPCIForeachData d = { .func = func,
277 .device_type = device_type,
278 .user_data = data };
279
280 qpci_device_foreach(bus, PCI_VENDOR_ID_REDHAT_QUMRANET, -1,
281 qvirtio_pci_foreach_callback, &d);
282}
283
284QVirtioPCIDevice *qvirtio_pci_device_find(QPCIBus *bus, uint16_t device_type)
285{
286 QVirtioPCIDevice *dev = NULL;
287 qvirtio_pci_foreach(bus, device_type, qvirtio_pci_assign_device, &dev);
288
289 return dev;
290}
291
292void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
293{
294 qpci_device_enable(d->pdev);
295 d->addr = qpci_iomap(d->pdev, 0, NULL);
296 g_assert(d->addr != NULL);
297}
298
299void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
300{
301 qpci_iounmap(d->pdev, d->addr);
302 d->addr = NULL;
303}
304
305void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
306 QGuestAllocator *alloc, uint16_t entry)
307{
308 uint16_t vector;
309 uint32_t control;
310 void *addr;
311
312 g_assert(d->pdev->msix_enabled);
313 addr = d->pdev->msix_table + (entry * 16);
314
315 g_assert_cmpint(entry, >=, 0);
316 g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
317 vqpci->msix_entry = entry;
318
319 vqpci->msix_addr = guest_alloc(alloc, 4);
320 qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
321 vqpci->msix_addr & ~0UL);
322 qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
323 (vqpci->msix_addr >> 32) & ~0UL);
324 qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, vqpci->msix_data);
325
326 control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
327 qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
328 control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
329
330 qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index);
331 qpci_io_writew(d->pdev, d->addr + VIRTIO_MSI_QUEUE_VECTOR, entry);
332 vector = qpci_io_readw(d->pdev, d->addr + VIRTIO_MSI_QUEUE_VECTOR);
333 g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
334}
335
336void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
337 QGuestAllocator *alloc, uint16_t entry)
338{
339 uint16_t vector;
340 uint32_t control;
341 void *addr;
342
343 g_assert(d->pdev->msix_enabled);
344 addr = d->pdev->msix_table + (entry * 16);
345
346 g_assert_cmpint(entry, >=, 0);
347 g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
348 d->config_msix_entry = entry;
349
350 d->config_msix_data = 0x12345678;
351 d->config_msix_addr = guest_alloc(alloc, 4);
352
353 qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
354 d->config_msix_addr & ~0UL);
355 qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
356 (d->config_msix_addr >> 32) & ~0UL);
357 qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, d->config_msix_data);
358
359 control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
360 qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
361 control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
362
363 qpci_io_writew(d->pdev, d->addr + VIRTIO_MSI_CONFIG_VECTOR, entry);
364 vector = qpci_io_readw(d->pdev, d->addr + VIRTIO_MSI_CONFIG_VECTOR);
365 g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
366}
367
