LXR qemu/target-arm/cpu64.c

   1/*
   2 * QEMU AArch64 CPU
   3 *
   4 * Copyright (c) 2013 Linaro Ltd
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; either version 2
   9 * of the License, or (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, see
  18 * <http://www.gnu.org/licenses/gpl-2.0.html>
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qapi/error.h"
  23#include "cpu.h"
  24#include "qemu-common.h"
  25#if !defined(CONFIG_USER_ONLY)
  26#include "hw/loader.h"
  27#endif
  28#include "hw/arm/arm.h"
  29#include "sysemu/sysemu.h"
  30#include "sysemu/kvm.h"
  31
  32static inline void set_feature(CPUARMState *env, int feature)
  33{
  34    env->features |= 1ULL << feature;
  35}
  36
  37static inline void unset_feature(CPUARMState *env, int feature)
  38{
  39    env->features &= ~(1ULL << feature);
  40}
  41
  42#ifndef CONFIG_USER_ONLY
  43static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  44{
  45    /* Number of processors is in [25:24]; otherwise we RAZ */
  46    return (smp_cpus - 1) << 24;
  47}
  48#endif
  49
  50static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
  51#ifndef CONFIG_USER_ONLY
  52    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
  53      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
  54      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  55      .writefn = arm_cp_write_ignore },
  56    { .name = "L2CTLR",
  57      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
  58      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  59      .writefn = arm_cp_write_ignore },
  60#endif
  61    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
  62      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
  63      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  64    { .name = "L2ECTLR",
  65      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
  66      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  67    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
  68      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
  69      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  70    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
  71      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
  72      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  73    { .name = "CPUACTLR",
  74      .cp = 15, .opc1 = 0, .crm = 15,
  75      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  76    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
  77      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
  78      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  79    { .name = "CPUECTLR",
  80      .cp = 15, .opc1 = 1, .crm = 15,
  81      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  82    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
  83      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
  84      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  85    { .name = "CPUMERRSR",
  86      .cp = 15, .opc1 = 2, .crm = 15,
  87      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  88    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
  89      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
  90      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  91    { .name = "L2MERRSR",
  92      .cp = 15, .opc1 = 3, .crm = 15,
  93      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  94    REGINFO_SENTINEL
  95};
  96
  97static void aarch64_a57_initfn(Object *obj)
  98{
  99    ARMCPU *cpu = ARM_CPU(obj);
 100
 101    cpu->dtb_compatible = "arm,cortex-a57";
 102    set_feature(&cpu->env, ARM_FEATURE_V8);
 103    set_feature(&cpu->env, ARM_FEATURE_VFP4);
 104    set_feature(&cpu->env, ARM_FEATURE_NEON);
 105    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 106    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 107    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 108    set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 109    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 110    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 111    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 112    set_feature(&cpu->env, ARM_FEATURE_CRC);
 113    set_feature(&cpu->env, ARM_FEATURE_EL3);
 114    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 115    cpu->midr = 0x411fd070;
 116    cpu->revidr = 0x00000000;
 117    cpu->reset_fpsid = 0x41034070;
 118    cpu->mvfr0 = 0x10110222;
 119    cpu->mvfr1 = 0x12111111;
 120    cpu->mvfr2 = 0x00000043;
 121    cpu->ctr = 0x8444c004;
 122    cpu->reset_sctlr = 0x00c50838;
 123    cpu->id_pfr0 = 0x00000131;
 124    cpu->id_pfr1 = 0x00011011;
 125    cpu->id_dfr0 = 0x03010066;
 126    cpu->id_afr0 = 0x00000000;
 127    cpu->id_mmfr0 = 0x10101105;
 128    cpu->id_mmfr1 = 0x40000000;
 129    cpu->id_mmfr2 = 0x01260000;
 130    cpu->id_mmfr3 = 0x02102211;
 131    cpu->id_isar0 = 0x02101110;
 132    cpu->id_isar1 = 0x13112111;
 133    cpu->id_isar2 = 0x21232042;
 134    cpu->id_isar3 = 0x01112131;
 135    cpu->id_isar4 = 0x00011142;
 136    cpu->id_isar5 = 0x00011121;
 137    cpu->id_aa64pfr0 = 0x00002222;
 138    cpu->id_aa64dfr0 = 0x10305106;
 139    cpu->pmceid0 = 0x00000000;
 140    cpu->pmceid1 = 0x00000000;
 141    cpu->id_aa64isar0 = 0x00011120;
 142    cpu->id_aa64mmfr0 = 0x00001124;
 143    cpu->dbgdidr = 0x3516d000;
 144    cpu->clidr = 0x0a200023;
 145    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 146    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 147    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 148    cpu->dcz_blocksize = 4; /* 64 bytes */
 149    define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 150}
 151
 152static void aarch64_a53_initfn(Object *obj)
 153{
 154    ARMCPU *cpu = ARM_CPU(obj);
 155
 156    cpu->dtb_compatible = "arm,cortex-a53";
 157    set_feature(&cpu->env, ARM_FEATURE_V8);
 158    set_feature(&cpu->env, ARM_FEATURE_VFP4);
 159    set_feature(&cpu->env, ARM_FEATURE_NEON);
 160    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 161    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 162    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 163    set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 164    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 165    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 166    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 167    set_feature(&cpu->env, ARM_FEATURE_CRC);
 168    set_feature(&cpu->env, ARM_FEATURE_EL3);
 169    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 170    cpu->midr = 0x410fd034;
 171    cpu->revidr = 0x00000000;
 172    cpu->reset_fpsid = 0x41034070;
 173    cpu->mvfr0 = 0x10110222;
 174    cpu->mvfr1 = 0x12111111;
 175    cpu->mvfr2 = 0x00000043;
 176    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 177    cpu->reset_sctlr = 0x00c50838;
 178    cpu->id_pfr0 = 0x00000131;
 179    cpu->id_pfr1 = 0x00011011;
 180    cpu->id_dfr0 = 0x03010066;
 181    cpu->id_afr0 = 0x00000000;
 182    cpu->id_mmfr0 = 0x10101105;
 183    cpu->id_mmfr1 = 0x40000000;
 184    cpu->id_mmfr2 = 0x01260000;
 185    cpu->id_mmfr3 = 0x02102211;
 186    cpu->id_isar0 = 0x02101110;
 187    cpu->id_isar1 = 0x13112111;
 188    cpu->id_isar2 = 0x21232042;
 189    cpu->id_isar3 = 0x01112131;
 190    cpu->id_isar4 = 0x00011142;
 191    cpu->id_isar5 = 0x00011121;
 192    cpu->id_aa64pfr0 = 0x00002222;
 193    cpu->id_aa64dfr0 = 0x10305106;
 194    cpu->id_aa64isar0 = 0x00011120;
 195    cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 196    cpu->dbgdidr = 0x3516d000;
 197    cpu->clidr = 0x0a200023;
 198    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 199    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 200    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 201    cpu->dcz_blocksize = 4; /* 64 bytes */
 202    define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 203}
 204
 205#ifdef CONFIG_USER_ONLY
 206static void aarch64_any_initfn(Object *obj)
 207{
 208    ARMCPU *cpu = ARM_CPU(obj);
 209
 210    set_feature(&cpu->env, ARM_FEATURE_V8);
 211    set_feature(&cpu->env, ARM_FEATURE_VFP4);
 212    set_feature(&cpu->env, ARM_FEATURE_NEON);
 213    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 214    set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 215    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 216    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 217    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 218    set_feature(&cpu->env, ARM_FEATURE_CRC);
 219    cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
 220    cpu->dcz_blocksize = 7; /*  512 bytes */
 221}
 222#endif
 223
 224typedef struct ARMCPUInfo {
 225    const char *name;
 226    void (*initfn)(Object *obj);
 227    void (*class_init)(ObjectClass *oc, void *data);
 228} ARMCPUInfo;
 229
 230static const ARMCPUInfo aarch64_cpus[] = {
 231    { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
 232    { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
 233#ifdef CONFIG_USER_ONLY
 234    { .name = "any",         .initfn = aarch64_any_initfn },
 235#endif
 236    { .name = NULL }
 237};
 238
 239static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
 240{
 241    ARMCPU *cpu = ARM_CPU(obj);
 242
 243    return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
 244}
 245
 246static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
 247{
 248    ARMCPU *cpu = ARM_CPU(obj);
 249
 250    /* At this time, this property is only allowed if KVM is enabled.  This
 251     * restriction allows us to avoid fixing up functionality that assumes a
 252     * uniform execution state like do_interrupt.
 253     */
 254    if (!kvm_enabled()) {
 255        error_setg(errp, "'aarch64' feature cannot be disabled "
 256                         "unless KVM is enabled");
 257        return;
 258    }
 259
 260    if (value == false) {
 261        unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
 262    } else {
 263        set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 264    }
 265}
 266
 267static void aarch64_cpu_initfn(Object *obj)
 268{
 269    object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
 270                             aarch64_cpu_set_aarch64, NULL);
 271    object_property_set_description(obj, "aarch64",
 272                                    "Set on/off to enable/disable aarch64 "
 273                                    "execution state ",
 274                                    NULL);
 275}
 276
 277static void aarch64_cpu_finalizefn(Object *obj)
 278{
 279}
 280
 281static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
 282{
 283    ARMCPU *cpu = ARM_CPU(cs);
 284    /* It's OK to look at env for the current mode here, because it's
 285     * never possible for an AArch64 TB to chain to an AArch32 TB.
 286     * (Otherwise we would need to use synchronize_from_tb instead.)
 287     */
 288    if (is_a64(&cpu->env)) {
 289        cpu->env.pc = value;
 290    } else {
 291        cpu->env.regs[15] = value;
 292    }
 293}
 294
 295static gchar *aarch64_gdb_arch_name(CPUState *cs)
 296{
 297    return g_strdup("aarch64");
 298}
 299
 300static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
 301{
 302    CPUClass *cc = CPU_CLASS(oc);
 303
 304    cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
 305    cc->set_pc = aarch64_cpu_set_pc;
 306    cc->gdb_read_register = aarch64_cpu_gdb_read_register;
 307    cc->gdb_write_register = aarch64_cpu_gdb_write_register;
 308    cc->gdb_num_core_regs = 34;
 309    cc->gdb_core_xml_file = "aarch64-core.xml";
 310    cc->gdb_arch_name = aarch64_gdb_arch_name;
 311}
 312
 313static void aarch64_cpu_register(const ARMCPUInfo *info)
 314{
 315    TypeInfo type_info = {
 316        .parent = TYPE_AARCH64_CPU,
 317        .instance_size = sizeof(ARMCPU),
 318        .instance_init = info->initfn,
 319        .class_size = sizeof(ARMCPUClass),
 320        .class_init = info->class_init,
 321    };
 322
 323    type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 324    type_register(&type_info);
 325    g_free((void *)type_info.name);
 326}
 327
 328static const TypeInfo aarch64_cpu_type_info = {
 329    .name = TYPE_AARCH64_CPU,
 330    .parent = TYPE_ARM_CPU,
 331    .instance_size = sizeof(ARMCPU),
 332    .instance_init = aarch64_cpu_initfn,
 333    .instance_finalize = aarch64_cpu_finalizefn,
 334    .abstract = true,
 335    .class_size = sizeof(AArch64CPUClass),
 336    .class_init = aarch64_cpu_class_init,
 337};
 338
 339static void aarch64_cpu_register_types(void)
 340{
 341    const ARMCPUInfo *info = aarch64_cpus;
 342
 343    type_register_static(&aarch64_cpu_type_info);
 344
 345    while (info->name) {
 346        aarch64_cpu_register(info);
 347        info++;
 348    }
 349}
 350
 351type_init(aarch64_cpu_register_types)
 352