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20#ifndef I386_CPU_H
21#define I386_CPU_H
22
23#include "qemu-common.h"
24#include "cpu-qom.h"
25#include "standard-headers/asm-x86/hyperv.h"
26
27#ifdef TARGET_X86_64
28#define TARGET_LONG_BITS 64
29#else
30#define TARGET_LONG_BITS 32
31#endif
32
33
34#define TARGET_MAX_INSN_SIZE 16
35
36
37
38#define TARGET_HAS_PRECISE_SMC
39
40#ifdef TARGET_X86_64
41#define I386_ELF_MACHINE EM_X86_64
42#define ELF_MACHINE_UNAME "x86_64"
43#else
44#define I386_ELF_MACHINE EM_386
45#define ELF_MACHINE_UNAME "i686"
46#endif
47
48#define CPUArchState struct CPUX86State
49
50#include "exec/cpu-defs.h"
51
52#include "fpu/softfloat.h"
53
54#define R_EAX 0
55#define R_ECX 1
56#define R_EDX 2
57#define R_EBX 3
58#define R_ESP 4
59#define R_EBP 5
60#define R_ESI 6
61#define R_EDI 7
62
63#define R_AL 0
64#define R_CL 1
65#define R_DL 2
66#define R_BL 3
67#define R_AH 4
68#define R_CH 5
69#define R_DH 6
70#define R_BH 7
71
72#define R_ES 0
73#define R_CS 1
74#define R_SS 2
75#define R_DS 3
76#define R_FS 4
77#define R_GS 5
78
79
80#define DESC_G_MASK (1 << 23)
81#define DESC_B_SHIFT 22
82#define DESC_B_MASK (1 << DESC_B_SHIFT)
83#define DESC_L_SHIFT 21
84#define DESC_L_MASK (1 << DESC_L_SHIFT)
85#define DESC_AVL_MASK (1 << 20)
86#define DESC_P_MASK (1 << 15)
87#define DESC_DPL_SHIFT 13
88#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
89#define DESC_S_MASK (1 << 12)
90#define DESC_TYPE_SHIFT 8
91#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
92#define DESC_A_MASK (1 << 8)
93
94#define DESC_CS_MASK (1 << 11)
95#define DESC_C_MASK (1 << 10)
96#define DESC_R_MASK (1 << 9)
97
98#define DESC_E_MASK (1 << 10)
99#define DESC_W_MASK (1 << 9)
100
101#define DESC_TSS_BUSY_MASK (1 << 9)
102
103
104#define CC_C 0x0001
105#define CC_P 0x0004
106#define CC_A 0x0010
107#define CC_Z 0x0040
108#define CC_S 0x0080
109#define CC_O 0x0800
110
111#define TF_SHIFT 8
112#define IOPL_SHIFT 12
113#define VM_SHIFT 17
114
115#define TF_MASK 0x00000100
116#define IF_MASK 0x00000200
117#define DF_MASK 0x00000400
118#define IOPL_MASK 0x00003000
119#define NT_MASK 0x00004000
120#define RF_MASK 0x00010000
121#define VM_MASK 0x00020000
122#define AC_MASK 0x00040000
123#define VIF_MASK 0x00080000
124#define VIP_MASK 0x00100000
125#define ID_MASK 0x00200000
126
127
128
129
130
131
132#define HF_CPL_SHIFT 0
133
134#define HF_INHIBIT_IRQ_SHIFT 3
135
136#define HF_CS32_SHIFT 4
137#define HF_SS32_SHIFT 5
138
139#define HF_ADDSEG_SHIFT 6
140
141#define HF_PE_SHIFT 7
142#define HF_TF_SHIFT 8
143#define HF_MP_SHIFT 9
144#define HF_EM_SHIFT 10
145#define HF_TS_SHIFT 11
146#define HF_IOPL_SHIFT 12
147#define HF_LMA_SHIFT 14
148#define HF_CS64_SHIFT 15
149#define HF_RF_SHIFT 16
150#define HF_VM_SHIFT 17
151#define HF_AC_SHIFT 18
152#define HF_SMM_SHIFT 19
153#define HF_SVME_SHIFT 20
154#define HF_SVMI_SHIFT 21
155#define HF_OSFXSR_SHIFT 22
156#define HF_SMAP_SHIFT 23
157#define HF_IOBPT_SHIFT 24
158#define HF_MPX_EN_SHIFT 25
159#define HF_MPX_IU_SHIFT 26
160
161#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
162#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
163#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
164#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
165#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
166#define HF_PE_MASK (1 << HF_PE_SHIFT)
167#define HF_TF_MASK (1 << HF_TF_SHIFT)
168#define HF_MP_MASK (1 << HF_MP_SHIFT)
169#define HF_EM_MASK (1 << HF_EM_SHIFT)
170#define HF_TS_MASK (1 << HF_TS_SHIFT)
171#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
172#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
173#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
174#define HF_RF_MASK (1 << HF_RF_SHIFT)
175#define HF_VM_MASK (1 << HF_VM_SHIFT)
176#define HF_AC_MASK (1 << HF_AC_SHIFT)
177#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
178#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
179#define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
180#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
181#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
182#define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
183#define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
184#define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
185
186
187
188#define HF2_GIF_SHIFT 0
189#define HF2_HIF_SHIFT 1
190#define HF2_NMI_SHIFT 2
191#define HF2_VINTR_SHIFT 3
192#define HF2_SMM_INSIDE_NMI_SHIFT 4
193#define HF2_MPX_PR_SHIFT 5
194
195#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
196#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
197#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
198#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
199#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
200#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
201
202#define CR0_PE_SHIFT 0
203#define CR0_MP_SHIFT 1
204
205#define CR0_PE_MASK (1U << 0)
206#define CR0_MP_MASK (1U << 1)
207#define CR0_EM_MASK (1U << 2)
208#define CR0_TS_MASK (1U << 3)
209#define CR0_ET_MASK (1U << 4)
210#define CR0_NE_MASK (1U << 5)
211#define CR0_WP_MASK (1U << 16)
212#define CR0_AM_MASK (1U << 18)
213#define CR0_PG_MASK (1U << 31)
214
215#define CR4_VME_MASK (1U << 0)
216#define CR4_PVI_MASK (1U << 1)
217#define CR4_TSD_MASK (1U << 2)
218#define CR4_DE_MASK (1U << 3)
219#define CR4_PSE_MASK (1U << 4)
220#define CR4_PAE_MASK (1U << 5)
221#define CR4_MCE_MASK (1U << 6)
222#define CR4_PGE_MASK (1U << 7)
223#define CR4_PCE_MASK (1U << 8)
224#define CR4_OSFXSR_SHIFT 9
225#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
226#define CR4_OSXMMEXCPT_MASK (1U << 10)
227#define CR4_VMXE_MASK (1U << 13)
228#define CR4_SMXE_MASK (1U << 14)
229#define CR4_FSGSBASE_MASK (1U << 16)
230#define CR4_PCIDE_MASK (1U << 17)
231#define CR4_OSXSAVE_MASK (1U << 18)
232#define CR4_SMEP_MASK (1U << 20)
233#define CR4_SMAP_MASK (1U << 21)
234#define CR4_PKE_MASK (1U << 22)
235
236#define DR6_BD (1 << 13)
237#define DR6_BS (1 << 14)
238#define DR6_BT (1 << 15)
239#define DR6_FIXED_1 0xffff0ff0
240
241#define DR7_GD (1 << 13)
242#define DR7_TYPE_SHIFT 16
243#define DR7_LEN_SHIFT 18
244#define DR7_FIXED_1 0x00000400
245#define DR7_GLOBAL_BP_MASK 0xaa
246#define DR7_LOCAL_BP_MASK 0x55
247#define DR7_MAX_BP 4
248#define DR7_TYPE_BP_INST 0x0
249#define DR7_TYPE_DATA_WR 0x1
250#define DR7_TYPE_IO_RW 0x2
251#define DR7_TYPE_DATA_RW 0x3
252
253#define PG_PRESENT_BIT 0
254#define PG_RW_BIT 1
255#define PG_USER_BIT 2
256#define PG_PWT_BIT 3
257#define PG_PCD_BIT 4
258#define PG_ACCESSED_BIT 5
259#define PG_DIRTY_BIT 6
260#define PG_PSE_BIT 7
261#define PG_GLOBAL_BIT 8
262#define PG_PSE_PAT_BIT 12
263#define PG_PKRU_BIT 59
264#define PG_NX_BIT 63
265
266#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
267#define PG_RW_MASK (1 << PG_RW_BIT)
268#define PG_USER_MASK (1 << PG_USER_BIT)
269#define PG_PWT_MASK (1 << PG_PWT_BIT)
270#define PG_PCD_MASK (1 << PG_PCD_BIT)
271#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
272#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
273#define PG_PSE_MASK (1 << PG_PSE_BIT)
274#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
275#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
276#define PG_ADDRESS_MASK 0x000ffffffffff000LL
277#define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
278#define PG_HI_USER_MASK 0x7ff0000000000000LL
279#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
280#define PG_NX_MASK (1ULL << PG_NX_BIT)
281
282#define PG_ERROR_W_BIT 1
283
284#define PG_ERROR_P_MASK 0x01
285#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
286#define PG_ERROR_U_MASK 0x04
287#define PG_ERROR_RSVD_MASK 0x08
288#define PG_ERROR_I_D_MASK 0x10
289#define PG_ERROR_PK_MASK 0x20
290
291#define MCG_CTL_P (1ULL<<8)
292#define MCG_SER_P (1ULL<<24)
293#define MCG_LMCE_P (1ULL<<27)
294
295#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
296#define MCE_BANKS_DEF 10
297
298#define MCG_CAP_BANKS_MASK 0xff
299
300#define MCG_STATUS_RIPV (1ULL<<0)
301#define MCG_STATUS_EIPV (1ULL<<1)
302#define MCG_STATUS_MCIP (1ULL<<2)
303#define MCG_STATUS_LMCE (1ULL<<3)
304
305#define MCG_EXT_CTL_LMCE_EN (1ULL<<0)
306
307#define MCI_STATUS_VAL (1ULL<<63)
308#define MCI_STATUS_OVER (1ULL<<62)
309#define MCI_STATUS_UC (1ULL<<61)
310#define MCI_STATUS_EN (1ULL<<60)
311#define MCI_STATUS_MISCV (1ULL<<59)
312#define MCI_STATUS_ADDRV (1ULL<<58)
313#define MCI_STATUS_PCC (1ULL<<57)
314#define MCI_STATUS_S (1ULL<<56)
315#define MCI_STATUS_AR (1ULL<<55)
316
317
318#define MCM_ADDR_SEGOFF 0
319#define MCM_ADDR_LINEAR 1
320#define MCM_ADDR_PHYS 2
321#define MCM_ADDR_MEM 3
322#define MCM_ADDR_GENERIC 7
323
324#define MSR_IA32_TSC 0x10
325#define MSR_IA32_APICBASE 0x1b
326#define MSR_IA32_APICBASE_BSP (1<<8)
327#define MSR_IA32_APICBASE_ENABLE (1<<11)
328#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
329#define MSR_IA32_FEATURE_CONTROL 0x0000003a
330#define MSR_TSC_ADJUST 0x0000003b
331#define MSR_IA32_TSCDEADLINE 0x6e0
332
333#define FEATURE_CONTROL_LOCKED (1<<0)
334#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
335#define FEATURE_CONTROL_LMCE (1<<20)
336
337#define MSR_P6_PERFCTR0 0xc1
338
339#define MSR_IA32_SMBASE 0x9e
340#define MSR_MTRRcap 0xfe
341#define MSR_MTRRcap_VCNT 8
342#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
343#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
344
345#define MSR_IA32_SYSENTER_CS 0x174
346#define MSR_IA32_SYSENTER_ESP 0x175
347#define MSR_IA32_SYSENTER_EIP 0x176
348
349#define MSR_MCG_CAP 0x179
350#define MSR_MCG_STATUS 0x17a
351#define MSR_MCG_CTL 0x17b
352#define MSR_MCG_EXT_CTL 0x4d0
353
354#define MSR_P6_EVNTSEL0 0x186
355
356#define MSR_IA32_PERF_STATUS 0x198
357
358#define MSR_IA32_MISC_ENABLE 0x1a0
359
360#define MSR_IA32_MISC_ENABLE_DEFAULT 1
361
362#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
363#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
364
365#define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
366
367#define MSR_MTRRfix64K_00000 0x250
368#define MSR_MTRRfix16K_80000 0x258
369#define MSR_MTRRfix16K_A0000 0x259
370#define MSR_MTRRfix4K_C0000 0x268
371#define MSR_MTRRfix4K_C8000 0x269
372#define MSR_MTRRfix4K_D0000 0x26a
373#define MSR_MTRRfix4K_D8000 0x26b
374#define MSR_MTRRfix4K_E0000 0x26c
375#define MSR_MTRRfix4K_E8000 0x26d
376#define MSR_MTRRfix4K_F0000 0x26e
377#define MSR_MTRRfix4K_F8000 0x26f
378
379#define MSR_PAT 0x277
380
381#define MSR_MTRRdefType 0x2ff
382
383#define MSR_CORE_PERF_FIXED_CTR0 0x309
384#define MSR_CORE_PERF_FIXED_CTR1 0x30a
385#define MSR_CORE_PERF_FIXED_CTR2 0x30b
386#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
387#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
388#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
389#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
390
391#define MSR_MC0_CTL 0x400
392#define MSR_MC0_STATUS 0x401
393#define MSR_MC0_ADDR 0x402
394#define MSR_MC0_MISC 0x403
395
396#define MSR_EFER 0xc0000080
397
398#define MSR_EFER_SCE (1 << 0)
399#define MSR_EFER_LME (1 << 8)
400#define MSR_EFER_LMA (1 << 10)
401#define MSR_EFER_NXE (1 << 11)
402#define MSR_EFER_SVME (1 << 12)
403#define MSR_EFER_FFXSR (1 << 14)
404
405#define MSR_STAR 0xc0000081
406#define MSR_LSTAR 0xc0000082
407#define MSR_CSTAR 0xc0000083
408#define MSR_FMASK 0xc0000084
409#define MSR_FSBASE 0xc0000100
410#define MSR_GSBASE 0xc0000101
411#define MSR_KERNELGSBASE 0xc0000102
412#define MSR_TSC_AUX 0xc0000103
413
414#define MSR_VM_HSAVE_PA 0xc0010117
415
416#define MSR_IA32_BNDCFGS 0x00000d90
417#define MSR_IA32_XSS 0x00000da0
418
419#define XSTATE_FP_BIT 0
420#define XSTATE_SSE_BIT 1
421#define XSTATE_YMM_BIT 2
422#define XSTATE_BNDREGS_BIT 3
423#define XSTATE_BNDCSR_BIT 4
424#define XSTATE_OPMASK_BIT 5
425#define XSTATE_ZMM_Hi256_BIT 6
426#define XSTATE_Hi16_ZMM_BIT 7
427#define XSTATE_PKRU_BIT 9
428
429#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
430#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
431#define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
432#define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
433#define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
434#define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
435#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
436#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
437#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
438
439
440typedef enum FeatureWord {
441 FEAT_1_EDX,
442 FEAT_1_ECX,
443 FEAT_7_0_EBX,
444 FEAT_7_0_ECX,
445 FEAT_8000_0001_EDX,
446 FEAT_8000_0001_ECX,
447 FEAT_8000_0007_EDX,
448 FEAT_C000_0001_EDX,
449 FEAT_KVM,
450 FEAT_HYPERV_EAX,
451 FEAT_HYPERV_EBX,
452 FEAT_HYPERV_EDX,
453 FEAT_SVM,
454 FEAT_XSAVE,
455 FEAT_6_EAX,
456 FEATURE_WORDS,
457} FeatureWord;
458
459typedef uint32_t FeatureWordArray[FEATURE_WORDS];
460
461
462#define CPUID_FP87 (1U << 0)
463#define CPUID_VME (1U << 1)
464#define CPUID_DE (1U << 2)
465#define CPUID_PSE (1U << 3)
466#define CPUID_TSC (1U << 4)
467#define CPUID_MSR (1U << 5)
468#define CPUID_PAE (1U << 6)
469#define CPUID_MCE (1U << 7)
470#define CPUID_CX8 (1U << 8)
471#define CPUID_APIC (1U << 9)
472#define CPUID_SEP (1U << 11)
473#define CPUID_MTRR (1U << 12)
474#define CPUID_PGE (1U << 13)
475#define CPUID_MCA (1U << 14)
476#define CPUID_CMOV (1U << 15)
477#define CPUID_PAT (1U << 16)
478#define CPUID_PSE36 (1U << 17)
479#define CPUID_PN (1U << 18)
480#define CPUID_CLFLUSH (1U << 19)
481#define CPUID_DTS (1U << 21)
482#define CPUID_ACPI (1U << 22)
483#define CPUID_MMX (1U << 23)
484#define CPUID_FXSR (1U << 24)
485#define CPUID_SSE (1U << 25)
486#define CPUID_SSE2 (1U << 26)
487#define CPUID_SS (1U << 27)
488#define CPUID_HT (1U << 28)
489#define CPUID_TM (1U << 29)
490#define CPUID_IA64 (1U << 30)
491#define CPUID_PBE (1U << 31)
492
493#define CPUID_EXT_SSE3 (1U << 0)
494#define CPUID_EXT_PCLMULQDQ (1U << 1)
495#define CPUID_EXT_DTES64 (1U << 2)
496#define CPUID_EXT_MONITOR (1U << 3)
497#define CPUID_EXT_DSCPL (1U << 4)
498#define CPUID_EXT_VMX (1U << 5)
499#define CPUID_EXT_SMX (1U << 6)
500#define CPUID_EXT_EST (1U << 7)
501#define CPUID_EXT_TM2 (1U << 8)
502#define CPUID_EXT_SSSE3 (1U << 9)
503#define CPUID_EXT_CID (1U << 10)
504#define CPUID_EXT_FMA (1U << 12)
505#define CPUID_EXT_CX16 (1U << 13)
506#define CPUID_EXT_XTPR (1U << 14)
507#define CPUID_EXT_PDCM (1U << 15)
508#define CPUID_EXT_PCID (1U << 17)
509#define CPUID_EXT_DCA (1U << 18)
510#define CPUID_EXT_SSE41 (1U << 19)
511#define CPUID_EXT_SSE42 (1U << 20)
512#define CPUID_EXT_X2APIC (1U << 21)
513#define CPUID_EXT_MOVBE (1U << 22)
514#define CPUID_EXT_POPCNT (1U << 23)
515#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
516#define CPUID_EXT_AES (1U << 25)
517#define CPUID_EXT_XSAVE (1U << 26)
518#define CPUID_EXT_OSXSAVE (1U << 27)
519#define CPUID_EXT_AVX (1U << 28)
520#define CPUID_EXT_F16C (1U << 29)
521#define CPUID_EXT_RDRAND (1U << 30)
522#define CPUID_EXT_HYPERVISOR (1U << 31)
523
524#define CPUID_EXT2_FPU (1U << 0)
525#define CPUID_EXT2_VME (1U << 1)
526#define CPUID_EXT2_DE (1U << 2)
527#define CPUID_EXT2_PSE (1U << 3)
528#define CPUID_EXT2_TSC (1U << 4)
529#define CPUID_EXT2_MSR (1U << 5)
530#define CPUID_EXT2_PAE (1U << 6)
531#define CPUID_EXT2_MCE (1U << 7)
532#define CPUID_EXT2_CX8 (1U << 8)
533#define CPUID_EXT2_APIC (1U << 9)
534#define CPUID_EXT2_SYSCALL (1U << 11)
535#define CPUID_EXT2_MTRR (1U << 12)
536#define CPUID_EXT2_PGE (1U << 13)
537#define CPUID_EXT2_MCA (1U << 14)
538#define CPUID_EXT2_CMOV (1U << 15)
539#define CPUID_EXT2_PAT (1U << 16)
540#define CPUID_EXT2_PSE36 (1U << 17)
541#define CPUID_EXT2_MP (1U << 19)
542#define CPUID_EXT2_NX (1U << 20)
543#define CPUID_EXT2_MMXEXT (1U << 22)
544#define CPUID_EXT2_MMX (1U << 23)
545#define CPUID_EXT2_FXSR (1U << 24)
546#define CPUID_EXT2_FFXSR (1U << 25)
547#define CPUID_EXT2_PDPE1GB (1U << 26)
548#define CPUID_EXT2_RDTSCP (1U << 27)
549#define CPUID_EXT2_LM (1U << 29)
550#define CPUID_EXT2_3DNOWEXT (1U << 30)
551#define CPUID_EXT2_3DNOW (1U << 31)
552
553
554#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
555 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
556 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
557 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
558 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
559 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
560 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
561 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
562 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
563
564#define CPUID_EXT3_LAHF_LM (1U << 0)
565#define CPUID_EXT3_CMP_LEG (1U << 1)
566#define CPUID_EXT3_SVM (1U << 2)
567#define CPUID_EXT3_EXTAPIC (1U << 3)
568#define CPUID_EXT3_CR8LEG (1U << 4)
569#define CPUID_EXT3_ABM (1U << 5)
570#define CPUID_EXT3_SSE4A (1U << 6)
571#define CPUID_EXT3_MISALIGNSSE (1U << 7)
572#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
573#define CPUID_EXT3_OSVW (1U << 9)
574#define CPUID_EXT3_IBS (1U << 10)
575#define CPUID_EXT3_XOP (1U << 11)
576#define CPUID_EXT3_SKINIT (1U << 12)
577#define CPUID_EXT3_WDT (1U << 13)
578#define CPUID_EXT3_LWP (1U << 15)
579#define CPUID_EXT3_FMA4 (1U << 16)
580#define CPUID_EXT3_TCE (1U << 17)
581#define CPUID_EXT3_NODEID (1U << 19)
582#define CPUID_EXT3_TBM (1U << 21)
583#define CPUID_EXT3_TOPOEXT (1U << 22)
584#define CPUID_EXT3_PERFCORE (1U << 23)
585#define CPUID_EXT3_PERFNB (1U << 24)
586
587#define CPUID_SVM_NPT (1U << 0)
588#define CPUID_SVM_LBRV (1U << 1)
589#define CPUID_SVM_SVMLOCK (1U << 2)
590#define CPUID_SVM_NRIPSAVE (1U << 3)
591#define CPUID_SVM_TSCSCALE (1U << 4)
592#define CPUID_SVM_VMCBCLEAN (1U << 5)
593#define CPUID_SVM_FLUSHASID (1U << 6)
594#define CPUID_SVM_DECODEASSIST (1U << 7)
595#define CPUID_SVM_PAUSEFILTER (1U << 10)
596#define CPUID_SVM_PFTHRESHOLD (1U << 12)
597
598#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
599#define CPUID_7_0_EBX_BMI1 (1U << 3)
600#define CPUID_7_0_EBX_HLE (1U << 4)
601#define CPUID_7_0_EBX_AVX2 (1U << 5)
602#define CPUID_7_0_EBX_SMEP (1U << 7)
603#define CPUID_7_0_EBX_BMI2 (1U << 8)
604#define CPUID_7_0_EBX_ERMS (1U << 9)
605#define CPUID_7_0_EBX_INVPCID (1U << 10)
606#define CPUID_7_0_EBX_RTM (1U << 11)
607#define CPUID_7_0_EBX_MPX (1U << 14)
608#define CPUID_7_0_EBX_AVX512F (1U << 16)
609#define CPUID_7_0_EBX_RDSEED (1U << 18)
610#define CPUID_7_0_EBX_ADX (1U << 19)
611#define CPUID_7_0_EBX_SMAP (1U << 20)
612#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
613#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
614#define CPUID_7_0_EBX_CLWB (1U << 24)
615#define CPUID_7_0_EBX_AVX512PF (1U << 26)
616#define CPUID_7_0_EBX_AVX512ER (1U << 27)
617#define CPUID_7_0_EBX_AVX512CD (1U << 28)
618
619#define CPUID_7_0_ECX_UMIP (1U << 2)
620#define CPUID_7_0_ECX_PKU (1U << 3)
621#define CPUID_7_0_ECX_OSPKE (1U << 4)
622#define CPUID_7_0_ECX_RDPID (1U << 22)
623
624#define CPUID_XSAVE_XSAVEOPT (1U << 0)
625#define CPUID_XSAVE_XSAVEC (1U << 1)
626#define CPUID_XSAVE_XGETBV1 (1U << 2)
627#define CPUID_XSAVE_XSAVES (1U << 3)
628
629#define CPUID_6_EAX_ARAT (1U << 2)
630
631
632#define CPUID_APM_INVTSC (1U << 8)
633
634#define CPUID_VENDOR_SZ 12
635
636#define CPUID_VENDOR_INTEL_1 0x756e6547
637#define CPUID_VENDOR_INTEL_2 0x49656e69
638#define CPUID_VENDOR_INTEL_3 0x6c65746e
639#define CPUID_VENDOR_INTEL "GenuineIntel"
640
641#define CPUID_VENDOR_AMD_1 0x68747541
642#define CPUID_VENDOR_AMD_2 0x69746e65
643#define CPUID_VENDOR_AMD_3 0x444d4163
644#define CPUID_VENDOR_AMD "AuthenticAMD"
645
646#define CPUID_VENDOR_VIA "CentaurHauls"
647
648#define CPUID_MWAIT_IBE (1U << 1)
649#define CPUID_MWAIT_EMX (1U << 0)
650
651
652#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
653#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
654#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
655
656#ifndef HYPERV_SPINLOCK_NEVER_RETRY
657#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
658#endif
659
660#define EXCP00_DIVZ 0
661#define EXCP01_DB 1
662#define EXCP02_NMI 2
663#define EXCP03_INT3 3
664#define EXCP04_INTO 4
665#define EXCP05_BOUND 5
666#define EXCP06_ILLOP 6
667#define EXCP07_PREX 7
668#define EXCP08_DBLE 8
669#define EXCP09_XERR 9
670#define EXCP0A_TSS 10
671#define EXCP0B_NOSEG 11
672#define EXCP0C_STACK 12
673#define EXCP0D_GPF 13
674#define EXCP0E_PAGE 14
675#define EXCP10_COPR 16
676#define EXCP11_ALGN 17
677#define EXCP12_MCHK 18
678
679#define EXCP_SYSCALL 0x100
680
681
682
683#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
684#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
685#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
686#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
687#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
688#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
689#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
690
691
692#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
693
694typedef enum {
695 CC_OP_DYNAMIC,
696 CC_OP_EFLAGS,
697
698 CC_OP_MULB,
699 CC_OP_MULW,
700 CC_OP_MULL,
701 CC_OP_MULQ,
702
703 CC_OP_ADDB,
704 CC_OP_ADDW,
705 CC_OP_ADDL,
706 CC_OP_ADDQ,
707
708 CC_OP_ADCB,
709 CC_OP_ADCW,
710 CC_OP_ADCL,
711 CC_OP_ADCQ,
712
713 CC_OP_SUBB,
714 CC_OP_SUBW,
715 CC_OP_SUBL,
716 CC_OP_SUBQ,
717
718 CC_OP_SBBB,
719 CC_OP_SBBW,
720 CC_OP_SBBL,
721 CC_OP_SBBQ,
722
723 CC_OP_LOGICB,
724 CC_OP_LOGICW,
725 CC_OP_LOGICL,
726 CC_OP_LOGICQ,
727
728 CC_OP_INCB,
729 CC_OP_INCW,
730 CC_OP_INCL,
731 CC_OP_INCQ,
732
733 CC_OP_DECB,
734 CC_OP_DECW,
735 CC_OP_DECL,
736 CC_OP_DECQ,
737
738 CC_OP_SHLB,
739 CC_OP_SHLW,
740 CC_OP_SHLL,
741 CC_OP_SHLQ,
742
743 CC_OP_SARB,
744 CC_OP_SARW,
745 CC_OP_SARL,
746 CC_OP_SARQ,
747
748 CC_OP_BMILGB,
749 CC_OP_BMILGW,
750 CC_OP_BMILGL,
751 CC_OP_BMILGQ,
752
753 CC_OP_ADCX,
754 CC_OP_ADOX,
755 CC_OP_ADCOX,
756
757 CC_OP_CLR,
758
759 CC_OP_NB,
760} CCOp;
761
762typedef struct SegmentCache {
763 uint32_t selector;
764 target_ulong base;
765 uint32_t limit;
766 uint32_t flags;
767} SegmentCache;
768
769#define MMREG_UNION(n, bits) \
770 union n { \
771 uint8_t _b_##n[(bits)/8]; \
772 uint16_t _w_##n[(bits)/16]; \
773 uint32_t _l_##n[(bits)/32]; \
774 uint64_t _q_##n[(bits)/64]; \
775 float32 _s_##n[(bits)/32]; \
776 float64 _d_##n[(bits)/64]; \
777 }
778
779typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
780typedef MMREG_UNION(MMXReg, 64) MMXReg;
781
782typedef struct BNDReg {
783 uint64_t lb;
784 uint64_t ub;
785} BNDReg;
786
787typedef struct BNDCSReg {
788 uint64_t cfgu;
789 uint64_t sts;
790} BNDCSReg;
791
792#define BNDCFG_ENABLE 1ULL
793#define BNDCFG_BNDPRESERVE 2ULL
794#define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
795
796#ifdef HOST_WORDS_BIGENDIAN
797#define ZMM_B(n) _b_ZMMReg[63 - (n)]
798#define ZMM_W(n) _w_ZMMReg[31 - (n)]
799#define ZMM_L(n) _l_ZMMReg[15 - (n)]
800#define ZMM_S(n) _s_ZMMReg[15 - (n)]
801#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
802#define ZMM_D(n) _d_ZMMReg[7 - (n)]
803
804#define MMX_B(n) _b_MMXReg[7 - (n)]
805#define MMX_W(n) _w_MMXReg[3 - (n)]
806#define MMX_L(n) _l_MMXReg[1 - (n)]
807#define MMX_S(n) _s_MMXReg[1 - (n)]
808#else
809#define ZMM_B(n) _b_ZMMReg[n]
810#define ZMM_W(n) _w_ZMMReg[n]
811#define ZMM_L(n) _l_ZMMReg[n]
812#define ZMM_S(n) _s_ZMMReg[n]
813#define ZMM_Q(n) _q_ZMMReg[n]
814#define ZMM_D(n) _d_ZMMReg[n]
815
816#define MMX_B(n) _b_MMXReg[n]
817#define MMX_W(n) _w_MMXReg[n]
818#define MMX_L(n) _l_MMXReg[n]
819#define MMX_S(n) _s_MMXReg[n]
820#endif
821#define MMX_Q(n) _q_MMXReg[n]
822
823typedef union {
824 floatx80 d __attribute__((aligned(16)));
825 MMXReg mmx;
826} FPReg;
827
828typedef struct {
829 uint64_t base;
830 uint64_t mask;
831} MTRRVar;
832
833#define CPU_NB_REGS64 16
834#define CPU_NB_REGS32 8
835
836#ifdef TARGET_X86_64
837#define CPU_NB_REGS CPU_NB_REGS64
838#else
839#define CPU_NB_REGS CPU_NB_REGS32
840#endif
841
842#define MAX_FIXED_COUNTERS 3
843#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
844
845#define NB_MMU_MODES 3
846#define TARGET_INSN_START_EXTRA_WORDS 1
847
848#define NB_OPMASK_REGS 8
849
850
851
852
853#define UNASSIGNED_APIC_ID 0xFFFFFFFF
854
855typedef union X86LegacyXSaveArea {
856 struct {
857 uint16_t fcw;
858 uint16_t fsw;
859 uint8_t ftw;
860 uint8_t reserved;
861 uint16_t fpop;
862 uint64_t fpip;
863 uint64_t fpdp;
864 uint32_t mxcsr;
865 uint32_t mxcsr_mask;
866 FPReg fpregs[8];
867 uint8_t xmm_regs[16][16];
868 };
869 uint8_t data[512];
870} X86LegacyXSaveArea;
871
872typedef struct X86XSaveHeader {
873 uint64_t xstate_bv;
874 uint64_t xcomp_bv;
875 uint8_t reserved[48];
876} X86XSaveHeader;
877
878
879typedef struct XSaveAVX {
880 uint8_t ymmh[16][16];
881} XSaveAVX;
882
883
884typedef struct XSaveBNDREG {
885 BNDReg bnd_regs[4];
886} XSaveBNDREG;
887
888
889typedef union XSaveBNDCSR {
890 BNDCSReg bndcsr;
891 uint8_t data[64];
892} XSaveBNDCSR;
893
894
895typedef struct XSaveOpmask {
896 uint64_t opmask_regs[NB_OPMASK_REGS];
897} XSaveOpmask;
898
899
900typedef struct XSaveZMM_Hi256 {
901 uint8_t zmm_hi256[16][32];
902} XSaveZMM_Hi256;
903
904
905typedef struct XSaveHi16_ZMM {
906 uint8_t hi16_zmm[16][64];
907} XSaveHi16_ZMM;
908
909
910typedef struct XSavePKRU {
911 uint32_t pkru;
912 uint32_t padding;
913} XSavePKRU;
914
915typedef struct X86XSaveArea {
916 X86LegacyXSaveArea legacy;
917 X86XSaveHeader header;
918
919
920
921
922 XSaveAVX avx_state;
923 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
924
925 XSaveBNDREG bndreg_state;
926 XSaveBNDCSR bndcsr_state;
927
928 XSaveOpmask opmask_state;
929 XSaveZMM_Hi256 zmm_hi256_state;
930 XSaveHi16_ZMM hi16_zmm_state;
931
932 XSavePKRU pkru_state;
933} X86XSaveArea;
934
935QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
936QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
937QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
938QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
939QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
940QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
941QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
942QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
943QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
944QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
945QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
946QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
947QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
948QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
949
950typedef enum TPRAccess {
951 TPR_ACCESS_READ,
952 TPR_ACCESS_WRITE,
953} TPRAccess;
954
955typedef struct CPUX86State {
956
957 target_ulong regs[CPU_NB_REGS];
958 target_ulong eip;
959 target_ulong eflags;
960
961
962
963
964 target_ulong cc_dst;
965 target_ulong cc_src;
966 target_ulong cc_src2;
967 uint32_t cc_op;
968 int32_t df;
969 uint32_t hflags;
970
971 uint32_t hflags2;
972
973
974 SegmentCache segs[6];
975 SegmentCache ldt;
976 SegmentCache tr;
977 SegmentCache gdt;
978 SegmentCache idt;
979
980 target_ulong cr[5];
981 int32_t a20_mask;
982
983 BNDReg bnd_regs[4];
984 BNDCSReg bndcs_regs;
985 uint64_t msr_bndcfgs;
986 uint64_t efer;
987
988
989 struct {} start_init_save;
990
991
992 unsigned int fpstt;
993 uint16_t fpus;
994 uint16_t fpuc;
995 uint8_t fptags[8];
996 FPReg fpregs[8];
997
998 uint16_t fpop;
999 uint64_t fpip;
1000 uint64_t fpdp;
1001
1002
1003 float_status fp_status;
1004 floatx80 ft0;
1005
1006 float_status mmx_status;
1007 float_status sse_status;
1008 uint32_t mxcsr;
1009 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1010 ZMMReg xmm_t0;
1011 MMXReg mmx_t0;
1012
1013 uint64_t opmask_regs[NB_OPMASK_REGS];
1014
1015
1016 uint32_t sysenter_cs;
1017 target_ulong sysenter_esp;
1018 target_ulong sysenter_eip;
1019 uint64_t star;
1020
1021 uint64_t vm_hsave;
1022
1023#ifdef TARGET_X86_64
1024 target_ulong lstar;
1025 target_ulong cstar;
1026 target_ulong fmask;
1027 target_ulong kernelgsbase;
1028#endif
1029
1030 uint64_t tsc;
1031 uint64_t tsc_adjust;
1032 uint64_t tsc_deadline;
1033
1034 uint64_t mcg_status;
1035 uint64_t msr_ia32_misc_enable;
1036 uint64_t msr_ia32_feature_control;
1037
1038 uint64_t msr_fixed_ctr_ctrl;
1039 uint64_t msr_global_ctrl;
1040 uint64_t msr_global_status;
1041 uint64_t msr_global_ovf_ctrl;
1042 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1043 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1044 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1045
1046 uint64_t pat;
1047 uint32_t smbase;
1048
1049
1050 struct {} end_init_save;
1051
1052 uint64_t system_time_msr;
1053 uint64_t wall_clock_msr;
1054 uint64_t steal_time_msr;
1055 uint64_t async_pf_en_msr;
1056 uint64_t pv_eoi_en_msr;
1057
1058 uint64_t msr_hv_hypercall;
1059 uint64_t msr_hv_guest_os_id;
1060 uint64_t msr_hv_vapic;
1061 uint64_t msr_hv_tsc;
1062 uint64_t msr_hv_crash_params[HV_X64_MSR_CRASH_PARAMS];
1063 uint64_t msr_hv_runtime;
1064 uint64_t msr_hv_synic_control;
1065 uint64_t msr_hv_synic_version;
1066 uint64_t msr_hv_synic_evt_page;
1067 uint64_t msr_hv_synic_msg_page;
1068 uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT];
1069 uint64_t msr_hv_stimer_config[HV_SYNIC_STIMER_COUNT];
1070 uint64_t msr_hv_stimer_count[HV_SYNIC_STIMER_COUNT];
1071
1072
1073 int error_code;
1074 int exception_is_int;
1075 target_ulong exception_next_eip;
1076 target_ulong dr[8];
1077 union {
1078 struct CPUBreakpoint *cpu_breakpoint[4];
1079 struct CPUWatchpoint *cpu_watchpoint[4];
1080 };
1081 int old_exception;
1082
1083 uint64_t vm_vmcb;
1084 uint64_t tsc_offset;
1085 uint64_t intercept;
1086 uint16_t intercept_cr_read;
1087 uint16_t intercept_cr_write;
1088 uint16_t intercept_dr_read;
1089 uint16_t intercept_dr_write;
1090 uint32_t intercept_exceptions;
1091 uint8_t v_tpr;
1092
1093
1094 uint8_t nmi_injected;
1095 uint8_t nmi_pending;
1096
1097 CPU_COMMON
1098
1099
1100
1101
1102 uint32_t cpuid_level;
1103 uint32_t cpuid_xlevel;
1104 uint32_t cpuid_xlevel2;
1105 uint32_t cpuid_vendor1;
1106 uint32_t cpuid_vendor2;
1107 uint32_t cpuid_vendor3;
1108 uint32_t cpuid_version;
1109 FeatureWordArray features;
1110 uint32_t cpuid_model[12];
1111
1112
1113 uint64_t mtrr_fixed[11];
1114 uint64_t mtrr_deftype;
1115 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1116
1117
1118 uint32_t mp_state;
1119 int32_t exception_injected;
1120 int32_t interrupt_injected;
1121 uint8_t soft_interrupt;
1122 uint8_t has_error_code;
1123 uint32_t sipi_vector;
1124 bool tsc_valid;
1125 int64_t tsc_khz;
1126 int64_t user_tsc_khz;
1127 void *kvm_xsave_buf;
1128
1129 uint64_t mcg_cap;
1130 uint64_t mcg_ctl;
1131 uint64_t mcg_ext_ctl;
1132 uint64_t mce_banks[MCE_BANKS_DEF*4];
1133
1134 uint64_t tsc_aux;
1135
1136
1137 uint16_t fpus_vmstate;
1138 uint16_t fptag_vmstate;
1139 uint16_t fpregs_format_vmstate;
1140 uint64_t xstate_bv;
1141
1142 uint64_t xcr0;
1143 uint64_t xss;
1144
1145 uint32_t pkru;
1146
1147 TPRAccess tpr_access_type;
1148} CPUX86State;
1149
1150struct kvm_msrs;
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161struct X86CPU {
1162
1163 CPUState parent_obj;
1164
1165
1166 CPUX86State env;
1167
1168 bool hyperv_vapic;
1169 bool hyperv_relaxed_timing;
1170 int hyperv_spinlock_attempts;
1171 char *hyperv_vendor_id;
1172 bool hyperv_time;
1173 bool hyperv_crash;
1174 bool hyperv_reset;
1175 bool hyperv_vpindex;
1176 bool hyperv_runtime;
1177 bool hyperv_synic;
1178 bool hyperv_stimer;
1179 bool check_cpuid;
1180 bool enforce_cpuid;
1181 bool expose_kvm;
1182 bool migratable;
1183 bool host_features;
1184 uint32_t apic_id;
1185
1186
1187 bool cache_info_passthrough;
1188
1189
1190 uint32_t filtered_features[FEATURE_WORDS];
1191
1192
1193
1194
1195
1196
1197 bool enable_pmu;
1198
1199
1200
1201
1202
1203 bool enable_lmce;
1204
1205
1206 bool enable_cpuid_0xb;
1207
1208
1209 bool fill_mtrr_mask;
1210
1211
1212 bool host_phys_bits;
1213
1214
1215 uint32_t phys_bits;
1216
1217
1218
1219 struct DeviceState *apic_state;
1220 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1221 Notifier machine_done;
1222
1223 struct kvm_msrs *kvm_msr_buf;
1224
1225 int32_t socket_id;
1226 int32_t core_id;
1227 int32_t thread_id;
1228};
1229
1230static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
1231{
1232 return container_of(env, X86CPU, env);
1233}
1234
1235#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
1236
1237#define ENV_OFFSET offsetof(X86CPU, env)
1238
1239#ifndef CONFIG_USER_ONLY
1240extern struct VMStateDescription vmstate_x86_cpu;
1241#endif
1242
1243
1244
1245
1246
1247void x86_cpu_do_interrupt(CPUState *cpu);
1248bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1249
1250int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1251 int cpuid, void *opaque);
1252int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1253 int cpuid, void *opaque);
1254int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1255 void *opaque);
1256int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1257 void *opaque);
1258
1259void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1260 Error **errp);
1261
1262void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1263 int flags);
1264
1265hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1266
1267int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1268int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1269
1270void x86_cpu_exec_enter(CPUState *cpu);
1271void x86_cpu_exec_exit(CPUState *cpu);
1272
1273X86CPU *cpu_x86_init(const char *cpu_model);
1274void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1275int cpu_x86_support_mca_broadcast(CPUX86State *env);
1276
1277int cpu_get_pic_interrupt(CPUX86State *s);
1278
1279void cpu_set_ferr(CPUX86State *s);
1280
1281
1282
1283static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1284 int seg_reg, unsigned int selector,
1285 target_ulong base,
1286 unsigned int limit,
1287 unsigned int flags)
1288{
1289 SegmentCache *sc;
1290 unsigned int new_hflags;
1291
1292 sc = &env->segs[seg_reg];
1293 sc->selector = selector;
1294 sc->base = base;
1295 sc->limit = limit;
1296 sc->flags = flags;
1297
1298
1299 {
1300 if (seg_reg == R_CS) {
1301#ifdef TARGET_X86_64
1302 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1303
1304 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1305 env->hflags &= ~(HF_ADDSEG_MASK);
1306 } else
1307#endif
1308 {
1309
1310 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1311 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1312 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1313 new_hflags;
1314 }
1315 }
1316 if (seg_reg == R_SS) {
1317 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1318#if HF_CPL_MASK != 3
1319#error HF_CPL_MASK is hardcoded
1320#endif
1321 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1322 }
1323 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1324 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1325 if (env->hflags & HF_CS64_MASK) {
1326
1327 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1328 (env->eflags & VM_MASK) ||
1329 !(env->hflags & HF_CS32_MASK)) {
1330
1331
1332
1333
1334
1335 new_hflags |= HF_ADDSEG_MASK;
1336 } else {
1337 new_hflags |= ((env->segs[R_DS].base |
1338 env->segs[R_ES].base |
1339 env->segs[R_SS].base) != 0) <<
1340 HF_ADDSEG_SHIFT;
1341 }
1342 env->hflags = (env->hflags &
1343 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1344 }
1345}
1346
1347static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1348 uint8_t sipi_vector)
1349{
1350 CPUState *cs = CPU(cpu);
1351 CPUX86State *env = &cpu->env;
1352
1353 env->eip = 0;
1354 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1355 sipi_vector << 12,
1356 env->segs[R_CS].limit,
1357 env->segs[R_CS].flags);
1358 cs->halted = 0;
1359}
1360
1361int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1362 target_ulong *base, unsigned int *limit,
1363 unsigned int *flags);
1364
1365
1366
1367void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
1368floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
1369
1370
1371
1372
1373void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1374void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1375void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1376
1377
1378
1379
1380int cpu_x86_signal_handler(int host_signum, void *pinfo,
1381 void *puc);
1382
1383
1384typedef struct ExtSaveArea {
1385 uint32_t feature, bits;
1386 uint32_t offset, size;
1387} ExtSaveArea;
1388
1389extern const ExtSaveArea x86_ext_save_areas[];
1390
1391void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1392 uint32_t *eax, uint32_t *ebx,
1393 uint32_t *ecx, uint32_t *edx);
1394void cpu_clear_apic_feature(CPUX86State *env);
1395void host_cpuid(uint32_t function, uint32_t count,
1396 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1397
1398
1399int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr,
1400 int is_write, int mmu_idx);
1401void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1402
1403#ifndef CONFIG_USER_ONLY
1404uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1405uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1406uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1407uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1408void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1409void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1410void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1411void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1412void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1413#endif
1414
1415void breakpoint_handler(CPUState *cs);
1416
1417
1418void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1419void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1420void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1421void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1422
1423
1424uint64_t cpu_get_tsc(CPUX86State *env);
1425
1426#define TARGET_PAGE_BITS 12
1427
1428#ifdef TARGET_X86_64
1429#define TARGET_PHYS_ADDR_SPACE_BITS 52
1430
1431
1432
1433#define TARGET_VIRT_ADDR_SPACE_BITS 47
1434#else
1435#define TARGET_PHYS_ADDR_SPACE_BITS 36
1436#define TARGET_VIRT_ADDR_SPACE_BITS 32
1437#endif
1438
1439
1440
1441# if defined(TARGET_X86_64)
1442# define TCG_PHYS_ADDR_BITS 40
1443# else
1444# define TCG_PHYS_ADDR_BITS 36
1445# endif
1446
1447#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1448
1449#define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model))
1450
1451#define cpu_signal_handler cpu_x86_signal_handler
1452#define cpu_list x86_cpu_list
1453
1454
1455#define MMU_MODE0_SUFFIX _ksmap
1456#define MMU_MODE1_SUFFIX _user
1457#define MMU_MODE2_SUFFIX _knosmap
1458#define MMU_KSMAP_IDX 0
1459#define MMU_USER_IDX 1
1460#define MMU_KNOSMAP_IDX 2
1461static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1462{
1463 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1464 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1465 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1466}
1467
1468static inline int cpu_mmu_index_kernel(CPUX86State *env)
1469{
1470 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1471 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1472 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1473}
1474
1475#define CC_DST (env->cc_dst)
1476#define CC_SRC (env->cc_src)
1477#define CC_SRC2 (env->cc_src2)
1478#define CC_OP (env->cc_op)
1479
1480
1481static inline target_long lshift(target_long x, int n)
1482{
1483 if (n >= 0) {
1484 return x << n;
1485 } else {
1486 return x >> (-n);
1487 }
1488}
1489
1490
1491#define FT0 (env->ft0)
1492#define ST0 (env->fpregs[env->fpstt].d)
1493#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1494#define ST1 ST(1)
1495
1496
1497void tcg_x86_init(void);
1498
1499#include "exec/cpu-all.h"
1500#include "svm.h"
1501
1502#if !defined(CONFIG_USER_ONLY)
1503#include "hw/i386/apic.h"
1504#endif
1505
1506static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1507 target_ulong *cs_base, uint32_t *flags)
1508{
1509 *cs_base = env->segs[R_CS].base;
1510 *pc = *cs_base + env->eip;
1511 *flags = env->hflags |
1512 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1513}
1514
1515void do_cpu_init(X86CPU *cpu);
1516void do_cpu_sipi(X86CPU *cpu);
1517
1518#define MCE_INJECT_BROADCAST 1
1519#define MCE_INJECT_UNCOND_AO 2
1520
1521void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1522 uint64_t status, uint64_t mcg_status, uint64_t addr,
1523 uint64_t misc, int flags);
1524
1525
1526void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1527void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
1528 uintptr_t retaddr);
1529void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1530 int error_code);
1531void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
1532 int error_code, uintptr_t retaddr);
1533void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1534 int error_code, int next_eip_addend);
1535
1536
1537extern const uint8_t parity_table[256];
1538uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1539void update_fp_status(CPUX86State *env);
1540
1541static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1542{
1543 return env->eflags | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1544}
1545
1546
1547
1548
1549static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1550 int update_mask)
1551{
1552 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1553 CC_OP = CC_OP_EFLAGS;
1554 env->df = 1 - (2 * ((eflags >> 10) & 1));
1555 env->eflags = (env->eflags & ~update_mask) |
1556 (eflags & update_mask) | 0x2;
1557}
1558
1559
1560
1561static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1562{
1563 env->efer = val;
1564 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1565 if (env->efer & MSR_EFER_LMA) {
1566 env->hflags |= HF_LMA_MASK;
1567 }
1568 if (env->efer & MSR_EFER_SVME) {
1569 env->hflags |= HF_SVME_MASK;
1570 }
1571}
1572
1573static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
1574{
1575 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
1576}
1577
1578
1579void cpu_set_mxcsr(CPUX86State *env, uint32_t val);
1580void cpu_set_fpuc(CPUX86State *env, uint16_t val);
1581
1582
1583void helper_lock_init(void);
1584
1585
1586void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1587 uint64_t param);
1588void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
1589
1590
1591void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1592
1593
1594void do_smm_enter(X86CPU *cpu);
1595void cpu_smm_update(X86CPU *cpu);
1596
1597
1598void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1599void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
1600 TPRAccess access);
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611void x86_cpu_change_kvm_default(const char *prop, const char *value);
1612
1613
1614void cpu_sync_bndcs_hflags(CPUX86State *env);
1615
1616
1617const char *get_register_name_32(unsigned int reg);
1618
1619void enable_compat_apic_id_mode(void);
1620
1621#define APIC_DEFAULT_ADDRESS 0xfee00000
1622#define APIC_SPACE_SIZE 0x100000
1623
1624void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f,
1625 fprintf_function cpu_fprintf, int flags);
1626
1627
1628bool cpu_is_bsp(X86CPU *cpu);
1629
1630#endif
1631