LXR qemu/hw/intc/i8259

   1/*
   2 * QEMU 8259 - common bits of emulated and KVM kernel model
   3 *
   4 * Copyright (c) 2003-2004 Fabrice Bellard
   5 * Copyright (c) 2011      Jan Kiszka, Siemens AG
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a copy
   8 * of this software and associated documentation files (the "Software"), to deal
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11 * copies of the Software, and to permit persons to whom the Software is
  12 * furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in
  15 * all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23 * THE SOFTWARE.
  24 */
  25#include "qemu/osdep.h"
  26#include "hw/i386/pc.h"
  27#include "hw/isa/i8259_internal.h"
  28
  29void pic_reset_common(PICCommonState *s)
  30{
  31    s->last_irr = 0;
  32    s->irr &= s->elcr;
  33    s->imr = 0;
  34    s->isr = 0;
  35    s->priority_add = 0;
  36    s->irq_base = 0;
  37    s->read_reg_select = 0;
  38    s->poll = 0;
  39    s->special_mask = 0;
  40    s->init_state = 0;
  41    s->auto_eoi = 0;
  42    s->rotate_on_auto_eoi = 0;
  43    s->special_fully_nested_mode = 0;
  44    s->init4 = 0;
  45    s->single_mode = 0;
  46    /* Note: ELCR is not reset */
  47}
  48
  49static void pic_dispatch_pre_save(void *opaque)
  50{
  51    PICCommonState *s = opaque;
  52    PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
  53
  54    if (info->pre_save) {
  55        info->pre_save(s);
  56    }
  57}
  58
  59static int pic_dispatch_post_load(void *opaque, int version_id)
  60{
  61    PICCommonState *s = opaque;
  62    PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
  63
  64    if (info->post_load) {
  65        info->post_load(s);
  66    }
  67    return 0;
  68}
  69
  70static void pic_common_realize(DeviceState *dev, Error **errp)
  71{
  72    PICCommonState *s = PIC_COMMON(dev);
  73    ISADevice *isa = ISA_DEVICE(dev);
  74
  75    isa_register_ioport(isa, &s->base_io, s->iobase);
  76    if (s->elcr_addr != -1) {
  77        isa_register_ioport(isa, &s->elcr_io, s->elcr_addr);
  78    }
  79
  80    qdev_set_legacy_instance_id(dev, s->iobase, 1);
  81}
  82
  83ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master)
  84{
  85    DeviceState *dev;
  86    ISADevice *isadev;
  87
  88    isadev = isa_create(bus, name);
  89    dev = DEVICE(isadev);
  90    qdev_prop_set_uint32(dev, "iobase", master ? 0x20 : 0xa0);
  91    qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1);
  92    qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde);
  93    qdev_prop_set_bit(dev, "master", master);
  94    qdev_init_nofail(dev);
  95
  96    return isadev;
  97}
  98
  99static const VMStateDescription vmstate_pic_common = {
 100    .name = "i8259",
 101    .version_id = 1,
 102    .minimum_version_id = 1,
 103    .pre_save = pic_dispatch_pre_save,
 104    .post_load = pic_dispatch_post_load,
 105    .fields = (VMStateField[]) {
 106        VMSTATE_UINT8(last_irr, PICCommonState),
 107        VMSTATE_UINT8(irr, PICCommonState),
 108        VMSTATE_UINT8(imr, PICCommonState),
 109        VMSTATE_UINT8(isr, PICCommonState),
 110        VMSTATE_UINT8(priority_add, PICCommonState),
 111        VMSTATE_UINT8(irq_base, PICCommonState),
 112        VMSTATE_UINT8(read_reg_select, PICCommonState),
 113        VMSTATE_UINT8(poll, PICCommonState),
 114        VMSTATE_UINT8(special_mask, PICCommonState),
 115        VMSTATE_UINT8(init_state, PICCommonState),
 116        VMSTATE_UINT8(auto_eoi, PICCommonState),
 117        VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState),
 118        VMSTATE_UINT8(special_fully_nested_mode, PICCommonState),
 119        VMSTATE_UINT8(init4, PICCommonState),
 120        VMSTATE_UINT8(single_mode, PICCommonState),
 121        VMSTATE_UINT8(elcr, PICCommonState),
 122        VMSTATE_END_OF_LIST()
 123    }
 124};
 125
 126static Property pic_properties_common[] = {
 127    DEFINE_PROP_UINT32("iobase", PICCommonState, iobase,  -1),
 128    DEFINE_PROP_UINT32("elcr_addr", PICCommonState, elcr_addr,  -1),
 129    DEFINE_PROP_UINT8("elcr_mask", PICCommonState, elcr_mask,  -1),
 130    DEFINE_PROP_BIT("master", PICCommonState, master,  0, false),
 131    DEFINE_PROP_END_OF_LIST(),
 132};
 133
 134static void pic_common_class_init(ObjectClass *klass, void *data)
 135{
 136    DeviceClass *dc = DEVICE_CLASS(klass);
 137
 138    dc->vmsd = &vmstate_pic_common;
 139    dc->props = pic_properties_common;
 140    dc->realize = pic_common_realize;
 141    /*
 142     * Reason: unlike ordinary ISA devices, the PICs need additional
 143     * wiring: its IRQ input lines are set up by board code, and the
 144     * wiring of the slave to the master is hard-coded in device model
 145     * code.
 146     */
 147    dc->cannot_instantiate_with_device_add_yet = true;
 148}
 149
 150static const TypeInfo pic_common_type = {
 151    .name = TYPE_PIC_COMMON,
 152    .parent = TYPE_ISA_DEVICE,
 153    .instance_size = sizeof(PICCommonState),
 154    .class_size = sizeof(PICCommonClass),
 155    .class_init = pic_common_class_init,
 156    .abstract = true,
 157};
 158
 159static void pic_common_register_types(void)
 160{
 161    type_register_static(&pic_common_type);
 162}
 163
 164type_init(pic_common_register_types)
 165