qemu/hw/arm/pxa2xx.c
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   1/*
   2 * Intel XScale PXA255/270 processor support.
   3 *
   4 * Copyright (c) 2006 Openedhand Ltd.
   5 * Written by Andrzej Zaborowski <balrog@zabor.org>
   6 *
   7 * This code is licensed under the GPL.
   8 */
   9
  10#include "qemu/osdep.h"
  11#include "qapi/error.h"
  12#include "qemu-common.h"
  13#include "cpu.h"
  14#include "hw/sysbus.h"
  15#include "hw/arm/pxa.h"
  16#include "sysemu/sysemu.h"
  17#include "hw/char/serial.h"
  18#include "hw/i2c/i2c.h"
  19#include "hw/ssi/ssi.h"
  20#include "sysemu/char.h"
  21#include "sysemu/block-backend.h"
  22#include "sysemu/blockdev.h"
  23#include "qemu/cutils.h"
  24
  25static struct {
  26    hwaddr io_base;
  27    int irqn;
  28} pxa255_serial[] = {
  29    { 0x40100000, PXA2XX_PIC_FFUART },
  30    { 0x40200000, PXA2XX_PIC_BTUART },
  31    { 0x40700000, PXA2XX_PIC_STUART },
  32    { 0x41600000, PXA25X_PIC_HWUART },
  33    { 0, 0 }
  34}, pxa270_serial[] = {
  35    { 0x40100000, PXA2XX_PIC_FFUART },
  36    { 0x40200000, PXA2XX_PIC_BTUART },
  37    { 0x40700000, PXA2XX_PIC_STUART },
  38    { 0, 0 }
  39};
  40
  41typedef struct PXASSPDef {
  42    hwaddr io_base;
  43    int irqn;
  44} PXASSPDef;
  45
  46#if 0
  47static PXASSPDef pxa250_ssp[] = {
  48    { 0x41000000, PXA2XX_PIC_SSP },
  49    { 0, 0 }
  50};
  51#endif
  52
  53static PXASSPDef pxa255_ssp[] = {
  54    { 0x41000000, PXA2XX_PIC_SSP },
  55    { 0x41400000, PXA25X_PIC_NSSP },
  56    { 0, 0 }
  57};
  58
  59#if 0
  60static PXASSPDef pxa26x_ssp[] = {
  61    { 0x41000000, PXA2XX_PIC_SSP },
  62    { 0x41400000, PXA25X_PIC_NSSP },
  63    { 0x41500000, PXA26X_PIC_ASSP },
  64    { 0, 0 }
  65};
  66#endif
  67
  68static PXASSPDef pxa27x_ssp[] = {
  69    { 0x41000000, PXA2XX_PIC_SSP },
  70    { 0x41700000, PXA27X_PIC_SSP2 },
  71    { 0x41900000, PXA2XX_PIC_SSP3 },
  72    { 0, 0 }
  73};
  74
  75#define PMCR    0x00    /* Power Manager Control register */
  76#define PSSR    0x04    /* Power Manager Sleep Status register */
  77#define PSPR    0x08    /* Power Manager Scratch-Pad register */
  78#define PWER    0x0c    /* Power Manager Wake-Up Enable register */
  79#define PRER    0x10    /* Power Manager Rising-Edge Detect Enable register */
  80#define PFER    0x14    /* Power Manager Falling-Edge Detect Enable register */
  81#define PEDR    0x18    /* Power Manager Edge-Detect Status register */
  82#define PCFR    0x1c    /* Power Manager General Configuration register */
  83#define PGSR0   0x20    /* Power Manager GPIO Sleep-State register 0 */
  84#define PGSR1   0x24    /* Power Manager GPIO Sleep-State register 1 */
  85#define PGSR2   0x28    /* Power Manager GPIO Sleep-State register 2 */
  86#define PGSR3   0x2c    /* Power Manager GPIO Sleep-State register 3 */
  87#define RCSR    0x30    /* Reset Controller Status register */
  88#define PSLR    0x34    /* Power Manager Sleep Configuration register */
  89#define PTSR    0x38    /* Power Manager Standby Configuration register */
  90#define PVCR    0x40    /* Power Manager Voltage Change Control register */
  91#define PUCR    0x4c    /* Power Manager USIM Card Control/Status register */
  92#define PKWR    0x50    /* Power Manager Keyboard Wake-Up Enable register */
  93#define PKSR    0x54    /* Power Manager Keyboard Level-Detect Status */
  94#define PCMD0   0x80    /* Power Manager I2C Command register File 0 */
  95#define PCMD31  0xfc    /* Power Manager I2C Command register File 31 */
  96
  97static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
  98                               unsigned size)
  99{
 100    PXA2xxState *s = (PXA2xxState *) opaque;
 101
 102    switch (addr) {
 103    case PMCR ... PCMD31:
 104        if (addr & 3)
 105            goto fail;
 106
 107        return s->pm_regs[addr >> 2];
 108    default:
 109    fail:
 110        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
 111        break;
 112    }
 113    return 0;
 114}
 115
 116static void pxa2xx_pm_write(void *opaque, hwaddr addr,
 117                            uint64_t value, unsigned size)
 118{
 119    PXA2xxState *s = (PXA2xxState *) opaque;
 120
 121    switch (addr) {
 122    case PMCR:
 123        /* Clear the write-one-to-clear bits... */
 124        s->pm_regs[addr >> 2] &= ~(value & 0x2a);
 125        /* ...and set the plain r/w bits */
 126        s->pm_regs[addr >> 2] &= ~0x15;
 127        s->pm_regs[addr >> 2] |= value & 0x15;
 128        break;
 129
 130    case PSSR:  /* Read-clean registers */
 131    case RCSR:
 132    case PKSR:
 133        s->pm_regs[addr >> 2] &= ~value;
 134        break;
 135
 136    default:    /* Read-write registers */
 137        if (!(addr & 3)) {
 138            s->pm_regs[addr >> 2] = value;
 139            break;
 140        }
 141
 142        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
 143        break;
 144    }
 145}
 146
 147static const MemoryRegionOps pxa2xx_pm_ops = {
 148    .read = pxa2xx_pm_read,
 149    .write = pxa2xx_pm_write,
 150    .endianness = DEVICE_NATIVE_ENDIAN,
 151};
 152
 153static const VMStateDescription vmstate_pxa2xx_pm = {
 154    .name = "pxa2xx_pm",
 155    .version_id = 0,
 156    .minimum_version_id = 0,
 157    .fields = (VMStateField[]) {
 158        VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
 159        VMSTATE_END_OF_LIST()
 160    }
 161};
 162
 163#define CCCR    0x00    /* Core Clock Configuration register */
 164#define CKEN    0x04    /* Clock Enable register */
 165#define OSCC    0x08    /* Oscillator Configuration register */
 166#define CCSR    0x0c    /* Core Clock Status register */
 167
 168static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
 169                               unsigned size)
 170{
 171    PXA2xxState *s = (PXA2xxState *) opaque;
 172
 173    switch (addr) {
 174    case CCCR:
 175    case CKEN:
 176    case OSCC:
 177        return s->cm_regs[addr >> 2];
 178
 179    case CCSR:
 180        return s->cm_regs[CCCR >> 2] | (3 << 28);
 181
 182    default:
 183        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
 184        break;
 185    }
 186    return 0;
 187}
 188
 189static void pxa2xx_cm_write(void *opaque, hwaddr addr,
 190                            uint64_t value, unsigned size)
 191{
 192    PXA2xxState *s = (PXA2xxState *) opaque;
 193
 194    switch (addr) {
 195    case CCCR:
 196    case CKEN:
 197        s->cm_regs[addr >> 2] = value;
 198        break;
 199
 200    case OSCC:
 201        s->cm_regs[addr >> 2] &= ~0x6c;
 202        s->cm_regs[addr >> 2] |= value & 0x6e;
 203        if ((value >> 1) & 1)                   /* OON */
 204            s->cm_regs[addr >> 2] |= 1 << 0;    /* Oscillator is now stable */
 205        break;
 206
 207    default:
 208        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
 209        break;
 210    }
 211}
 212
 213static const MemoryRegionOps pxa2xx_cm_ops = {
 214    .read = pxa2xx_cm_read,
 215    .write = pxa2xx_cm_write,
 216    .endianness = DEVICE_NATIVE_ENDIAN,
 217};
 218
 219static const VMStateDescription vmstate_pxa2xx_cm = {
 220    .name = "pxa2xx_cm",
 221    .version_id = 0,
 222    .minimum_version_id = 0,
 223    .fields = (VMStateField[]) {
 224        VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
 225        VMSTATE_UINT32(clkcfg, PXA2xxState),
 226        VMSTATE_UINT32(pmnc, PXA2xxState),
 227        VMSTATE_END_OF_LIST()
 228    }
 229};
 230
 231static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri)
 232{
 233    PXA2xxState *s = (PXA2xxState *)ri->opaque;
 234    return s->clkcfg;
 235}
 236
 237static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
 238                                uint64_t value)
 239{
 240    PXA2xxState *s = (PXA2xxState *)ri->opaque;
 241    s->clkcfg = value & 0xf;
 242    if (value & 2) {
 243        printf("%s: CPU frequency change attempt\n", __func__);
 244    }
 245}
 246
 247static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
 248                                 uint64_t value)
 249{
 250    PXA2xxState *s = (PXA2xxState *)ri->opaque;
 251    static const char *pwrmode[8] = {
 252        "Normal", "Idle", "Deep-idle", "Standby",
 253        "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
 254    };
 255
 256    if (value & 8) {
 257        printf("%s: CPU voltage change attempt\n", __func__);
 258    }
 259    switch (value & 7) {
 260    case 0:
 261        /* Do nothing */
 262        break;
 263
 264    case 1:
 265        /* Idle */
 266        if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
 267            cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
 268            break;
 269        }
 270        /* Fall through.  */
 271
 272    case 2:
 273        /* Deep-Idle */
 274        cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
 275        s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
 276        goto message;
 277
 278    case 3:
 279        s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
 280        s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
 281        s->cpu->env.cp15.sctlr_ns = 0;
 282        s->cpu->env.cp15.cpacr_el1 = 0;
 283        s->cpu->env.cp15.ttbr0_el[1] = 0;
 284        s->cpu->env.cp15.dacr_ns = 0;
 285        s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
 286        s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
 287
 288        /*
 289         * The scratch-pad register is almost universally used
 290         * for storing the return address on suspend.  For the
 291         * lack of a resuming bootloader, perform a jump
 292         * directly to that address.
 293         */
 294        memset(s->cpu->env.regs, 0, 4 * 15);
 295        s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
 296
 297#if 0
 298        buffer = 0xe59ff000; /* ldr     pc, [pc, #0] */
 299        cpu_physical_memory_write(0, &buffer, 4);
 300        buffer = s->pm_regs[PSPR >> 2];
 301        cpu_physical_memory_write(8, &buffer, 4);
 302#endif
 303
 304        /* Suspend */
 305        cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
 306
 307        goto message;
 308
 309    default:
 310    message:
 311        printf("%s: machine entered %s mode\n", __func__,
 312               pwrmode[value & 7]);
 313    }
 314}
 315
 316static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri)
 317{
 318    PXA2xxState *s = (PXA2xxState *)ri->opaque;
 319    return s->pmnc;
 320}
 321
 322static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
 323                                uint64_t value)
 324{
 325    PXA2xxState *s = (PXA2xxState *)ri->opaque;
 326    s->pmnc = value;
 327}
 328
 329static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
 330{
 331    PXA2xxState *s = (PXA2xxState *)ri->opaque;
 332    if (s->pmnc & 1) {
 333        return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 334    } else {
 335        return 0;
 336    }
 337}
 338
 339static const ARMCPRegInfo pxa_cp_reginfo[] = {
 340    /* cp14 crm==1: perf registers */
 341    { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
 342      .access = PL1_RW, .type = ARM_CP_IO,
 343      .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
 344    { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
 345      .access = PL1_RW, .type = ARM_CP_IO,
 346      .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
 347    { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
 348      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 349    { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
 350      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 351    { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
 352      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 353    /* cp14 crm==2: performance count registers */
 354    { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
 355      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 356    { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
 357      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 358    { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
 359      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 360    { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
 361      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 362    /* cp14 crn==6: CLKCFG */
 363    { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
 364      .access = PL1_RW, .type = ARM_CP_IO,
 365      .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
 366    /* cp14 crn==7: PWRMODE */
 367    { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
 368      .access = PL1_RW, .type = ARM_CP_IO,
 369      .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
 370    REGINFO_SENTINEL
 371};
 372
 373static void pxa2xx_setup_cp14(PXA2xxState *s)
 374{
 375    define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
 376}
 377
 378#define MDCNFG          0x00    /* SDRAM Configuration register */
 379#define MDREFR          0x04    /* SDRAM Refresh Control register */
 380#define MSC0            0x08    /* Static Memory Control register 0 */
 381#define MSC1            0x0c    /* Static Memory Control register 1 */
 382#define MSC2            0x10    /* Static Memory Control register 2 */
 383#define MECR            0x14    /* Expansion Memory Bus Config register */
 384#define SXCNFG          0x1c    /* Synchronous Static Memory Config register */
 385#define MCMEM0          0x28    /* PC Card Memory Socket 0 Timing register */
 386#define MCMEM1          0x2c    /* PC Card Memory Socket 1 Timing register */
 387#define MCATT0          0x30    /* PC Card Attribute Socket 0 register */
 388#define MCATT1          0x34    /* PC Card Attribute Socket 1 register */
 389#define MCIO0           0x38    /* PC Card I/O Socket 0 Timing register */
 390#define MCIO1           0x3c    /* PC Card I/O Socket 1 Timing register */
 391#define MDMRS           0x40    /* SDRAM Mode Register Set Config register */
 392#define BOOT_DEF        0x44    /* Boot-time Default Configuration register */
 393#define ARB_CNTL        0x48    /* Arbiter Control register */
 394#define BSCNTR0         0x4c    /* Memory Buffer Strength Control register 0 */
 395#define BSCNTR1         0x50    /* Memory Buffer Strength Control register 1 */
 396#define LCDBSCNTR       0x54    /* LCD Buffer Strength Control register */
 397#define MDMRSLP         0x58    /* Low Power SDRAM Mode Set Config register */
 398#define BSCNTR2         0x5c    /* Memory Buffer Strength Control register 2 */
 399#define BSCNTR3         0x60    /* Memory Buffer Strength Control register 3 */
 400#define SA1110          0x64    /* SA-1110 Memory Compatibility register */
 401
 402static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
 403                               unsigned size)
 404{
 405    PXA2xxState *s = (PXA2xxState *) opaque;
 406
 407    switch (addr) {
 408    case MDCNFG ... SA1110:
 409        if ((addr & 3) == 0)
 410            return s->mm_regs[addr >> 2];
 411
 412    default:
 413        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
 414        break;
 415    }
 416    return 0;
 417}
 418
 419static void pxa2xx_mm_write(void *opaque, hwaddr addr,
 420                            uint64_t value, unsigned size)
 421{
 422    PXA2xxState *s = (PXA2xxState *) opaque;
 423
 424    switch (addr) {
 425    case MDCNFG ... SA1110:
 426        if ((addr & 3) == 0) {
 427            s->mm_regs[addr >> 2] = value;
 428            break;
 429        }
 430
 431    default:
 432        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
 433        break;
 434    }
 435}
 436
 437static const MemoryRegionOps pxa2xx_mm_ops = {
 438    .read = pxa2xx_mm_read,
 439    .write = pxa2xx_mm_write,
 440    .endianness = DEVICE_NATIVE_ENDIAN,
 441};
 442
 443static const VMStateDescription vmstate_pxa2xx_mm = {
 444    .name = "pxa2xx_mm",
 445    .version_id = 0,
 446    .minimum_version_id = 0,
 447    .fields = (VMStateField[]) {
 448        VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
 449        VMSTATE_END_OF_LIST()
 450    }
 451};
 452
 453#define TYPE_PXA2XX_SSP "pxa2xx-ssp"
 454#define PXA2XX_SSP(obj) \
 455    OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
 456
 457/* Synchronous Serial Ports */
 458typedef struct {
 459    /*< private >*/
 460    SysBusDevice parent_obj;
 461    /*< public >*/
 462
 463    MemoryRegion iomem;
 464    qemu_irq irq;
 465    uint32_t enable;
 466    SSIBus *bus;
 467
 468    uint32_t sscr[2];
 469    uint32_t sspsp;
 470    uint32_t ssto;
 471    uint32_t ssitr;
 472    uint32_t sssr;
 473    uint8_t sstsa;
 474    uint8_t ssrsa;
 475    uint8_t ssacd;
 476
 477    uint32_t rx_fifo[16];
 478    uint32_t rx_level;
 479    uint32_t rx_start;
 480} PXA2xxSSPState;
 481
 482static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id)
 483{
 484    PXA2xxSSPState *s = opaque;
 485
 486    return s->rx_start < sizeof(s->rx_fifo);
 487}
 488
 489static const VMStateDescription vmstate_pxa2xx_ssp = {
 490    .name = "pxa2xx-ssp",
 491    .version_id = 1,
 492    .minimum_version_id = 1,
 493    .fields = (VMStateField[]) {
 494        VMSTATE_UINT32(enable, PXA2xxSSPState),
 495        VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2),
 496        VMSTATE_UINT32(sspsp, PXA2xxSSPState),
 497        VMSTATE_UINT32(ssto, PXA2xxSSPState),
 498        VMSTATE_UINT32(ssitr, PXA2xxSSPState),
 499        VMSTATE_UINT32(sssr, PXA2xxSSPState),
 500        VMSTATE_UINT8(sstsa, PXA2xxSSPState),
 501        VMSTATE_UINT8(ssrsa, PXA2xxSSPState),
 502        VMSTATE_UINT8(ssacd, PXA2xxSSPState),
 503        VMSTATE_UINT32(rx_level, PXA2xxSSPState),
 504        VMSTATE_UINT32(rx_start, PXA2xxSSPState),
 505        VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate),
 506        VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16),
 507        VMSTATE_END_OF_LIST()
 508    }
 509};
 510
 511#define SSCR0   0x00    /* SSP Control register 0 */
 512#define SSCR1   0x04    /* SSP Control register 1 */
 513#define SSSR    0x08    /* SSP Status register */
 514#define SSITR   0x0c    /* SSP Interrupt Test register */
 515#define SSDR    0x10    /* SSP Data register */
 516#define SSTO    0x28    /* SSP Time-Out register */
 517#define SSPSP   0x2c    /* SSP Programmable Serial Protocol register */
 518#define SSTSA   0x30    /* SSP TX Time Slot Active register */
 519#define SSRSA   0x34    /* SSP RX Time Slot Active register */
 520#define SSTSS   0x38    /* SSP Time Slot Status register */
 521#define SSACD   0x3c    /* SSP Audio Clock Divider register */
 522
 523/* Bitfields for above registers */
 524#define SSCR0_SPI(x)    (((x) & 0x30) == 0x00)
 525#define SSCR0_SSP(x)    (((x) & 0x30) == 0x10)
 526#define SSCR0_UWIRE(x)  (((x) & 0x30) == 0x20)
 527#define SSCR0_PSP(x)    (((x) & 0x30) == 0x30)
 528#define SSCR0_SSE       (1 << 7)
 529#define SSCR0_RIM       (1 << 22)
 530#define SSCR0_TIM       (1 << 23)
 531#define SSCR0_MOD       (1U << 31)
 532#define SSCR0_DSS(x)    (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
 533#define SSCR1_RIE       (1 << 0)
 534#define SSCR1_TIE       (1 << 1)
 535#define SSCR1_LBM       (1 << 2)
 536#define SSCR1_MWDS      (1 << 5)
 537#define SSCR1_TFT(x)    ((((x) >> 6) & 0xf) + 1)
 538#define SSCR1_RFT(x)    ((((x) >> 10) & 0xf) + 1)
 539#define SSCR1_EFWR      (1 << 14)
 540#define SSCR1_PINTE     (1 << 18)
 541#define SSCR1_TINTE     (1 << 19)
 542#define SSCR1_RSRE      (1 << 20)
 543#define SSCR1_TSRE      (1 << 21)
 544#define SSCR1_EBCEI     (1 << 29)
 545#define SSITR_INT       (7 << 5)
 546#define SSSR_TNF        (1 << 2)
 547#define SSSR_RNE        (1 << 3)
 548#define SSSR_TFS        (1 << 5)
 549#define SSSR_RFS        (1 << 6)
 550#define SSSR_ROR        (1 << 7)
 551#define SSSR_PINT       (1 << 18)
 552#define SSSR_TINT       (1 << 19)
 553#define SSSR_EOC        (1 << 20)
 554#define SSSR_TUR        (1 << 21)
 555#define SSSR_BCE        (1 << 23)
 556#define SSSR_RW         0x00bc0080
 557
 558static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
 559{
 560    int level = 0;
 561
 562    level |= s->ssitr & SSITR_INT;
 563    level |= (s->sssr & SSSR_BCE)  &&  (s->sscr[1] & SSCR1_EBCEI);
 564    level |= (s->sssr & SSSR_TUR)  && !(s->sscr[0] & SSCR0_TIM);
 565    level |= (s->sssr & SSSR_EOC)  &&  (s->sssr & (SSSR_TINT | SSSR_PINT));
 566    level |= (s->sssr & SSSR_TINT) &&  (s->sscr[1] & SSCR1_TINTE);
 567    level |= (s->sssr & SSSR_PINT) &&  (s->sscr[1] & SSCR1_PINTE);
 568    level |= (s->sssr & SSSR_ROR)  && !(s->sscr[0] & SSCR0_RIM);
 569    level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);
 570    level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);
 571    qemu_set_irq(s->irq, !!level);
 572}
 573
 574static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
 575{
 576    s->sssr &= ~(0xf << 12);    /* Clear RFL */
 577    s->sssr &= ~(0xf << 8);     /* Clear TFL */
 578    s->sssr &= ~SSSR_TFS;
 579    s->sssr &= ~SSSR_TNF;
 580    if (s->enable) {
 581        s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
 582        if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
 583            s->sssr |= SSSR_RFS;
 584        else
 585            s->sssr &= ~SSSR_RFS;
 586        if (s->rx_level)
 587            s->sssr |= SSSR_RNE;
 588        else
 589            s->sssr &= ~SSSR_RNE;
 590        /* TX FIFO is never filled, so it is always in underrun
 591           condition if SSP is enabled */
 592        s->sssr |= SSSR_TFS;
 593        s->sssr |= SSSR_TNF;
 594    }
 595
 596    pxa2xx_ssp_int_update(s);
 597}
 598
 599static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
 600                                unsigned size)
 601{
 602    PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
 603    uint32_t retval;
 604
 605    switch (addr) {
 606    case SSCR0:
 607        return s->sscr[0];
 608    case SSCR1:
 609        return s->sscr[1];
 610    case SSPSP:
 611        return s->sspsp;
 612    case SSTO:
 613        return s->ssto;
 614    case SSITR:
 615        return s->ssitr;
 616    case SSSR:
 617        return s->sssr | s->ssitr;
 618    case SSDR:
 619        if (!s->enable)
 620            return 0xffffffff;
 621        if (s->rx_level < 1) {
 622            printf("%s: SSP Rx Underrun\n", __FUNCTION__);
 623            return 0xffffffff;
 624        }
 625        s->rx_level --;
 626        retval = s->rx_fifo[s->rx_start ++];
 627        s->rx_start &= 0xf;
 628        pxa2xx_ssp_fifo_update(s);
 629        return retval;
 630    case SSTSA:
 631        return s->sstsa;
 632    case SSRSA:
 633        return s->ssrsa;
 634    case SSTSS:
 635        return 0;
 636    case SSACD:
 637        return s->ssacd;
 638    default:
 639        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
 640        break;
 641    }
 642    return 0;
 643}
 644
 645static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
 646                             uint64_t value64, unsigned size)
 647{
 648    PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
 649    uint32_t value = value64;
 650
 651    switch (addr) {
 652    case SSCR0:
 653        s->sscr[0] = value & 0xc7ffffff;
 654        s->enable = value & SSCR0_SSE;
 655        if (value & SSCR0_MOD)
 656            printf("%s: Attempt to use network mode\n", __FUNCTION__);
 657        if (s->enable && SSCR0_DSS(value) < 4)
 658            printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
 659                            SSCR0_DSS(value));
 660        if (!(value & SSCR0_SSE)) {
 661            s->sssr = 0;
 662            s->ssitr = 0;
 663            s->rx_level = 0;
 664        }
 665        pxa2xx_ssp_fifo_update(s);
 666        break;
 667
 668    case SSCR1:
 669        s->sscr[1] = value;
 670        if (value & (SSCR1_LBM | SSCR1_EFWR))
 671            printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
 672        pxa2xx_ssp_fifo_update(s);
 673        break;
 674
 675    case SSPSP:
 676        s->sspsp = value;
 677        break;
 678
 679    case SSTO:
 680        s->ssto = value;
 681        break;
 682
 683    case SSITR:
 684        s->ssitr = value & SSITR_INT;
 685        pxa2xx_ssp_int_update(s);
 686        break;
 687
 688    case SSSR:
 689        s->sssr &= ~(value & SSSR_RW);
 690        pxa2xx_ssp_int_update(s);
 691        break;
 692
 693    case SSDR:
 694        if (SSCR0_UWIRE(s->sscr[0])) {
 695            if (s->sscr[1] & SSCR1_MWDS)
 696                value &= 0xffff;
 697            else
 698                value &= 0xff;
 699        } else
 700            /* Note how 32bits overflow does no harm here */
 701            value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
 702
 703        /* Data goes from here to the Tx FIFO and is shifted out from
 704         * there directly to the slave, no need to buffer it.
 705         */
 706        if (s->enable) {
 707            uint32_t readval;
 708            readval = ssi_transfer(s->bus, value);
 709            if (s->rx_level < 0x10) {
 710                s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
 711            } else {
 712                s->sssr |= SSSR_ROR;
 713            }
 714        }
 715        pxa2xx_ssp_fifo_update(s);
 716        break;
 717
 718    case SSTSA:
 719        s->sstsa = value;
 720        break;
 721
 722    case SSRSA:
 723        s->ssrsa = value;
 724        break;
 725
 726    case SSACD:
 727        s->ssacd = value;
 728        break;
 729
 730    default:
 731        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
 732        break;
 733    }
 734}
 735
 736static const MemoryRegionOps pxa2xx_ssp_ops = {
 737    .read = pxa2xx_ssp_read,
 738    .write = pxa2xx_ssp_write,
 739    .endianness = DEVICE_NATIVE_ENDIAN,
 740};
 741
 742static void pxa2xx_ssp_reset(DeviceState *d)
 743{
 744    PXA2xxSSPState *s = PXA2XX_SSP(d);
 745
 746    s->enable = 0;
 747    s->sscr[0] = s->sscr[1] = 0;
 748    s->sspsp = 0;
 749    s->ssto = 0;
 750    s->ssitr = 0;
 751    s->sssr = 0;
 752    s->sstsa = 0;
 753    s->ssrsa = 0;
 754    s->ssacd = 0;
 755    s->rx_start = s->rx_level = 0;
 756}
 757
 758static int pxa2xx_ssp_init(SysBusDevice *sbd)
 759{
 760    DeviceState *dev = DEVICE(sbd);
 761    PXA2xxSSPState *s = PXA2XX_SSP(dev);
 762
 763    sysbus_init_irq(sbd, &s->irq);
 764
 765    memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
 766                          "pxa2xx-ssp", 0x1000);
 767    sysbus_init_mmio(sbd, &s->iomem);
 768
 769    s->bus = ssi_create_bus(dev, "ssi");
 770    return 0;
 771}
 772
 773/* Real-Time Clock */
 774#define RCNR            0x00    /* RTC Counter register */
 775#define RTAR            0x04    /* RTC Alarm register */
 776#define RTSR            0x08    /* RTC Status register */
 777#define RTTR            0x0c    /* RTC Timer Trim register */
 778#define RDCR            0x10    /* RTC Day Counter register */
 779#define RYCR            0x14    /* RTC Year Counter register */
 780#define RDAR1           0x18    /* RTC Wristwatch Day Alarm register 1 */
 781#define RYAR1           0x1c    /* RTC Wristwatch Year Alarm register 1 */
 782#define RDAR2           0x20    /* RTC Wristwatch Day Alarm register 2 */
 783#define RYAR2           0x24    /* RTC Wristwatch Year Alarm register 2 */
 784#define SWCR            0x28    /* RTC Stopwatch Counter register */
 785#define SWAR1           0x2c    /* RTC Stopwatch Alarm register 1 */
 786#define SWAR2           0x30    /* RTC Stopwatch Alarm register 2 */
 787#define RTCPICR         0x34    /* RTC Periodic Interrupt Counter register */
 788#define PIAR            0x38    /* RTC Periodic Interrupt Alarm register */
 789
 790#define TYPE_PXA2XX_RTC "pxa2xx_rtc"
 791#define PXA2XX_RTC(obj) \
 792    OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
 793
 794typedef struct {
 795    /*< private >*/
 796    SysBusDevice parent_obj;
 797    /*< public >*/
 798
 799    MemoryRegion iomem;
 800    uint32_t rttr;
 801    uint32_t rtsr;
 802    uint32_t rtar;
 803    uint32_t rdar1;
 804    uint32_t rdar2;
 805    uint32_t ryar1;
 806    uint32_t ryar2;
 807    uint32_t swar1;
 808    uint32_t swar2;
 809    uint32_t piar;
 810    uint32_t last_rcnr;
 811    uint32_t last_rdcr;
 812    uint32_t last_rycr;
 813    uint32_t last_swcr;
 814    uint32_t last_rtcpicr;
 815    int64_t last_hz;
 816    int64_t last_sw;
 817    int64_t last_pi;
 818    QEMUTimer *rtc_hz;
 819    QEMUTimer *rtc_rdal1;
 820    QEMUTimer *rtc_rdal2;
 821    QEMUTimer *rtc_swal1;
 822    QEMUTimer *rtc_swal2;
 823    QEMUTimer *rtc_pi;
 824    qemu_irq rtc_irq;
 825} PXA2xxRTCState;
 826
 827static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
 828{
 829    qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
 830}
 831
 832static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
 833{
 834    int64_t rt = qemu_clock_get_ms(rtc_clock);
 835    s->last_rcnr += ((rt - s->last_hz) << 15) /
 836            (1000 * ((s->rttr & 0xffff) + 1));
 837    s->last_rdcr += ((rt - s->last_hz) << 15) /
 838            (1000 * ((s->rttr & 0xffff) + 1));
 839    s->last_hz = rt;
 840}
 841
 842static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
 843{
 844    int64_t rt = qemu_clock_get_ms(rtc_clock);
 845    if (s->rtsr & (1 << 12))
 846        s->last_swcr += (rt - s->last_sw) / 10;
 847    s->last_sw = rt;
 848}
 849
 850static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
 851{
 852    int64_t rt = qemu_clock_get_ms(rtc_clock);
 853    if (s->rtsr & (1 << 15))
 854        s->last_swcr += rt - s->last_pi;
 855    s->last_pi = rt;
 856}
 857
 858static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
 859                uint32_t rtsr)
 860{
 861    if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
 862        timer_mod(s->rtc_hz, s->last_hz +
 863                (((s->rtar - s->last_rcnr) * 1000 *
 864                  ((s->rttr & 0xffff) + 1)) >> 15));
 865    else
 866        timer_del(s->rtc_hz);
 867
 868    if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
 869        timer_mod(s->rtc_rdal1, s->last_hz +
 870                (((s->rdar1 - s->last_rdcr) * 1000 *
 871                  ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
 872    else
 873        timer_del(s->rtc_rdal1);
 874
 875    if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
 876        timer_mod(s->rtc_rdal2, s->last_hz +
 877                (((s->rdar2 - s->last_rdcr) * 1000 *
 878                  ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
 879    else
 880        timer_del(s->rtc_rdal2);
 881
 882    if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
 883        timer_mod(s->rtc_swal1, s->last_sw +
 884                        (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
 885    else
 886        timer_del(s->rtc_swal1);
 887
 888    if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
 889        timer_mod(s->rtc_swal2, s->last_sw +
 890                        (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
 891    else
 892        timer_del(s->rtc_swal2);
 893
 894    if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
 895        timer_mod(s->rtc_pi, s->last_pi +
 896                        (s->piar & 0xffff) - s->last_rtcpicr);
 897    else
 898        timer_del(s->rtc_pi);
 899}
 900
 901static inline void pxa2xx_rtc_hz_tick(void *opaque)
 902{
 903    PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
 904    s->rtsr |= (1 << 0);
 905    pxa2xx_rtc_alarm_update(s, s->rtsr);
 906    pxa2xx_rtc_int_update(s);
 907}
 908
 909static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
 910{
 911    PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
 912    s->rtsr |= (1 << 4);
 913    pxa2xx_rtc_alarm_update(s, s->rtsr);
 914    pxa2xx_rtc_int_update(s);
 915}
 916
 917static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
 918{
 919    PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
 920    s->rtsr |= (1 << 6);
 921    pxa2xx_rtc_alarm_update(s, s->rtsr);
 922    pxa2xx_rtc_int_update(s);
 923}
 924
 925static inline void pxa2xx_rtc_swal1_tick(void *opaque)
 926{
 927    PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
 928    s->rtsr |= (1 << 8);
 929    pxa2xx_rtc_alarm_update(s, s->rtsr);
 930    pxa2xx_rtc_int_update(s);
 931}
 932
 933static inline void pxa2xx_rtc_swal2_tick(void *opaque)
 934{
 935    PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
 936    s->rtsr |= (1 << 10);
 937    pxa2xx_rtc_alarm_update(s, s->rtsr);
 938    pxa2xx_rtc_int_update(s);
 939}
 940
 941static inline void pxa2xx_rtc_pi_tick(void *opaque)
 942{
 943    PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
 944    s->rtsr |= (1 << 13);
 945    pxa2xx_rtc_piupdate(s);
 946    s->last_rtcpicr = 0;
 947    pxa2xx_rtc_alarm_update(s, s->rtsr);
 948    pxa2xx_rtc_int_update(s);
 949}
 950
 951static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
 952                                unsigned size)
 953{
 954    PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
 955
 956    switch (addr) {
 957    case RTTR:
 958        return s->rttr;
 959    case RTSR:
 960        return s->rtsr;
 961    case RTAR:
 962        return s->rtar;
 963    case RDAR1:
 964        return s->rdar1;
 965    case RDAR2:
 966        return s->rdar2;
 967    case RYAR1:
 968        return s->ryar1;
 969    case RYAR2:
 970        return s->ryar2;
 971    case SWAR1:
 972        return s->swar1;
 973    case SWAR2:
 974        return s->swar2;
 975    case PIAR:
 976        return s->piar;
 977    case RCNR:
 978        return s->last_rcnr +
 979            ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
 980            (1000 * ((s->rttr & 0xffff) + 1));
 981    case RDCR:
 982        return s->last_rdcr +
 983            ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
 984            (1000 * ((s->rttr & 0xffff) + 1));
 985    case RYCR:
 986        return s->last_rycr;
 987    case SWCR:
 988        if (s->rtsr & (1 << 12))
 989            return s->last_swcr +
 990                (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10;
 991        else
 992            return s->last_swcr;
 993    default:
 994        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
 995        break;
 996    }
 997    return 0;
 998}
 999
1000static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
1001                             uint64_t value64, unsigned size)
1002{
1003    PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1004    uint32_t value = value64;
1005
1006    switch (addr) {
1007    case RTTR:
1008        if (!(s->rttr & (1U << 31))) {
1009            pxa2xx_rtc_hzupdate(s);
1010            s->rttr = value;
1011            pxa2xx_rtc_alarm_update(s, s->rtsr);
1012        }
1013        break;
1014
1015    case RTSR:
1016        if ((s->rtsr ^ value) & (1 << 15))
1017            pxa2xx_rtc_piupdate(s);
1018
1019        if ((s->rtsr ^ value) & (1 << 12))
1020            pxa2xx_rtc_swupdate(s);
1021
1022        if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1023            pxa2xx_rtc_alarm_update(s, value);
1024
1025        s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1026        pxa2xx_rtc_int_update(s);
1027        break;
1028
1029    case RTAR:
1030        s->rtar = value;
1031        pxa2xx_rtc_alarm_update(s, s->rtsr);
1032        break;
1033
1034    case RDAR1:
1035        s->rdar1 = value;
1036        pxa2xx_rtc_alarm_update(s, s->rtsr);
1037        break;
1038
1039    case RDAR2:
1040        s->rdar2 = value;
1041        pxa2xx_rtc_alarm_update(s, s->rtsr);
1042        break;
1043
1044    case RYAR1:
1045        s->ryar1 = value;
1046        pxa2xx_rtc_alarm_update(s, s->rtsr);
1047        break;
1048
1049    case RYAR2:
1050        s->ryar2 = value;
1051        pxa2xx_rtc_alarm_update(s, s->rtsr);
1052        break;
1053
1054    case SWAR1:
1055        pxa2xx_rtc_swupdate(s);
1056        s->swar1 = value;
1057        s->last_swcr = 0;
1058        pxa2xx_rtc_alarm_update(s, s->rtsr);
1059        break;
1060
1061    case SWAR2:
1062        s->swar2 = value;
1063        pxa2xx_rtc_alarm_update(s, s->rtsr);
1064        break;
1065
1066    case PIAR:
1067        s->piar = value;
1068        pxa2xx_rtc_alarm_update(s, s->rtsr);
1069        break;
1070
1071    case RCNR:
1072        pxa2xx_rtc_hzupdate(s);
1073        s->last_rcnr = value;
1074        pxa2xx_rtc_alarm_update(s, s->rtsr);
1075        break;
1076
1077    case RDCR:
1078        pxa2xx_rtc_hzupdate(s);
1079        s->last_rdcr = value;
1080        pxa2xx_rtc_alarm_update(s, s->rtsr);
1081        break;
1082
1083    case RYCR:
1084        s->last_rycr = value;
1085        break;
1086
1087    case SWCR:
1088        pxa2xx_rtc_swupdate(s);
1089        s->last_swcr = value;
1090        pxa2xx_rtc_alarm_update(s, s->rtsr);
1091        break;
1092
1093    case RTCPICR:
1094        pxa2xx_rtc_piupdate(s);
1095        s->last_rtcpicr = value & 0xffff;
1096        pxa2xx_rtc_alarm_update(s, s->rtsr);
1097        break;
1098
1099    default:
1100        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1101    }
1102}
1103
1104static const MemoryRegionOps pxa2xx_rtc_ops = {
1105    .read = pxa2xx_rtc_read,
1106    .write = pxa2xx_rtc_write,
1107    .endianness = DEVICE_NATIVE_ENDIAN,
1108};
1109
1110static void pxa2xx_rtc_init(Object *obj)
1111{
1112    PXA2xxRTCState *s = PXA2XX_RTC(obj);
1113    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1114    struct tm tm;
1115    int wom;
1116
1117    s->rttr = 0x7fff;
1118    s->rtsr = 0;
1119
1120    qemu_get_timedate(&tm, 0);
1121    wom = ((tm.tm_mday - 1) / 7) + 1;
1122
1123    s->last_rcnr = (uint32_t) mktimegm(&tm);
1124    s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1125            (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1126    s->last_rycr = ((tm.tm_year + 1900) << 9) |
1127            ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1128    s->last_swcr = (tm.tm_hour << 19) |
1129            (tm.tm_min << 13) | (tm.tm_sec << 7);
1130    s->last_rtcpicr = 0;
1131    s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock);
1132
1133    s->rtc_hz    = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick,    s);
1134    s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
1135    s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
1136    s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
1137    s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
1138    s->rtc_pi    = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick,    s);
1139
1140    sysbus_init_irq(dev, &s->rtc_irq);
1141
1142    memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s,
1143                          "pxa2xx-rtc", 0x10000);
1144    sysbus_init_mmio(dev, &s->iomem);
1145}
1146
1147static void pxa2xx_rtc_pre_save(void *opaque)
1148{
1149    PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1150
1151    pxa2xx_rtc_hzupdate(s);
1152    pxa2xx_rtc_piupdate(s);
1153    pxa2xx_rtc_swupdate(s);
1154}
1155
1156static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1157{
1158    PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1159
1160    pxa2xx_rtc_alarm_update(s, s->rtsr);
1161
1162    return 0;
1163}
1164
1165static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1166    .name = "pxa2xx_rtc",
1167    .version_id = 0,
1168    .minimum_version_id = 0,
1169    .pre_save = pxa2xx_rtc_pre_save,
1170    .post_load = pxa2xx_rtc_post_load,
1171    .fields = (VMStateField[]) {
1172        VMSTATE_UINT32(rttr, PXA2xxRTCState),
1173        VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1174        VMSTATE_UINT32(rtar, PXA2xxRTCState),
1175        VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1176        VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1177        VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1178        VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1179        VMSTATE_UINT32(swar1, PXA2xxRTCState),
1180        VMSTATE_UINT32(swar2, PXA2xxRTCState),
1181        VMSTATE_UINT32(piar, PXA2xxRTCState),
1182        VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1183        VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1184        VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1185        VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1186        VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1187        VMSTATE_INT64(last_hz, PXA2xxRTCState),
1188        VMSTATE_INT64(last_sw, PXA2xxRTCState),
1189        VMSTATE_INT64(last_pi, PXA2xxRTCState),
1190        VMSTATE_END_OF_LIST(),
1191    },
1192};
1193
1194static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
1195{
1196    DeviceClass *dc = DEVICE_CLASS(klass);
1197
1198    dc->desc = "PXA2xx RTC Controller";
1199    dc->vmsd = &vmstate_pxa2xx_rtc_regs;
1200}
1201
1202static const TypeInfo pxa2xx_rtc_sysbus_info = {
1203    .name          = TYPE_PXA2XX_RTC,
1204    .parent        = TYPE_SYS_BUS_DEVICE,
1205    .instance_size = sizeof(PXA2xxRTCState),
1206    .instance_init = pxa2xx_rtc_init,
1207    .class_init    = pxa2xx_rtc_sysbus_class_init,
1208};
1209
1210/* I2C Interface */
1211
1212#define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
1213#define PXA2XX_I2C_SLAVE(obj) \
1214    OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE)
1215
1216typedef struct PXA2xxI2CSlaveState {
1217    I2CSlave parent_obj;
1218
1219    PXA2xxI2CState *host;
1220} PXA2xxI2CSlaveState;
1221
1222#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
1223#define PXA2XX_I2C(obj) \
1224    OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
1225
1226struct PXA2xxI2CState {
1227    /*< private >*/
1228    SysBusDevice parent_obj;
1229    /*< public >*/
1230
1231    MemoryRegion iomem;
1232    PXA2xxI2CSlaveState *slave;
1233    I2CBus *bus;
1234    qemu_irq irq;
1235    uint32_t offset;
1236    uint32_t region_size;
1237
1238    uint16_t control;
1239    uint16_t status;
1240    uint8_t ibmr;
1241    uint8_t data;
1242};
1243
1244#define IBMR    0x80    /* I2C Bus Monitor register */
1245#define IDBR    0x88    /* I2C Data Buffer register */
1246#define ICR     0x90    /* I2C Control register */
1247#define ISR     0x98    /* I2C Status register */
1248#define ISAR    0xa0    /* I2C Slave Address register */
1249
1250static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1251{
1252    uint16_t level = 0;
1253    level |= s->status & s->control & (1 << 10);                /* BED */
1254    level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1255    level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1256    level |= s->status & (1 << 9);                              /* SAD */
1257    qemu_set_irq(s->irq, !!level);
1258}
1259
1260/* These are only stubs now.  */
1261static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event)
1262{
1263    PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1264    PXA2xxI2CState *s = slave->host;
1265
1266    switch (event) {
1267    case I2C_START_SEND:
1268        s->status |= (1 << 9);                          /* set SAD */
1269        s->status &= ~(1 << 0);                         /* clear RWM */
1270        break;
1271    case I2C_START_RECV:
1272        s->status |= (1 << 9);                          /* set SAD */
1273        s->status |= 1 << 0;                            /* set RWM */
1274        break;
1275    case I2C_FINISH:
1276        s->status |= (1 << 4);                          /* set SSD */
1277        break;
1278    case I2C_NACK:
1279        s->status |= 1 << 1;                            /* set ACKNAK */
1280        break;
1281    }
1282    pxa2xx_i2c_update(s);
1283}
1284
1285static int pxa2xx_i2c_rx(I2CSlave *i2c)
1286{
1287    PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1288    PXA2xxI2CState *s = slave->host;
1289
1290    if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1291        return 0;
1292    }
1293
1294    if (s->status & (1 << 0)) {                 /* RWM */
1295        s->status |= 1 << 6;                    /* set ITE */
1296    }
1297    pxa2xx_i2c_update(s);
1298
1299    return s->data;
1300}
1301
1302static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
1303{
1304    PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1305    PXA2xxI2CState *s = slave->host;
1306
1307    if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1308        return 1;
1309    }
1310
1311    if (!(s->status & (1 << 0))) {              /* RWM */
1312        s->status |= 1 << 7;                    /* set IRF */
1313        s->data = data;
1314    }
1315    pxa2xx_i2c_update(s);
1316
1317    return 1;
1318}
1319
1320static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
1321                                unsigned size)
1322{
1323    PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1324    I2CSlave *slave;
1325
1326    addr -= s->offset;
1327    switch (addr) {
1328    case ICR:
1329        return s->control;
1330    case ISR:
1331        return s->status | (i2c_bus_busy(s->bus) << 2);
1332    case ISAR:
1333        slave = I2C_SLAVE(s->slave);
1334        return slave->address;
1335    case IDBR:
1336        return s->data;
1337    case IBMR:
1338        if (s->status & (1 << 2))
1339            s->ibmr ^= 3;       /* Fake SCL and SDA pin changes */
1340        else
1341            s->ibmr = 0;
1342        return s->ibmr;
1343    default:
1344        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1345        break;
1346    }
1347    return 0;
1348}
1349
1350static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
1351                             uint64_t value64, unsigned size)
1352{
1353    PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1354    uint32_t value = value64;
1355    int ack;
1356
1357    addr -= s->offset;
1358    switch (addr) {
1359    case ICR:
1360        s->control = value & 0xfff7;
1361        if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1362            /* TODO: slave mode */
1363            if (value & (1 << 0)) {                     /* START condition */
1364                if (s->data & 1)
1365                    s->status |= 1 << 0;                /* set RWM */
1366                else
1367                    s->status &= ~(1 << 0);             /* clear RWM */
1368                ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1369            } else {
1370                if (s->status & (1 << 0)) {             /* RWM */
1371                    s->data = i2c_recv(s->bus);
1372                    if (value & (1 << 2))               /* ACKNAK */
1373                        i2c_nack(s->bus);
1374                    ack = 1;
1375                } else
1376                    ack = !i2c_send(s->bus, s->data);
1377            }
1378
1379            if (value & (1 << 1))                       /* STOP condition */
1380                i2c_end_transfer(s->bus);
1381
1382            if (ack) {
1383                if (value & (1 << 0))                   /* START condition */
1384                    s->status |= 1 << 6;                /* set ITE */
1385                else
1386                    if (s->status & (1 << 0))           /* RWM */
1387                        s->status |= 1 << 7;            /* set IRF */
1388                    else
1389                        s->status |= 1 << 6;            /* set ITE */
1390                s->status &= ~(1 << 1);                 /* clear ACKNAK */
1391            } else {
1392                s->status |= 1 << 6;                    /* set ITE */
1393                s->status |= 1 << 10;                   /* set BED */
1394                s->status |= 1 << 1;                    /* set ACKNAK */
1395            }
1396        }
1397        if (!(value & (1 << 3)) && (value & (1 << 6)))  /* !TB and IUE */
1398            if (value & (1 << 4))                       /* MA */
1399                i2c_end_transfer(s->bus);
1400        pxa2xx_i2c_update(s);
1401        break;
1402
1403    case ISR:
1404        s->status &= ~(value & 0x07f0);
1405        pxa2xx_i2c_update(s);
1406        break;
1407
1408    case ISAR:
1409        i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f);
1410        break;
1411
1412    case IDBR:
1413        s->data = value & 0xff;
1414        break;
1415
1416    default:
1417        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1418    }
1419}
1420
1421static const MemoryRegionOps pxa2xx_i2c_ops = {
1422    .read = pxa2xx_i2c_read,
1423    .write = pxa2xx_i2c_write,
1424    .endianness = DEVICE_NATIVE_ENDIAN,
1425};
1426
1427static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1428    .name = "pxa2xx_i2c_slave",
1429    .version_id = 1,
1430    .minimum_version_id = 1,
1431    .fields = (VMStateField[]) {
1432        VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState),
1433        VMSTATE_END_OF_LIST()
1434    }
1435};
1436
1437static const VMStateDescription vmstate_pxa2xx_i2c = {
1438    .name = "pxa2xx_i2c",
1439    .version_id = 1,
1440    .minimum_version_id = 1,
1441    .fields = (VMStateField[]) {
1442        VMSTATE_UINT16(control, PXA2xxI2CState),
1443        VMSTATE_UINT16(status, PXA2xxI2CState),
1444        VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1445        VMSTATE_UINT8(data, PXA2xxI2CState),
1446        VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1447                               vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState),
1448        VMSTATE_END_OF_LIST()
1449    }
1450};
1451
1452static int pxa2xx_i2c_slave_init(I2CSlave *i2c)
1453{
1454    /* Nothing to do.  */
1455    return 0;
1456}
1457
1458static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
1459{
1460    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1461
1462    k->init = pxa2xx_i2c_slave_init;
1463    k->event = pxa2xx_i2c_event;
1464    k->recv = pxa2xx_i2c_rx;
1465    k->send = pxa2xx_i2c_tx;
1466}
1467
1468static const TypeInfo pxa2xx_i2c_slave_info = {
1469    .name          = TYPE_PXA2XX_I2C_SLAVE,
1470    .parent        = TYPE_I2C_SLAVE,
1471    .instance_size = sizeof(PXA2xxI2CSlaveState),
1472    .class_init    = pxa2xx_i2c_slave_class_init,
1473};
1474
1475PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
1476                qemu_irq irq, uint32_t region_size)
1477{
1478    DeviceState *dev;
1479    SysBusDevice *i2c_dev;
1480    PXA2xxI2CState *s;
1481    I2CBus *i2cbus;
1482
1483    dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
1484    qdev_prop_set_uint32(dev, "size", region_size + 1);
1485    qdev_prop_set_uint32(dev, "offset", base & region_size);
1486    qdev_init_nofail(dev);
1487
1488    i2c_dev = SYS_BUS_DEVICE(dev);
1489    sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1490    sysbus_connect_irq(i2c_dev, 0, irq);
1491
1492    s = PXA2XX_I2C(i2c_dev);
1493    /* FIXME: Should the slave device really be on a separate bus?  */
1494    i2cbus = i2c_init_bus(dev, "dummy");
1495    dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0);
1496    s->slave = PXA2XX_I2C_SLAVE(dev);
1497    s->slave->host = s;
1498
1499    return s;
1500}
1501
1502static void pxa2xx_i2c_initfn(Object *obj)
1503{
1504    DeviceState *dev = DEVICE(obj);
1505    PXA2xxI2CState *s = PXA2XX_I2C(obj);
1506    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1507
1508    s->bus = i2c_init_bus(dev, NULL);
1509
1510    memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s,
1511                          "pxa2xx-i2c", s->region_size);
1512    sysbus_init_mmio(sbd, &s->iomem);
1513    sysbus_init_irq(sbd, &s->irq);
1514}
1515
1516I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1517{
1518    return s->bus;
1519}
1520
1521static Property pxa2xx_i2c_properties[] = {
1522    DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1523    DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1524    DEFINE_PROP_END_OF_LIST(),
1525};
1526
1527static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
1528{
1529    DeviceClass *dc = DEVICE_CLASS(klass);
1530
1531    dc->desc = "PXA2xx I2C Bus Controller";
1532    dc->vmsd = &vmstate_pxa2xx_i2c;
1533    dc->props = pxa2xx_i2c_properties;
1534}
1535
1536static const TypeInfo pxa2xx_i2c_info = {
1537    .name          = TYPE_PXA2XX_I2C,
1538    .parent        = TYPE_SYS_BUS_DEVICE,
1539    .instance_size = sizeof(PXA2xxI2CState),
1540    .instance_init = pxa2xx_i2c_initfn,
1541    .class_init    = pxa2xx_i2c_class_init,
1542};
1543
1544/* PXA Inter-IC Sound Controller */
1545static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1546{
1547    i2s->rx_len = 0;
1548    i2s->tx_len = 0;
1549    i2s->fifo_len = 0;
1550    i2s->clk = 0x1a;
1551    i2s->control[0] = 0x00;
1552    i2s->control[1] = 0x00;
1553    i2s->status = 0x00;
1554    i2s->mask = 0x00;
1555}
1556
1557#define SACR_TFTH(val)  ((val >> 8) & 0xf)
1558#define SACR_RFTH(val)  ((val >> 12) & 0xf)
1559#define SACR_DREC(val)  (val & (1 << 3))
1560#define SACR_DPRL(val)  (val & (1 << 4))
1561
1562static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1563{
1564    int rfs, tfs;
1565    rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1566            !SACR_DREC(i2s->control[1]);
1567    tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1568            i2s->enable && !SACR_DPRL(i2s->control[1]);
1569
1570    qemu_set_irq(i2s->rx_dma, rfs);
1571    qemu_set_irq(i2s->tx_dma, tfs);
1572
1573    i2s->status &= 0xe0;
1574    if (i2s->fifo_len < 16 || !i2s->enable)
1575        i2s->status |= 1 << 0;                  /* TNF */
1576    if (i2s->rx_len)
1577        i2s->status |= 1 << 1;                  /* RNE */
1578    if (i2s->enable)
1579        i2s->status |= 1 << 2;                  /* BSY */
1580    if (tfs)
1581        i2s->status |= 1 << 3;                  /* TFS */
1582    if (rfs)
1583        i2s->status |= 1 << 4;                  /* RFS */
1584    if (!(i2s->tx_len && i2s->enable))
1585        i2s->status |= i2s->fifo_len << 8;      /* TFL */
1586    i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1587
1588    qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1589}
1590
1591#define SACR0   0x00    /* Serial Audio Global Control register */
1592#define SACR1   0x04    /* Serial Audio I2S/MSB-Justified Control register */
1593#define SASR0   0x0c    /* Serial Audio Interface and FIFO Status register */
1594#define SAIMR   0x14    /* Serial Audio Interrupt Mask register */
1595#define SAICR   0x18    /* Serial Audio Interrupt Clear register */
1596#define SADIV   0x60    /* Serial Audio Clock Divider register */
1597#define SADR    0x80    /* Serial Audio Data register */
1598
1599static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
1600                                unsigned size)
1601{
1602    PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1603
1604    switch (addr) {
1605    case SACR0:
1606        return s->control[0];
1607    case SACR1:
1608        return s->control[1];
1609    case SASR0:
1610        return s->status;
1611    case SAIMR:
1612        return s->mask;
1613    case SAICR:
1614        return 0;
1615    case SADIV:
1616        return s->clk;
1617    case SADR:
1618        if (s->rx_len > 0) {
1619            s->rx_len --;
1620            pxa2xx_i2s_update(s);
1621            return s->codec_in(s->opaque);
1622        }
1623        return 0;
1624    default:
1625        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1626        break;
1627    }
1628    return 0;
1629}
1630
1631static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
1632                             uint64_t value, unsigned size)
1633{
1634    PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1635    uint32_t *sample;
1636
1637    switch (addr) {
1638    case SACR0:
1639        if (value & (1 << 3))                           /* RST */
1640            pxa2xx_i2s_reset(s);
1641        s->control[0] = value & 0xff3d;
1642        if (!s->enable && (value & 1) && s->tx_len) {   /* ENB */
1643            for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1644                s->codec_out(s->opaque, *sample);
1645            s->status &= ~(1 << 7);                     /* I2SOFF */
1646        }
1647        if (value & (1 << 4))                           /* EFWR */
1648            printf("%s: Attempt to use special function\n", __FUNCTION__);
1649        s->enable = (value & 9) == 1;                   /* ENB && !RST*/
1650        pxa2xx_i2s_update(s);
1651        break;
1652    case SACR1:
1653        s->control[1] = value & 0x0039;
1654        if (value & (1 << 5))                           /* ENLBF */
1655            printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1656        if (value & (1 << 4))                           /* DPRL */
1657            s->fifo_len = 0;
1658        pxa2xx_i2s_update(s);
1659        break;
1660    case SAIMR:
1661        s->mask = value & 0x0078;
1662        pxa2xx_i2s_update(s);
1663        break;
1664    case SAICR:
1665        s->status &= ~(value & (3 << 5));
1666        pxa2xx_i2s_update(s);
1667        break;
1668    case SADIV:
1669        s->clk = value & 0x007f;
1670        break;
1671    case SADR:
1672        if (s->tx_len && s->enable) {
1673            s->tx_len --;
1674            pxa2xx_i2s_update(s);
1675            s->codec_out(s->opaque, value);
1676        } else if (s->fifo_len < 16) {
1677            s->fifo[s->fifo_len ++] = value;
1678            pxa2xx_i2s_update(s);
1679        }
1680        break;
1681    default:
1682        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1683    }
1684}
1685
1686static const MemoryRegionOps pxa2xx_i2s_ops = {
1687    .read = pxa2xx_i2s_read,
1688    .write = pxa2xx_i2s_write,
1689    .endianness = DEVICE_NATIVE_ENDIAN,
1690};
1691
1692static const VMStateDescription vmstate_pxa2xx_i2s = {
1693    .name = "pxa2xx_i2s",
1694    .version_id = 0,
1695    .minimum_version_id = 0,
1696    .fields = (VMStateField[]) {
1697        VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1698        VMSTATE_UINT32(status, PXA2xxI2SState),
1699        VMSTATE_UINT32(mask, PXA2xxI2SState),
1700        VMSTATE_UINT32(clk, PXA2xxI2SState),
1701        VMSTATE_INT32(enable, PXA2xxI2SState),
1702        VMSTATE_INT32(rx_len, PXA2xxI2SState),
1703        VMSTATE_INT32(tx_len, PXA2xxI2SState),
1704        VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1705        VMSTATE_END_OF_LIST()
1706    }
1707};
1708
1709static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1710{
1711    PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1712    uint32_t *sample;
1713
1714    /* Signal FIFO errors */
1715    if (s->enable && s->tx_len)
1716        s->status |= 1 << 5;            /* TUR */
1717    if (s->enable && s->rx_len)
1718        s->status |= 1 << 6;            /* ROR */
1719
1720    /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1721     * handle the cases where it makes a difference.  */
1722    s->tx_len = tx - s->fifo_len;
1723    s->rx_len = rx;
1724    /* Note that is s->codec_out wasn't set, we wouldn't get called.  */
1725    if (s->enable)
1726        for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1727            s->codec_out(s->opaque, *sample);
1728    pxa2xx_i2s_update(s);
1729}
1730
1731static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1732                hwaddr base,
1733                qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1734{
1735    PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1);
1736
1737    s->irq = irq;
1738    s->rx_dma = rx_dma;
1739    s->tx_dma = tx_dma;
1740    s->data_req = pxa2xx_i2s_data_req;
1741
1742    pxa2xx_i2s_reset(s);
1743
1744    memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
1745                          "pxa2xx-i2s", 0x100000);
1746    memory_region_add_subregion(sysmem, base, &s->iomem);
1747
1748    vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1749
1750    return s;
1751}
1752
1753/* PXA Fast Infra-red Communications Port */
1754#define TYPE_PXA2XX_FIR "pxa2xx-fir"
1755#define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR)
1756
1757struct PXA2xxFIrState {
1758    /*< private >*/
1759    SysBusDevice parent_obj;
1760    /*< public >*/
1761
1762    MemoryRegion iomem;
1763    qemu_irq irq;
1764    qemu_irq rx_dma;
1765    qemu_irq tx_dma;
1766    uint32_t enable;
1767    CharBackend chr;
1768
1769    uint8_t control[3];
1770    uint8_t status[2];
1771
1772    uint32_t rx_len;
1773    uint32_t rx_start;
1774    uint8_t rx_fifo[64];
1775};
1776
1777static void pxa2xx_fir_reset(DeviceState *d)
1778{
1779    PXA2xxFIrState *s = PXA2XX_FIR(d);
1780
1781    s->control[0] = 0x00;
1782    s->control[1] = 0x00;
1783    s->control[2] = 0x00;
1784    s->status[0] = 0x00;
1785    s->status[1] = 0x00;
1786    s->enable = 0;
1787}
1788
1789static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1790{
1791    static const int tresh[4] = { 8, 16, 32, 0 };
1792    int intr = 0;
1793    if ((s->control[0] & (1 << 4)) &&                   /* RXE */
1794                    s->rx_len >= tresh[s->control[2] & 3])      /* TRIG */
1795        s->status[0] |= 1 << 4;                         /* RFS */
1796    else
1797        s->status[0] &= ~(1 << 4);                      /* RFS */
1798    if (s->control[0] & (1 << 3))                       /* TXE */
1799        s->status[0] |= 1 << 3;                         /* TFS */
1800    else
1801        s->status[0] &= ~(1 << 3);                      /* TFS */
1802    if (s->rx_len)
1803        s->status[1] |= 1 << 2;                         /* RNE */
1804    else
1805        s->status[1] &= ~(1 << 2);                      /* RNE */
1806    if (s->control[0] & (1 << 4))                       /* RXE */
1807        s->status[1] |= 1 << 0;                         /* RSY */
1808    else
1809        s->status[1] &= ~(1 << 0);                      /* RSY */
1810
1811    intr |= (s->control[0] & (1 << 5)) &&               /* RIE */
1812            (s->status[0] & (1 << 4));                  /* RFS */
1813    intr |= (s->control[0] & (1 << 6)) &&               /* TIE */
1814            (s->status[0] & (1 << 3));                  /* TFS */
1815    intr |= (s->control[2] & (1 << 4)) &&               /* TRAIL */
1816            (s->status[0] & (1 << 6));                  /* EOC */
1817    intr |= (s->control[0] & (1 << 2)) &&               /* TUS */
1818            (s->status[0] & (1 << 1));                  /* TUR */
1819    intr |= s->status[0] & 0x25;                        /* FRE, RAB, EIF */
1820
1821    qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1822    qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1823
1824    qemu_set_irq(s->irq, intr && s->enable);
1825}
1826
1827#define ICCR0   0x00    /* FICP Control register 0 */
1828#define ICCR1   0x04    /* FICP Control register 1 */
1829#define ICCR2   0x08    /* FICP Control register 2 */
1830#define ICDR    0x0c    /* FICP Data register */
1831#define ICSR0   0x14    /* FICP Status register 0 */
1832#define ICSR1   0x18    /* FICP Status register 1 */
1833#define ICFOR   0x1c    /* FICP FIFO Occupancy Status register */
1834
1835static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
1836                                unsigned size)
1837{
1838    PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1839    uint8_t ret;
1840
1841    switch (addr) {
1842    case ICCR0:
1843        return s->control[0];
1844    case ICCR1:
1845        return s->control[1];
1846    case ICCR2:
1847        return s->control[2];
1848    case ICDR:
1849        s->status[0] &= ~0x01;
1850        s->status[1] &= ~0x72;
1851        if (s->rx_len) {
1852            s->rx_len --;
1853            ret = s->rx_fifo[s->rx_start ++];
1854            s->rx_start &= 63;
1855            pxa2xx_fir_update(s);
1856            return ret;
1857        }
1858        printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1859        break;
1860    case ICSR0:
1861        return s->status[0];
1862    case ICSR1:
1863        return s->status[1] | (1 << 3);                 /* TNF */
1864    case ICFOR:
1865        return s->rx_len;
1866    default:
1867        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1868        break;
1869    }
1870    return 0;
1871}
1872
1873static void pxa2xx_fir_write(void *opaque, hwaddr addr,
1874                             uint64_t value64, unsigned size)
1875{
1876    PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1877    uint32_t value = value64;
1878    uint8_t ch;
1879
1880    switch (addr) {
1881    case ICCR0:
1882        s->control[0] = value;
1883        if (!(value & (1 << 4)))                        /* RXE */
1884            s->rx_len = s->rx_start = 0;
1885        if (!(value & (1 << 3))) {                      /* TXE */
1886            /* Nop */
1887        }
1888        s->enable = value & 1;                          /* ITR */
1889        if (!s->enable)
1890            s->status[0] = 0;
1891        pxa2xx_fir_update(s);
1892        break;
1893    case ICCR1:
1894        s->control[1] = value;
1895        break;
1896    case ICCR2:
1897        s->control[2] = value & 0x3f;
1898        pxa2xx_fir_update(s);
1899        break;
1900    case ICDR:
1901        if (s->control[2] & (1 << 2)) { /* TXP */
1902            ch = value;
1903        } else {
1904            ch = ~value;
1905        }
1906        if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */
1907            /* XXX this blocks entire thread. Rewrite to use
1908             * qemu_chr_fe_write and background I/O callbacks */
1909            qemu_chr_fe_write_all(&s->chr, &ch, 1);
1910        }
1911        break;
1912    case ICSR0:
1913        s->status[0] &= ~(value & 0x66);
1914        pxa2xx_fir_update(s);
1915        break;
1916    case ICFOR:
1917        break;
1918    default:
1919        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1920    }
1921}
1922
1923static const MemoryRegionOps pxa2xx_fir_ops = {
1924    .read = pxa2xx_fir_read,
1925    .write = pxa2xx_fir_write,
1926    .endianness = DEVICE_NATIVE_ENDIAN,
1927};
1928
1929static int pxa2xx_fir_is_empty(void *opaque)
1930{
1931    PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1932    return (s->rx_len < 64);
1933}
1934
1935static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1936{
1937    PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1938    if (!(s->control[0] & (1 << 4)))                    /* RXE */
1939        return;
1940
1941    while (size --) {
1942        s->status[1] |= 1 << 4;                         /* EOF */
1943        if (s->rx_len >= 64) {
1944            s->status[1] |= 1 << 6;                     /* ROR */
1945            break;
1946        }
1947
1948        if (s->control[2] & (1 << 3))                   /* RXP */
1949            s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1950        else
1951            s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1952    }
1953
1954    pxa2xx_fir_update(s);
1955}
1956
1957static void pxa2xx_fir_event(void *opaque, int event)
1958{
1959}
1960
1961static void pxa2xx_fir_instance_init(Object *obj)
1962{
1963    PXA2xxFIrState *s = PXA2XX_FIR(obj);
1964    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1965
1966    memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s,
1967                          "pxa2xx-fir", 0x1000);
1968    sysbus_init_mmio(sbd, &s->iomem);
1969    sysbus_init_irq(sbd, &s->irq);
1970    sysbus_init_irq(sbd, &s->rx_dma);
1971    sysbus_init_irq(sbd, &s->tx_dma);
1972}
1973
1974static void pxa2xx_fir_realize(DeviceState *dev, Error **errp)
1975{
1976    PXA2xxFIrState *s = PXA2XX_FIR(dev);
1977
1978    qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty,
1979                             pxa2xx_fir_rx, pxa2xx_fir_event, s, NULL, true);
1980}
1981
1982static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id)
1983{
1984    PXA2xxFIrState *s = opaque;
1985
1986    return s->rx_start < ARRAY_SIZE(s->rx_fifo);
1987}
1988
1989static const VMStateDescription pxa2xx_fir_vmsd = {
1990    .name = "pxa2xx-fir",
1991    .version_id = 1,
1992    .minimum_version_id = 1,
1993    .fields = (VMStateField[]) {
1994        VMSTATE_UINT32(enable, PXA2xxFIrState),
1995        VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3),
1996        VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2),
1997        VMSTATE_UINT32(rx_len, PXA2xxFIrState),
1998        VMSTATE_UINT32(rx_start, PXA2xxFIrState),
1999        VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate),
2000        VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64),
2001        VMSTATE_END_OF_LIST()
2002    }
2003};
2004
2005static Property pxa2xx_fir_properties[] = {
2006    DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr),
2007    DEFINE_PROP_END_OF_LIST(),
2008};
2009
2010static void pxa2xx_fir_class_init(ObjectClass *klass, void *data)
2011{
2012    DeviceClass *dc = DEVICE_CLASS(klass);
2013
2014    dc->realize = pxa2xx_fir_realize;
2015    dc->vmsd = &pxa2xx_fir_vmsd;
2016    dc->props = pxa2xx_fir_properties;
2017    dc->reset = pxa2xx_fir_reset;
2018}
2019
2020static const TypeInfo pxa2xx_fir_info = {
2021    .name = TYPE_PXA2XX_FIR,
2022    .parent = TYPE_SYS_BUS_DEVICE,
2023    .instance_size = sizeof(PXA2xxFIrState),
2024    .class_init = pxa2xx_fir_class_init,
2025    .instance_init = pxa2xx_fir_instance_init,
2026};
2027
2028static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
2029                                       hwaddr base,
2030                                       qemu_irq irq, qemu_irq rx_dma,
2031                                       qemu_irq tx_dma,
2032                                       CharDriverState *chr)
2033{
2034    DeviceState *dev;
2035    SysBusDevice *sbd;
2036
2037    dev = qdev_create(NULL, TYPE_PXA2XX_FIR);
2038    qdev_prop_set_chr(dev, "chardev", chr);
2039    qdev_init_nofail(dev);
2040    sbd = SYS_BUS_DEVICE(dev);
2041    sysbus_mmio_map(sbd, 0, base);
2042    sysbus_connect_irq(sbd, 0, irq);
2043    sysbus_connect_irq(sbd, 1, rx_dma);
2044    sysbus_connect_irq(sbd, 2, tx_dma);
2045    return PXA2XX_FIR(dev);
2046}
2047
2048static void pxa2xx_reset(void *opaque, int line, int level)
2049{
2050    PXA2xxState *s = (PXA2xxState *) opaque;
2051
2052    if (level && (s->pm_regs[PCFR >> 2] & 0x10)) {      /* GPR_EN */
2053        cpu_reset(CPU(s->cpu));
2054        /* TODO: reset peripherals */
2055    }
2056}
2057
2058/* Initialise a PXA270 integrated chip (ARM based core).  */
2059PXA2xxState *pxa270_init(MemoryRegion *address_space,
2060                         unsigned int sdram_size, const char *revision)
2061{
2062    PXA2xxState *s;
2063    int i;
2064    DriveInfo *dinfo;
2065    s = g_new0(PXA2xxState, 1);
2066
2067    if (revision && strncmp(revision, "pxa27", 5)) {
2068        fprintf(stderr, "Machine requires a PXA27x processor.\n");
2069        exit(1);
2070    }
2071    if (!revision)
2072        revision = "pxa270";
2073    
2074    s->cpu = cpu_arm_init(revision);
2075    if (s->cpu == NULL) {
2076        fprintf(stderr, "Unable to find CPU definition\n");
2077        exit(1);
2078    }
2079    s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2080
2081    /* SDRAM & Internal Memory Storage */
2082    memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size,
2083                           &error_fatal);
2084    vmstate_register_ram_global(&s->sdram);
2085    memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2086    memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000,
2087                           &error_fatal);
2088    vmstate_register_ram_global(&s->internal);
2089    memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2090                                &s->internal);
2091
2092    s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2093
2094    s->dma = pxa27x_dma_init(0x40000000,
2095                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2096
2097    sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2098                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2099                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2100                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2101                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2102                    qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2103                    NULL);
2104
2105    s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121);
2106
2107    dinfo = drive_get(IF_SD, 0, 0);
2108    if (!dinfo) {
2109        fprintf(stderr, "qemu: missing SecureDigital device\n");
2110        exit(1);
2111    }
2112    s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2113                    blk_by_legacy_dinfo(dinfo),
2114                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2115                    qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2116                    qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2117
2118    for (i = 0; pxa270_serial[i].io_base; i++) {
2119        if (serial_hds[i]) {
2120            serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2121                           qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2122                           14857000 / 16, serial_hds[i],
2123                           DEVICE_NATIVE_ENDIAN);
2124        } else {
2125            break;
2126        }
2127    }
2128    if (serial_hds[i])
2129        s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2130                        qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2131                        qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2132                        qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2133                        serial_hds[i]);
2134
2135    s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2136                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2137
2138    s->cm_base = 0x41300000;
2139    s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2140    s->clkcfg = 0x00000009;             /* Turbo mode active */
2141    memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2142    memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2143    vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2144
2145    pxa2xx_setup_cp14(s);
2146
2147    s->mm_base = 0x48000000;
2148    s->mm_regs[MDMRS >> 2] = 0x00020002;
2149    s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2150    s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2151    memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2152    memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2153    vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2154
2155    s->pm_base = 0x40f00000;
2156    memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2157    memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2158    vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2159
2160    for (i = 0; pxa27x_ssp[i].io_base; i ++);
2161    s->ssp = g_new0(SSIBus *, i);
2162    for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2163        DeviceState *dev;
2164        dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base,
2165                        qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2166        s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2167    }
2168
2169    sysbus_create_simple("sysbus-ohci", 0x4c000000,
2170                         qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2171
2172    s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2173    s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2174
2175    sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2176                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2177
2178    s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2179                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2180    s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2181                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2182
2183    s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2184                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2185                    qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2186                    qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2187
2188    s->kp = pxa27x_keypad_init(address_space, 0x41500000,
2189                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2190
2191    /* GPIO1 resets the processor */
2192    /* The handler can be overridden by board-specific code */
2193    qdev_connect_gpio_out(s->gpio, 1, s->reset);
2194    return s;
2195}
2196
2197/* Initialise a PXA255 integrated chip (ARM based core).  */
2198PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2199{
2200    PXA2xxState *s;
2201    int i;
2202    DriveInfo *dinfo;
2203
2204    s = g_new0(PXA2xxState, 1);
2205
2206    s->cpu = cpu_arm_init("pxa255");
2207    if (s->cpu == NULL) {
2208        fprintf(stderr, "Unable to find CPU definition\n");
2209        exit(1);
2210    }
2211    s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2212
2213    /* SDRAM & Internal Memory Storage */
2214    memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size,
2215                           &error_fatal);
2216    vmstate_register_ram_global(&s->sdram);
2217    memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2218    memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2219                           PXA2XX_INTERNAL_SIZE, &error_fatal);
2220    vmstate_register_ram_global(&s->internal);
2221    memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2222                                &s->internal);
2223
2224    s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2225
2226    s->dma = pxa255_dma_init(0x40000000,
2227                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2228
2229    sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2230                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2231                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2232                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2233                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2234                    NULL);
2235
2236    s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85);
2237
2238    dinfo = drive_get(IF_SD, 0, 0);
2239    if (!dinfo) {
2240        fprintf(stderr, "qemu: missing SecureDigital device\n");
2241        exit(1);
2242    }
2243    s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2244                    blk_by_legacy_dinfo(dinfo),
2245                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2246                    qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2247                    qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2248
2249    for (i = 0; pxa255_serial[i].io_base; i++) {
2250        if (serial_hds[i]) {
2251            serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2252                           qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2253                           14745600 / 16, serial_hds[i],
2254                           DEVICE_NATIVE_ENDIAN);
2255        } else {
2256            break;
2257        }
2258    }
2259    if (serial_hds[i])
2260        s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2261                        qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2262                        qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2263                        qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2264                        serial_hds[i]);
2265
2266    s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2267                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2268
2269    s->cm_base = 0x41300000;
2270    s->cm_regs[CCCR >> 2] = 0x00000121;         /* from datasheet */
2271    s->cm_regs[CKEN >> 2] = 0x00017def;         /* from datasheet */
2272
2273    s->clkcfg = 0x00000009;             /* Turbo mode active */
2274    memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2275    memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2276    vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2277
2278    pxa2xx_setup_cp14(s);
2279
2280    s->mm_base = 0x48000000;
2281    s->mm_regs[MDMRS >> 2] = 0x00020002;
2282    s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2283    s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2284    memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2285    memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2286    vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2287
2288    s->pm_base = 0x40f00000;
2289    memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2290    memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2291    vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2292
2293    for (i = 0; pxa255_ssp[i].io_base; i ++);
2294    s->ssp = g_new0(SSIBus *, i);
2295    for (i = 0; pxa255_ssp[i].io_base; i ++) {
2296        DeviceState *dev;
2297        dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base,
2298                        qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2299        s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2300    }
2301
2302    sysbus_create_simple("sysbus-ohci", 0x4c000000,
2303                         qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2304
2305    s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2306    s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2307
2308    sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2309                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2310
2311    s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2312                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2313    s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2314                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2315
2316    s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2317                    qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2318                    qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2319                    qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2320
2321    /* GPIO1 resets the processor */
2322    /* The handler can be overridden by board-specific code */
2323    qdev_connect_gpio_out(s->gpio, 1, s->reset);
2324    return s;
2325}
2326
2327static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
2328{
2329    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
2330    DeviceClass *dc = DEVICE_CLASS(klass);
2331
2332    sdc->init = pxa2xx_ssp_init;
2333    dc->reset = pxa2xx_ssp_reset;
2334    dc->vmsd = &vmstate_pxa2xx_ssp;
2335}
2336
2337static const TypeInfo pxa2xx_ssp_info = {
2338    .name          = TYPE_PXA2XX_SSP,
2339    .parent        = TYPE_SYS_BUS_DEVICE,
2340    .instance_size = sizeof(PXA2xxSSPState),
2341    .class_init    = pxa2xx_ssp_class_init,
2342};
2343
2344static void pxa2xx_register_types(void)
2345{
2346    type_register_static(&pxa2xx_i2c_slave_info);
2347    type_register_static(&pxa2xx_ssp_info);
2348    type_register_static(&pxa2xx_i2c_info);
2349    type_register_static(&pxa2xx_rtc_sysbus_info);
2350    type_register_static(&pxa2xx_fir_info);
2351}
2352
2353type_init(pxa2xx_register_types)
2354