qemu/hw/char/milkymist-uart.c
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   1/*
   2 *  QEMU model of the Milkymist UART block.
   3 *
   4 *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 *
  19 *
  20 * Specification available at:
  21 *   http://milkymist.walle.cc/socdoc/uart.pdf
  22 */
  23
  24#include "qemu/osdep.h"
  25#include "hw/hw.h"
  26#include "hw/sysbus.h"
  27#include "trace.h"
  28#include "sysemu/char.h"
  29#include "qemu/error-report.h"
  30
  31enum {
  32    R_RXTX = 0,
  33    R_DIV,
  34    R_STAT,
  35    R_CTRL,
  36    R_DBG,
  37    R_MAX
  38};
  39
  40enum {
  41    STAT_THRE   = (1<<0),
  42    STAT_RX_EVT = (1<<1),
  43    STAT_TX_EVT = (1<<2),
  44};
  45
  46enum {
  47    CTRL_RX_IRQ_EN = (1<<0),
  48    CTRL_TX_IRQ_EN = (1<<1),
  49    CTRL_THRU_EN   = (1<<2),
  50};
  51
  52enum {
  53    DBG_BREAK_EN = (1<<0),
  54};
  55
  56#define TYPE_MILKYMIST_UART "milkymist-uart"
  57#define MILKYMIST_UART(obj) \
  58    OBJECT_CHECK(MilkymistUartState, (obj), TYPE_MILKYMIST_UART)
  59
  60struct MilkymistUartState {
  61    SysBusDevice parent_obj;
  62
  63    MemoryRegion regs_region;
  64    CharBackend chr;
  65    qemu_irq irq;
  66
  67    uint32_t regs[R_MAX];
  68};
  69typedef struct MilkymistUartState MilkymistUartState;
  70
  71static void uart_update_irq(MilkymistUartState *s)
  72{
  73    int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
  74    int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
  75    int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
  76    int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
  77
  78    if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
  79        trace_milkymist_uart_raise_irq();
  80        qemu_irq_raise(s->irq);
  81    } else {
  82        trace_milkymist_uart_lower_irq();
  83        qemu_irq_lower(s->irq);
  84    }
  85}
  86
  87static uint64_t uart_read(void *opaque, hwaddr addr,
  88                          unsigned size)
  89{
  90    MilkymistUartState *s = opaque;
  91    uint32_t r = 0;
  92
  93    addr >>= 2;
  94    switch (addr) {
  95    case R_RXTX:
  96        r = s->regs[addr];
  97        break;
  98    case R_DIV:
  99    case R_STAT:
 100    case R_CTRL:
 101    case R_DBG:
 102        r = s->regs[addr];
 103        break;
 104
 105    default:
 106        error_report("milkymist_uart: read access to unknown register 0x"
 107                TARGET_FMT_plx, addr << 2);
 108        break;
 109    }
 110
 111    trace_milkymist_uart_memory_read(addr << 2, r);
 112
 113    return r;
 114}
 115
 116static void uart_write(void *opaque, hwaddr addr, uint64_t value,
 117                       unsigned size)
 118{
 119    MilkymistUartState *s = opaque;
 120    unsigned char ch = value;
 121
 122    trace_milkymist_uart_memory_write(addr, value);
 123
 124    addr >>= 2;
 125    switch (addr) {
 126    case R_RXTX:
 127        qemu_chr_fe_write_all(&s->chr, &ch, 1);
 128        s->regs[R_STAT] |= STAT_TX_EVT;
 129        break;
 130    case R_DIV:
 131    case R_CTRL:
 132    case R_DBG:
 133        s->regs[addr] = value;
 134        break;
 135
 136    case R_STAT:
 137        /* write one to clear bits */
 138        s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
 139        qemu_chr_fe_accept_input(&s->chr);
 140        break;
 141
 142    default:
 143        error_report("milkymist_uart: write access to unknown register 0x"
 144                TARGET_FMT_plx, addr << 2);
 145        break;
 146    }
 147
 148    uart_update_irq(s);
 149}
 150
 151static const MemoryRegionOps uart_mmio_ops = {
 152    .read = uart_read,
 153    .write = uart_write,
 154    .valid = {
 155        .min_access_size = 4,
 156        .max_access_size = 4,
 157    },
 158    .endianness = DEVICE_NATIVE_ENDIAN,
 159};
 160
 161static void uart_rx(void *opaque, const uint8_t *buf, int size)
 162{
 163    MilkymistUartState *s = opaque;
 164
 165    assert(!(s->regs[R_STAT] & STAT_RX_EVT));
 166
 167    s->regs[R_STAT] |= STAT_RX_EVT;
 168    s->regs[R_RXTX] = *buf;
 169
 170    uart_update_irq(s);
 171}
 172
 173static int uart_can_rx(void *opaque)
 174{
 175    MilkymistUartState *s = opaque;
 176
 177    return !(s->regs[R_STAT] & STAT_RX_EVT);
 178}
 179
 180static void uart_event(void *opaque, int event)
 181{
 182}
 183
 184static void milkymist_uart_reset(DeviceState *d)
 185{
 186    MilkymistUartState *s = MILKYMIST_UART(d);
 187    int i;
 188
 189    for (i = 0; i < R_MAX; i++) {
 190        s->regs[i] = 0;
 191    }
 192
 193    /* THRE is always set */
 194    s->regs[R_STAT] = STAT_THRE;
 195}
 196
 197static void milkymist_uart_realize(DeviceState *dev, Error **errp)
 198{
 199    MilkymistUartState *s = MILKYMIST_UART(dev);
 200
 201    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
 202                             uart_event, s, NULL, true);
 203}
 204
 205static void milkymist_uart_init(Object *obj)
 206{
 207    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 208    MilkymistUartState *s = MILKYMIST_UART(obj);
 209
 210    sysbus_init_irq(sbd, &s->irq);
 211
 212    memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
 213                          "milkymist-uart", R_MAX * 4);
 214    sysbus_init_mmio(sbd, &s->regs_region);
 215}
 216
 217static const VMStateDescription vmstate_milkymist_uart = {
 218    .name = "milkymist-uart",
 219    .version_id = 1,
 220    .minimum_version_id = 1,
 221    .fields = (VMStateField[]) {
 222        VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
 223        VMSTATE_END_OF_LIST()
 224    }
 225};
 226
 227static Property milkymist_uart_properties[] = {
 228    DEFINE_PROP_CHR("chardev", MilkymistUartState, chr),
 229    DEFINE_PROP_END_OF_LIST(),
 230};
 231
 232static void milkymist_uart_class_init(ObjectClass *klass, void *data)
 233{
 234    DeviceClass *dc = DEVICE_CLASS(klass);
 235
 236    dc->realize = milkymist_uart_realize;
 237    dc->reset = milkymist_uart_reset;
 238    dc->vmsd = &vmstate_milkymist_uart;
 239    dc->props = milkymist_uart_properties;
 240}
 241
 242static const TypeInfo milkymist_uart_info = {
 243    .name          = TYPE_MILKYMIST_UART,
 244    .parent        = TYPE_SYS_BUS_DEVICE,
 245    .instance_size = sizeof(MilkymistUartState),
 246    .instance_init = milkymist_uart_init,
 247    .class_init    = milkymist_uart_class_init,
 248};
 249
 250static void milkymist_uart_register_types(void)
 251{
 252    type_register_static(&milkymist_uart_info);
 253}
 254
 255type_init(milkymist_uart_register_types)
 256