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12#include "qemu/osdep.h"
13#include "qemu-common.h"
14#include "cpu.h"
15#include "hw/i386/apic_internal.h"
16#include "hw/pci/msi.h"
17#include "sysemu/kvm.h"
18#include "target-i386/kvm_i386.h"
19
20static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,
21 int reg_id, uint32_t val)
22{
23 *((uint32_t *)(kapic->regs + (reg_id << 4))) = val;
24}
25
26static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic,
27 int reg_id)
28{
29 return *((uint32_t *)(kapic->regs + (reg_id << 4)));
30}
31
32static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic)
33{
34 int i;
35
36 memset(kapic, 0, sizeof(*kapic));
37 if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) {
38 kvm_apic_set_reg(kapic, 0x2, s->initial_apic_id);
39 } else {
40 kvm_apic_set_reg(kapic, 0x2, s->id << 24);
41 }
42 kvm_apic_set_reg(kapic, 0x8, s->tpr);
43 kvm_apic_set_reg(kapic, 0xd, s->log_dest << 24);
44 kvm_apic_set_reg(kapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
45 kvm_apic_set_reg(kapic, 0xf, s->spurious_vec);
46 for (i = 0; i < 8; i++) {
47 kvm_apic_set_reg(kapic, 0x10 + i, s->isr[i]);
48 kvm_apic_set_reg(kapic, 0x18 + i, s->tmr[i]);
49 kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]);
50 }
51 kvm_apic_set_reg(kapic, 0x28, s->esr);
52 kvm_apic_set_reg(kapic, 0x30, s->icr[0]);
53 kvm_apic_set_reg(kapic, 0x31, s->icr[1]);
54 for (i = 0; i < APIC_LVT_NB; i++) {
55 kvm_apic_set_reg(kapic, 0x32 + i, s->lvt[i]);
56 }
57 kvm_apic_set_reg(kapic, 0x38, s->initial_count);
58 kvm_apic_set_reg(kapic, 0x3e, s->divide_conf);
59}
60
61void kvm_get_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic)
62{
63 APICCommonState *s = APIC_COMMON(dev);
64 int i, v;
65
66 if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) {
67 assert(kvm_apic_get_reg(kapic, 0x2) == s->initial_apic_id);
68 } else {
69 s->id = kvm_apic_get_reg(kapic, 0x2) >> 24;
70 }
71 s->tpr = kvm_apic_get_reg(kapic, 0x8);
72 s->arb_id = kvm_apic_get_reg(kapic, 0x9);
73 s->log_dest = kvm_apic_get_reg(kapic, 0xd) >> 24;
74 s->dest_mode = kvm_apic_get_reg(kapic, 0xe) >> 28;
75 s->spurious_vec = kvm_apic_get_reg(kapic, 0xf);
76 for (i = 0; i < 8; i++) {
77 s->isr[i] = kvm_apic_get_reg(kapic, 0x10 + i);
78 s->tmr[i] = kvm_apic_get_reg(kapic, 0x18 + i);
79 s->irr[i] = kvm_apic_get_reg(kapic, 0x20 + i);
80 }
81 s->esr = kvm_apic_get_reg(kapic, 0x28);
82 s->icr[0] = kvm_apic_get_reg(kapic, 0x30);
83 s->icr[1] = kvm_apic_get_reg(kapic, 0x31);
84 for (i = 0; i < APIC_LVT_NB; i++) {
85 s->lvt[i] = kvm_apic_get_reg(kapic, 0x32 + i);
86 }
87 s->initial_count = kvm_apic_get_reg(kapic, 0x38);
88 s->divide_conf = kvm_apic_get_reg(kapic, 0x3e);
89
90 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
91 s->count_shift = (v + 1) & 7;
92
93 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
94 apic_next_timer(s, s->initial_count_load_time);
95}
96
97static void kvm_apic_set_base(APICCommonState *s, uint64_t val)
98{
99 s->apicbase = val;
100}
101
102static void kvm_apic_set_tpr(APICCommonState *s, uint8_t val)
103{
104 s->tpr = (val & 0x0f) << 4;
105}
106
107static uint8_t kvm_apic_get_tpr(APICCommonState *s)
108{
109 return s->tpr >> 4;
110}
111
112static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable)
113{
114 struct kvm_tpr_access_ctl ctl = {
115 .enabled = enable
116 };
117
118 kvm_vcpu_ioctl(CPU(s->cpu), KVM_TPR_ACCESS_REPORTING, &ctl);
119}
120
121static void kvm_apic_vapic_base_update(APICCommonState *s)
122{
123 struct kvm_vapic_addr vapid_addr = {
124 .vapic_addr = s->vapic_paddr,
125 };
126 int ret;
127
128 ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_VAPIC_ADDR, &vapid_addr);
129 if (ret < 0) {
130 fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n",
131 strerror(-ret));
132 abort();
133 }
134}
135
136static void kvm_apic_put(CPUState *cs, run_on_cpu_data data)
137{
138 APICCommonState *s = data.host_ptr;
139 struct kvm_lapic_state kapic;
140 int ret;
141
142 kvm_put_apicbase(s->cpu, s->apicbase);
143 kvm_put_apic_state(s, &kapic);
144
145 ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_LAPIC, &kapic);
146 if (ret < 0) {
147 fprintf(stderr, "KVM_SET_LAPIC failed: %s\n", strerror(ret));
148 abort();
149 }
150}
151
152static void kvm_apic_post_load(APICCommonState *s)
153{
154 run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s));
155}
156
157static void do_inject_external_nmi(CPUState *cpu, run_on_cpu_data data)
158{
159 APICCommonState *s = data.host_ptr;
160 uint32_t lvt;
161 int ret;
162
163 cpu_synchronize_state(cpu);
164
165 lvt = s->lvt[APIC_LVT_LINT1];
166 if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) {
167 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
168 if (ret < 0) {
169 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
170 strerror(-ret));
171 }
172 }
173}
174
175static void kvm_apic_external_nmi(APICCommonState *s)
176{
177 run_on_cpu(CPU(s->cpu), do_inject_external_nmi, RUN_ON_CPU_HOST_PTR(s));
178}
179
180static void kvm_send_msi(MSIMessage *msg)
181{
182 int ret;
183
184 ret = kvm_irqchip_send_msi(kvm_state, *msg);
185 if (ret < 0) {
186 fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n",
187 strerror(-ret));
188 }
189}
190
191static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr,
192 unsigned size)
193{
194 return ~(uint64_t)0;
195}
196
197static void kvm_apic_mem_write(void *opaque, hwaddr addr,
198 uint64_t data, unsigned size)
199{
200 MSIMessage msg = { .address = addr, .data = data };
201
202 kvm_send_msi(&msg);
203}
204
205static const MemoryRegionOps kvm_apic_io_ops = {
206 .read = kvm_apic_mem_read,
207 .write = kvm_apic_mem_write,
208 .endianness = DEVICE_NATIVE_ENDIAN,
209};
210
211static void kvm_apic_reset(APICCommonState *s)
212{
213
214 s->wait_for_sipi = 0;
215
216 run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s));
217}
218
219static void kvm_apic_realize(DeviceState *dev, Error **errp)
220{
221 APICCommonState *s = APIC_COMMON(dev);
222
223 memory_region_init_io(&s->io_memory, OBJECT(s), &kvm_apic_io_ops, s,
224 "kvm-apic-msi", APIC_SPACE_SIZE);
225
226 if (kvm_has_gsi_routing()) {
227 msi_nonbroken = true;
228 }
229}
230
231static void kvm_apic_unrealize(DeviceState *dev, Error **errp)
232{
233}
234
235static void kvm_apic_class_init(ObjectClass *klass, void *data)
236{
237 APICCommonClass *k = APIC_COMMON_CLASS(klass);
238
239 k->realize = kvm_apic_realize;
240 k->unrealize = kvm_apic_unrealize;
241 k->reset = kvm_apic_reset;
242 k->set_base = kvm_apic_set_base;
243 k->set_tpr = kvm_apic_set_tpr;
244 k->get_tpr = kvm_apic_get_tpr;
245 k->post_load = kvm_apic_post_load;
246 k->enable_tpr_reporting = kvm_apic_enable_tpr_reporting;
247 k->vapic_base_update = kvm_apic_vapic_base_update;
248 k->external_nmi = kvm_apic_external_nmi;
249 k->send_msi = kvm_send_msi;
250}
251
252static const TypeInfo kvm_apic_info = {
253 .name = "kvm-apic",
254 .parent = TYPE_APIC_COMMON,
255 .instance_size = sizeof(APICCommonState),
256 .class_init = kvm_apic_class_init,
257};
258
259static void kvm_apic_register_types(void)
260{
261 type_register_static(&kvm_apic_info);
262}
263
264type_init(kvm_apic_register_types)
265
