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24#include "qemu/osdep.h"
25#include "hw/hw.h"
26#include "hw/i386/pc.h"
27#include "hw/char/serial.h"
28#include "hw/i386/apic.h"
29#include "hw/i386/topology.h"
30#include "sysemu/cpus.h"
31#include "hw/block/fdc.h"
32#include "hw/ide.h"
33#include "hw/pci/pci.h"
34#include "hw/pci/pci_bus.h"
35#include "hw/nvram/fw_cfg.h"
36#include "hw/timer/hpet.h"
37#include "hw/smbios/smbios.h"
38#include "hw/loader.h"
39#include "elf.h"
40#include "multiboot.h"
41#include "hw/timer/mc146818rtc.h"
42#include "hw/timer/i8254.h"
43#include "hw/audio/pcspk.h"
44#include "hw/pci/msi.h"
45#include "hw/sysbus.h"
46#include "sysemu/sysemu.h"
47#include "sysemu/numa.h"
48#include "sysemu/kvm.h"
49#include "sysemu/qtest.h"
50#include "kvm_i386.h"
51#include "hw/xen/xen.h"
52#include "sysemu/block-backend.h"
53#include "hw/block/block.h"
54#include "ui/qemu-spice.h"
55#include "exec/memory.h"
56#include "exec/address-spaces.h"
57#include "sysemu/arch_init.h"
58#include "qemu/bitmap.h"
59#include "qemu/config-file.h"
60#include "qemu/error-report.h"
61#include "hw/acpi/acpi.h"
62#include "hw/acpi/cpu_hotplug.h"
63#include "hw/boards.h"
64#include "hw/pci/pci_host.h"
65#include "acpi-build.h"
66#include "hw/mem/pc-dimm.h"
67#include "qapi/visitor.h"
68#include "qapi-visit.h"
69#include "qom/cpu.h"
70#include "hw/nmi.h"
71#include "hw/i386/intel_iommu.h"
72
73
74
75
76#ifdef DEBUG_IRQ
77#define DPRINTF(fmt, ...) \
78 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
79#else
80#define DPRINTF(fmt, ...)
81#endif
82
83#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
84#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
85#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
86#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
87#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
88
89#define E820_NR_ENTRIES 16
90
91struct e820_entry {
92 uint64_t address;
93 uint64_t length;
94 uint32_t type;
95} QEMU_PACKED __attribute((__aligned__(4)));
96
97struct e820_table {
98 uint32_t count;
99 struct e820_entry entry[E820_NR_ENTRIES];
100} QEMU_PACKED __attribute((__aligned__(4)));
101
102static struct e820_table e820_reserve;
103static struct e820_entry *e820_table;
104static unsigned e820_entries;
105struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
106
107void gsi_handler(void *opaque, int n, int level)
108{
109 GSIState *s = opaque;
110
111 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
112 if (n < ISA_NUM_IRQS) {
113 qemu_set_irq(s->i8259_irq[n], level);
114 }
115 qemu_set_irq(s->ioapic_irq[n], level);
116}
117
118static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
119 unsigned size)
120{
121}
122
123static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
124{
125 return 0xffffffffffffffffULL;
126}
127
128
129static qemu_irq ferr_irq;
130
131void pc_register_ferr_irq(qemu_irq irq)
132{
133 ferr_irq = irq;
134}
135
136
137void cpu_set_ferr(CPUX86State *s)
138{
139 qemu_irq_raise(ferr_irq);
140}
141
142static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
143 unsigned size)
144{
145 qemu_irq_lower(ferr_irq);
146}
147
148static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
149{
150 return 0xffffffffffffffffULL;
151}
152
153
154uint64_t cpu_get_tsc(CPUX86State *env)
155{
156 return cpu_get_ticks();
157}
158
159
160int cpu_get_pic_interrupt(CPUX86State *env)
161{
162 X86CPU *cpu = x86_env_get_cpu(env);
163 int intno;
164
165 if (!kvm_irqchip_in_kernel()) {
166 intno = apic_get_interrupt(cpu->apic_state);
167 if (intno >= 0) {
168 return intno;
169 }
170
171 if (!apic_accept_pic_intr(cpu->apic_state)) {
172 return -1;
173 }
174 }
175
176 intno = pic_read_irq(isa_pic);
177 return intno;
178}
179
180static void pic_irq_request(void *opaque, int irq, int level)
181{
182 CPUState *cs = first_cpu;
183 X86CPU *cpu = X86_CPU(cs);
184
185 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
186 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
187 CPU_FOREACH(cs) {
188 cpu = X86_CPU(cs);
189 if (apic_accept_pic_intr(cpu->apic_state)) {
190 apic_deliver_pic_intr(cpu->apic_state, level);
191 }
192 }
193 } else {
194 if (level) {
195 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
196 } else {
197 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
198 }
199 }
200}
201
202
203
204#define REG_EQUIPMENT_BYTE 0x14
205
206int cmos_get_fd_drive_type(FloppyDriveType fd0)
207{
208 int val;
209
210 switch (fd0) {
211 case FLOPPY_DRIVE_TYPE_144:
212
213 val = 4;
214 break;
215 case FLOPPY_DRIVE_TYPE_288:
216
217 val = 5;
218 break;
219 case FLOPPY_DRIVE_TYPE_120:
220
221 val = 2;
222 break;
223 case FLOPPY_DRIVE_TYPE_NONE:
224 default:
225 val = 0;
226 break;
227 }
228 return val;
229}
230
231static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
232 int16_t cylinders, int8_t heads, int8_t sectors)
233{
234 rtc_set_memory(s, type_ofs, 47);
235 rtc_set_memory(s, info_ofs, cylinders);
236 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
237 rtc_set_memory(s, info_ofs + 2, heads);
238 rtc_set_memory(s, info_ofs + 3, 0xff);
239 rtc_set_memory(s, info_ofs + 4, 0xff);
240 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
241 rtc_set_memory(s, info_ofs + 6, cylinders);
242 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
243 rtc_set_memory(s, info_ofs + 8, sectors);
244}
245
246
247static int boot_device2nibble(char boot_device)
248{
249 switch(boot_device) {
250 case 'a':
251 case 'b':
252 return 0x01;
253 case 'c':
254 return 0x02;
255 case 'd':
256 return 0x03;
257 case 'n':
258 return 0x04;
259 }
260 return 0;
261}
262
263static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
264{
265#define PC_MAX_BOOT_DEVICES 3
266 int nbds, bds[3] = { 0, };
267 int i;
268
269 nbds = strlen(boot_device);
270 if (nbds > PC_MAX_BOOT_DEVICES) {
271 error_setg(errp, "Too many boot devices for PC");
272 return;
273 }
274 for (i = 0; i < nbds; i++) {
275 bds[i] = boot_device2nibble(boot_device[i]);
276 if (bds[i] == 0) {
277 error_setg(errp, "Invalid boot device for PC: '%c'",
278 boot_device[i]);
279 return;
280 }
281 }
282 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
283 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
284}
285
286static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
287{
288 set_boot_dev(opaque, boot_device, errp);
289}
290
291static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
292{
293 int val, nb, i;
294 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
295 FLOPPY_DRIVE_TYPE_NONE };
296
297
298 if (floppy) {
299 for (i = 0; i < 2; i++) {
300 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
301 }
302 }
303 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
304 cmos_get_fd_drive_type(fd_type[1]);
305 rtc_set_memory(rtc_state, 0x10, val);
306
307 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
308 nb = 0;
309 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
310 nb++;
311 }
312 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
313 nb++;
314 }
315 switch (nb) {
316 case 0:
317 break;
318 case 1:
319 val |= 0x01;
320 break;
321 case 2:
322 val |= 0x41;
323 break;
324 }
325 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
326}
327
328typedef struct pc_cmos_init_late_arg {
329 ISADevice *rtc_state;
330 BusState *idebus[2];
331} pc_cmos_init_late_arg;
332
333typedef struct check_fdc_state {
334 ISADevice *floppy;
335 bool multiple;
336} CheckFdcState;
337
338static int check_fdc(Object *obj, void *opaque)
339{
340 CheckFdcState *state = opaque;
341 Object *fdc;
342 uint32_t iobase;
343 Error *local_err = NULL;
344
345 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
346 if (!fdc) {
347 return 0;
348 }
349
350 iobase = object_property_get_int(obj, "iobase", &local_err);
351 if (local_err || iobase != 0x3f0) {
352 error_free(local_err);
353 return 0;
354 }
355
356 if (state->floppy) {
357 state->multiple = true;
358 } else {
359 state->floppy = ISA_DEVICE(obj);
360 }
361 return 0;
362}
363
364static const char * const fdc_container_path[] = {
365 "/unattached", "/peripheral", "/peripheral-anon"
366};
367
368
369
370
371
372ISADevice *pc_find_fdc0(void)
373{
374 int i;
375 Object *container;
376 CheckFdcState state = { 0 };
377
378 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
379 container = container_get(qdev_get_machine(), fdc_container_path[i]);
380 object_child_foreach(container, check_fdc, &state);
381 }
382
383 if (state.multiple) {
384 error_report("warning: multiple floppy disk controllers with "
385 "iobase=0x3f0 have been found");
386 error_printf("the one being picked for CMOS setup might not reflect "
387 "your intent\n");
388 }
389
390 return state.floppy;
391}
392
393static void pc_cmos_init_late(void *opaque)
394{
395 pc_cmos_init_late_arg *arg = opaque;
396 ISADevice *s = arg->rtc_state;
397 int16_t cylinders;
398 int8_t heads, sectors;
399 int val;
400 int i, trans;
401
402 val = 0;
403 if (ide_get_geometry(arg->idebus[0], 0,
404 &cylinders, &heads, §ors) >= 0) {
405 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
406 val |= 0xf0;
407 }
408 if (ide_get_geometry(arg->idebus[0], 1,
409 &cylinders, &heads, §ors) >= 0) {
410 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
411 val |= 0x0f;
412 }
413 rtc_set_memory(s, 0x12, val);
414
415 val = 0;
416 for (i = 0; i < 4; i++) {
417
418
419
420
421 if (ide_get_geometry(arg->idebus[i / 2], i % 2,
422 &cylinders, &heads, §ors) >= 0) {
423 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
424 assert((trans & ~3) == 0);
425 val |= trans << (i * 2);
426 }
427 }
428 rtc_set_memory(s, 0x39, val);
429
430 pc_cmos_init_floppy(s, pc_find_fdc0());
431
432 qemu_unregister_reset(pc_cmos_init_late, opaque);
433}
434
435void pc_cmos_init(PCMachineState *pcms,
436 BusState *idebus0, BusState *idebus1,
437 ISADevice *s)
438{
439 int val;
440 static pc_cmos_init_late_arg arg;
441
442
443
444
445
446 val = MIN(pcms->below_4g_mem_size / 1024, 640);
447 rtc_set_memory(s, 0x15, val);
448 rtc_set_memory(s, 0x16, val >> 8);
449
450 if (pcms->below_4g_mem_size > 1024 * 1024) {
451 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024;
452 } else {
453 val = 0;
454 }
455 if (val > 65535)
456 val = 65535;
457 rtc_set_memory(s, 0x17, val);
458 rtc_set_memory(s, 0x18, val >> 8);
459 rtc_set_memory(s, 0x30, val);
460 rtc_set_memory(s, 0x31, val >> 8);
461
462 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) {
463 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536;
464 } else {
465 val = 0;
466 }
467 if (val > 65535)
468 val = 65535;
469 rtc_set_memory(s, 0x34, val);
470 rtc_set_memory(s, 0x35, val >> 8);
471
472 val = pcms->above_4g_mem_size / 65536;
473 rtc_set_memory(s, 0x5b, val);
474 rtc_set_memory(s, 0x5c, val >> 8);
475 rtc_set_memory(s, 0x5d, val >> 16);
476
477 object_property_add_link(OBJECT(pcms), "rtc_state",
478 TYPE_ISA_DEVICE,
479 (Object **)&pcms->rtc,
480 object_property_allow_set_link,
481 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
482 object_property_set_link(OBJECT(pcms), OBJECT(s),
483 "rtc_state", &error_abort);
484
485 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
486
487 val = 0;
488 val |= 0x02;
489 val |= 0x04;
490 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
491
492
493 arg.rtc_state = s;
494 arg.idebus[0] = idebus0;
495 arg.idebus[1] = idebus1;
496 qemu_register_reset(pc_cmos_init_late, &arg);
497}
498
499#define TYPE_PORT92 "port92"
500#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
501
502
503typedef struct Port92State {
504 ISADevice parent_obj;
505
506 MemoryRegion io;
507 uint8_t outport;
508 qemu_irq a20_out;
509} Port92State;
510
511static void port92_write(void *opaque, hwaddr addr, uint64_t val,
512 unsigned size)
513{
514 Port92State *s = opaque;
515 int oldval = s->outport;
516
517 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
518 s->outport = val;
519 qemu_set_irq(s->a20_out, (val >> 1) & 1);
520 if ((val & 1) && !(oldval & 1)) {
521 qemu_system_reset_request();
522 }
523}
524
525static uint64_t port92_read(void *opaque, hwaddr addr,
526 unsigned size)
527{
528 Port92State *s = opaque;
529 uint32_t ret;
530
531 ret = s->outport;
532 DPRINTF("port92: read 0x%02x\n", ret);
533 return ret;
534}
535
536static void port92_init(ISADevice *dev, qemu_irq a20_out)
537{
538 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
539}
540
541static const VMStateDescription vmstate_port92_isa = {
542 .name = "port92",
543 .version_id = 1,
544 .minimum_version_id = 1,
545 .fields = (VMStateField[]) {
546 VMSTATE_UINT8(outport, Port92State),
547 VMSTATE_END_OF_LIST()
548 }
549};
550
551static void port92_reset(DeviceState *d)
552{
553 Port92State *s = PORT92(d);
554
555 s->outport &= ~1;
556}
557
558static const MemoryRegionOps port92_ops = {
559 .read = port92_read,
560 .write = port92_write,
561 .impl = {
562 .min_access_size = 1,
563 .max_access_size = 1,
564 },
565 .endianness = DEVICE_LITTLE_ENDIAN,
566};
567
568static void port92_initfn(Object *obj)
569{
570 Port92State *s = PORT92(obj);
571
572 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
573
574 s->outport = 0;
575
576 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
577}
578
579static void port92_realizefn(DeviceState *dev, Error **errp)
580{
581 ISADevice *isadev = ISA_DEVICE(dev);
582 Port92State *s = PORT92(dev);
583
584 isa_register_ioport(isadev, &s->io, 0x92);
585}
586
587static void port92_class_initfn(ObjectClass *klass, void *data)
588{
589 DeviceClass *dc = DEVICE_CLASS(klass);
590
591 dc->realize = port92_realizefn;
592 dc->reset = port92_reset;
593 dc->vmsd = &vmstate_port92_isa;
594
595
596
597
598
599 dc->cannot_instantiate_with_device_add_yet = true;
600}
601
602static const TypeInfo port92_info = {
603 .name = TYPE_PORT92,
604 .parent = TYPE_ISA_DEVICE,
605 .instance_size = sizeof(Port92State),
606 .instance_init = port92_initfn,
607 .class_init = port92_class_initfn,
608};
609
610static void port92_register_types(void)
611{
612 type_register_static(&port92_info);
613}
614
615type_init(port92_register_types)
616
617static void handle_a20_line_change(void *opaque, int irq, int level)
618{
619 X86CPU *cpu = opaque;
620
621
622
623 x86_cpu_set_a20(cpu, level);
624}
625
626int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
627{
628 int index = le32_to_cpu(e820_reserve.count);
629 struct e820_entry *entry;
630
631 if (type != E820_RAM) {
632
633 if (index >= E820_NR_ENTRIES) {
634 return -EBUSY;
635 }
636 entry = &e820_reserve.entry[index++];
637
638 entry->address = cpu_to_le64(address);
639 entry->length = cpu_to_le64(length);
640 entry->type = cpu_to_le32(type);
641
642 e820_reserve.count = cpu_to_le32(index);
643 }
644
645
646 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
647 e820_table[e820_entries].address = cpu_to_le64(address);
648 e820_table[e820_entries].length = cpu_to_le64(length);
649 e820_table[e820_entries].type = cpu_to_le32(type);
650 e820_entries++;
651
652 return e820_entries;
653}
654
655int e820_get_num_entries(void)
656{
657 return e820_entries;
658}
659
660bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
661{
662 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
663 *address = le64_to_cpu(e820_table[idx].address);
664 *length = le64_to_cpu(e820_table[idx].length);
665 return true;
666 }
667 return false;
668}
669
670
671static bool compat_apic_id_mode;
672
673void enable_compat_apic_id_mode(void)
674{
675 compat_apic_id_mode = true;
676}
677
678
679
680
681
682
683
684
685static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
686{
687 uint32_t correct_id;
688 static bool warned;
689
690 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
691 if (compat_apic_id_mode) {
692 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
693 error_report("APIC IDs set in compatibility mode, "
694 "CPU topology won't match the configuration");
695 warned = true;
696 }
697 return cpu_index;
698 } else {
699 return correct_id;
700 }
701}
702
703static void pc_build_smbios(FWCfgState *fw_cfg)
704{
705 uint8_t *smbios_tables, *smbios_anchor;
706 size_t smbios_tables_len, smbios_anchor_len;
707 struct smbios_phys_mem_area *mem_array;
708 unsigned i, array_count;
709
710 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
711 if (smbios_tables) {
712 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
713 smbios_tables, smbios_tables_len);
714 }
715
716
717 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
718 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
719 uint64_t addr, len;
720
721 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
722 mem_array[array_count].address = addr;
723 mem_array[array_count].length = len;
724 array_count++;
725 }
726 }
727 smbios_get_tables(mem_array, array_count,
728 &smbios_tables, &smbios_tables_len,
729 &smbios_anchor, &smbios_anchor_len);
730 g_free(mem_array);
731
732 if (smbios_anchor) {
733 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
734 smbios_tables, smbios_tables_len);
735 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
736 smbios_anchor, smbios_anchor_len);
737 }
738}
739
740static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
741{
742 FWCfgState *fw_cfg;
743 uint64_t *numa_fw_cfg;
744 int i, j;
745
746 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
747 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
748
749
750
751
752
753
754
755
756
757
758
759
760
761 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
762 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
763 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
764 acpi_tables, acpi_tables_len);
765 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
766
767 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
768 &e820_reserve, sizeof(e820_reserve));
769 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
770 sizeof(struct e820_entry) * e820_entries);
771
772 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
773
774
775
776
777 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
778 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
779 for (i = 0; i < max_cpus; i++) {
780 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
781 assert(apic_id < pcms->apic_id_limit);
782 j = numa_get_node_for_cpu(i);
783 if (j < nb_numa_nodes) {
784 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
785 }
786 }
787 for (i = 0; i < nb_numa_nodes; i++) {
788 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
789 cpu_to_le64(numa_info[i].node_mem);
790 }
791 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
792 (1 + pcms->apic_id_limit + nb_numa_nodes) *
793 sizeof(*numa_fw_cfg));
794
795 return fw_cfg;
796}
797
798static long get_file_size(FILE *f)
799{
800 long where, size;
801
802
803
804 where = ftell(f);
805 fseek(f, 0, SEEK_END);
806 size = ftell(f);
807 fseek(f, where, SEEK_SET);
808
809 return size;
810}
811
812
813#define SETUP_NONE 0
814#define SETUP_E820_EXT 1
815#define SETUP_DTB 2
816#define SETUP_PCI 3
817#define SETUP_EFI 4
818
819struct setup_data {
820 uint64_t next;
821 uint32_t type;
822 uint32_t len;
823 uint8_t data[0];
824} __attribute__((packed));
825
826static void load_linux(PCMachineState *pcms,
827 FWCfgState *fw_cfg)
828{
829 uint16_t protocol;
830 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
831 int dtb_size, setup_data_offset;
832 uint32_t initrd_max;
833 uint8_t header[8192], *setup, *kernel, *initrd_data;
834 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
835 FILE *f;
836 char *vmode;
837 MachineState *machine = MACHINE(pcms);
838 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
839 struct setup_data *setup_data;
840 const char *kernel_filename = machine->kernel_filename;
841 const char *initrd_filename = machine->initrd_filename;
842 const char *dtb_filename = machine->dtb;
843 const char *kernel_cmdline = machine->kernel_cmdline;
844
845
846 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
847
848
849 f = fopen(kernel_filename, "rb");
850 if (!f || !(kernel_size = get_file_size(f)) ||
851 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
852 MIN(ARRAY_SIZE(header), kernel_size)) {
853 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
854 kernel_filename, strerror(errno));
855 exit(1);
856 }
857
858
859#if 0
860 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
861#endif
862 if (ldl_p(header+0x202) == 0x53726448) {
863 protocol = lduw_p(header+0x206);
864 } else {
865
866
867 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
868 kernel_cmdline, kernel_size, header)) {
869 return;
870 }
871 protocol = 0;
872 }
873
874 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
875
876 real_addr = 0x90000;
877 cmdline_addr = 0x9a000 - cmdline_size;
878 prot_addr = 0x10000;
879 } else if (protocol < 0x202) {
880
881 real_addr = 0x90000;
882 cmdline_addr = 0x9a000 - cmdline_size;
883 prot_addr = 0x100000;
884 } else {
885
886 real_addr = 0x10000;
887 cmdline_addr = 0x20000;
888 prot_addr = 0x100000;
889 }
890
891#if 0
892 fprintf(stderr,
893 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
894 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
895 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
896 real_addr,
897 cmdline_addr,
898 prot_addr);
899#endif
900
901
902 if (protocol >= 0x203) {
903 initrd_max = ldl_p(header+0x22c);
904 } else {
905 initrd_max = 0x37ffffff;
906 }
907
908 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
909 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
910 }
911
912 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
913 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
914 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
915
916 if (protocol >= 0x202) {
917 stl_p(header+0x228, cmdline_addr);
918 } else {
919 stw_p(header+0x20, 0xA33F);
920 stw_p(header+0x22, cmdline_addr-real_addr);
921 }
922
923
924 vmode = strstr(kernel_cmdline, "vga=");
925 if (vmode) {
926 unsigned int video_mode;
927
928 vmode += 4;
929 if (!strncmp(vmode, "normal", 6)) {
930 video_mode = 0xffff;
931 } else if (!strncmp(vmode, "ext", 3)) {
932 video_mode = 0xfffe;
933 } else if (!strncmp(vmode, "ask", 3)) {
934 video_mode = 0xfffd;
935 } else {
936 video_mode = strtol(vmode, NULL, 0);
937 }
938 stw_p(header+0x1fa, video_mode);
939 }
940
941
942
943
944
945 if (protocol >= 0x200) {
946 header[0x210] = 0xB0;
947 }
948
949 if (protocol >= 0x201) {
950 header[0x211] |= 0x80;
951 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
952 }
953
954
955 if (initrd_filename) {
956 if (protocol < 0x200) {
957 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
958 exit(1);
959 }
960
961 initrd_size = get_image_size(initrd_filename);
962 if (initrd_size < 0) {
963 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
964 initrd_filename, strerror(errno));
965 exit(1);
966 }
967
968 initrd_addr = (initrd_max-initrd_size) & ~4095;
969
970 initrd_data = g_malloc(initrd_size);
971 load_image(initrd_filename, initrd_data);
972
973 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
974 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
975 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
976
977 stl_p(header+0x218, initrd_addr);
978 stl_p(header+0x21c, initrd_size);
979 }
980
981
982 setup_size = header[0x1f1];
983 if (setup_size == 0) {
984 setup_size = 4;
985 }
986 setup_size = (setup_size+1)*512;
987 if (setup_size > kernel_size) {
988 fprintf(stderr, "qemu: invalid kernel header\n");
989 exit(1);
990 }
991 kernel_size -= setup_size;
992
993 setup = g_malloc(setup_size);
994 kernel = g_malloc(kernel_size);
995 fseek(f, 0, SEEK_SET);
996 if (fread(setup, 1, setup_size, f) != setup_size) {
997 fprintf(stderr, "fread() failed\n");
998 exit(1);
999 }
1000 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1001 fprintf(stderr, "fread() failed\n");
1002 exit(1);
1003 }
1004 fclose(f);
1005
1006
1007 if (dtb_filename) {
1008 if (protocol < 0x209) {
1009 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1010 exit(1);
1011 }
1012
1013 dtb_size = get_image_size(dtb_filename);
1014 if (dtb_size <= 0) {
1015 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1016 dtb_filename, strerror(errno));
1017 exit(1);
1018 }
1019
1020 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1021 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1022 kernel = g_realloc(kernel, kernel_size);
1023
1024 stq_p(header+0x250, prot_addr + setup_data_offset);
1025
1026 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1027 setup_data->next = 0;
1028 setup_data->type = cpu_to_le32(SETUP_DTB);
1029 setup_data->len = cpu_to_le32(dtb_size);
1030
1031 load_image_size(dtb_filename, setup_data->data, dtb_size);
1032 }
1033
1034 memcpy(setup, header, MIN(sizeof(header), setup_size));
1035
1036 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1037 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1038 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1039
1040 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1041 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1042 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1043
1044 if (fw_cfg_dma_enabled(fw_cfg)) {
1045 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1046 option_rom[nb_option_roms].bootindex = 0;
1047 } else {
1048 option_rom[nb_option_roms].name = "linuxboot.bin";
1049 option_rom[nb_option_roms].bootindex = 0;
1050 }
1051 nb_option_roms++;
1052}
1053
1054#define NE2000_NB_MAX 6
1055
1056static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1057 0x280, 0x380 };
1058static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1059
1060void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1061{
1062 static int nb_ne2k = 0;
1063
1064 if (nb_ne2k == NE2000_NB_MAX)
1065 return;
1066 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1067 ne2000_irq[nb_ne2k], nd);
1068 nb_ne2k++;
1069}
1070
1071DeviceState *cpu_get_current_apic(void)
1072{
1073 if (current_cpu) {
1074 X86CPU *cpu = X86_CPU(current_cpu);
1075 return cpu->apic_state;
1076 } else {
1077 return NULL;
1078 }
1079}
1080
1081void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1082{
1083 X86CPU *cpu = opaque;
1084
1085 if (level) {
1086 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1087 }
1088}
1089
1090static X86CPU *pc_new_cpu(const char *typename, int64_t apic_id,
1091 Error **errp)
1092{
1093 X86CPU *cpu = NULL;
1094 Error *local_err = NULL;
1095
1096 cpu = X86_CPU(object_new(typename));
1097
1098 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
1099 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
1100
1101 if (local_err) {
1102 error_propagate(errp, local_err);
1103 object_unref(OBJECT(cpu));
1104 cpu = NULL;
1105 }
1106 return cpu;
1107}
1108
1109void pc_hot_add_cpu(const int64_t id, Error **errp)
1110{
1111 X86CPU *cpu;
1112 ObjectClass *oc;
1113 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1114 int64_t apic_id = x86_cpu_apic_id_from_index(id);
1115 Error *local_err = NULL;
1116
1117 if (id < 0) {
1118 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1119 return;
1120 }
1121
1122 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1123 error_setg(errp, "Unable to add CPU: %" PRIi64
1124 ", resulting APIC ID (%" PRIi64 ") is too large",
1125 id, apic_id);
1126 return;
1127 }
1128
1129 assert(pcms->possible_cpus->cpus[0].cpu);
1130 oc = OBJECT_CLASS(CPU_GET_CLASS(pcms->possible_cpus->cpus[0].cpu));
1131 cpu = pc_new_cpu(object_class_get_name(oc), apic_id, &local_err);
1132 if (local_err) {
1133 error_propagate(errp, local_err);
1134 return;
1135 }
1136 object_unref(OBJECT(cpu));
1137}
1138
1139void pc_cpus_init(PCMachineState *pcms)
1140{
1141 int i;
1142 CPUClass *cc;
1143 ObjectClass *oc;
1144 const char *typename;
1145 gchar **model_pieces;
1146 X86CPU *cpu = NULL;
1147 MachineState *machine = MACHINE(pcms);
1148
1149
1150 if (machine->cpu_model == NULL) {
1151#ifdef TARGET_X86_64
1152 machine->cpu_model = "qemu64";
1153#else
1154 machine->cpu_model = "qemu32";
1155#endif
1156 }
1157
1158 model_pieces = g_strsplit(machine->cpu_model, ",", 2);
1159 if (!model_pieces[0]) {
1160 error_report("Invalid/empty CPU model name");
1161 exit(1);
1162 }
1163
1164 oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]);
1165 if (oc == NULL) {
1166 error_report("Unable to find CPU definition: %s", model_pieces[0]);
1167 exit(1);
1168 }
1169 typename = object_class_get_name(oc);
1170 cc = CPU_CLASS(oc);
1171 cc->parse_features(typename, model_pieces[1], &error_fatal);
1172 g_strfreev(model_pieces);
1173
1174
1175
1176
1177
1178
1179
1180
1181 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
1182 pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1183 sizeof(CPUArchId) * max_cpus);
1184 for (i = 0; i < max_cpus; i++) {
1185 pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
1186 pcms->possible_cpus->len++;
1187 if (i < smp_cpus) {
1188 cpu = pc_new_cpu(typename, x86_cpu_apic_id_from_index(i),
1189 &error_fatal);
1190 object_unref(OBJECT(cpu));
1191 }
1192 }
1193
1194
1195 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
1196}
1197
1198static void pc_build_feature_control_file(PCMachineState *pcms)
1199{
1200 X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu);
1201 CPUX86State *env = &cpu->env;
1202 uint32_t unused, ecx, edx;
1203 uint64_t feature_control_bits = 0;
1204 uint64_t *val;
1205
1206 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1207 if (ecx & CPUID_EXT_VMX) {
1208 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1209 }
1210
1211 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1212 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1213 (env->mcg_cap & MCG_LMCE_P)) {
1214 feature_control_bits |= FEATURE_CONTROL_LMCE;
1215 }
1216
1217 if (!feature_control_bits) {
1218 return;
1219 }
1220
1221 val = g_malloc(sizeof(*val));
1222 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1223 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1224}
1225
1226static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1227{
1228 if (cpus_count > 0xff) {
1229
1230
1231
1232
1233 rtc_set_memory(rtc, 0x5f, 0);
1234 } else {
1235 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1236 }
1237}
1238
1239static
1240void pc_machine_done(Notifier *notifier, void *data)
1241{
1242 PCMachineState *pcms = container_of(notifier,
1243 PCMachineState, machine_done);
1244 PCIBus *bus = pcms->bus;
1245
1246
1247 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1248
1249 if (bus) {
1250 int extra_hosts = 0;
1251
1252 QLIST_FOREACH(bus, &bus->child, sibling) {
1253
1254 if (pci_bus_is_root(bus)) {
1255 extra_hosts++;
1256 }
1257 }
1258 if (extra_hosts && pcms->fw_cfg) {
1259 uint64_t *val = g_malloc(sizeof(*val));
1260 *val = cpu_to_le64(extra_hosts);
1261 fw_cfg_add_file(pcms->fw_cfg,
1262 "etc/extra-pci-roots", val, sizeof(*val));
1263 }
1264 }
1265
1266 acpi_setup();
1267 if (pcms->fw_cfg) {
1268 pc_build_smbios(pcms->fw_cfg);
1269 pc_build_feature_control_file(pcms);
1270
1271 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1272 }
1273
1274 if (pcms->apic_id_limit > 255) {
1275 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1276
1277 if (!iommu || !iommu->x86_iommu.intr_supported ||
1278 iommu->intr_eim != ON_OFF_AUTO_ON) {
1279 error_report("current -smp configuration requires "
1280 "Extended Interrupt Mode enabled. "
1281 "You can add an IOMMU using: "
1282 "-device intel-iommu,intremap=on,eim=on");
1283 exit(EXIT_FAILURE);
1284 }
1285 }
1286}
1287
1288void pc_guest_info_init(PCMachineState *pcms)
1289{
1290 int i;
1291
1292 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1293 pcms->numa_nodes = nb_numa_nodes;
1294 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1295 sizeof *pcms->node_mem);
1296 for (i = 0; i < nb_numa_nodes; i++) {
1297 pcms->node_mem[i] = numa_info[i].node_mem;
1298 }
1299
1300 pcms->machine_done.notify = pc_machine_done;
1301 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1302}
1303
1304
1305void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1306 MemoryRegion *pci_address_space)
1307{
1308
1309 memory_region_add_subregion_overlap(system_memory, 0x0,
1310 pci_address_space, -1);
1311}
1312
1313void pc_acpi_init(const char *default_dsdt)
1314{
1315 char *filename;
1316
1317 if (acpi_tables != NULL) {
1318
1319 return;
1320 }
1321
1322 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1323 if (filename == NULL) {
1324 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1325 } else {
1326 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1327 &error_abort);
1328 Error *err = NULL;
1329
1330 qemu_opt_set(opts, "file", filename, &error_abort);
1331
1332 acpi_table_add_builtin(opts, &err);
1333 if (err) {
1334 error_reportf_err(err, "WARNING: failed to load %s: ",
1335 filename);
1336 }
1337 g_free(filename);
1338 }
1339}
1340
1341void xen_load_linux(PCMachineState *pcms)
1342{
1343 int i;
1344 FWCfgState *fw_cfg;
1345
1346 assert(MACHINE(pcms)->kernel_filename != NULL);
1347
1348 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1349 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1350 rom_set_fw(fw_cfg);
1351
1352 load_linux(pcms, fw_cfg);
1353 for (i = 0; i < nb_option_roms; i++) {
1354 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1355 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1356 !strcmp(option_rom[i].name, "multiboot.bin"));
1357 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1358 }
1359 pcms->fw_cfg = fw_cfg;
1360}
1361
1362void pc_memory_init(PCMachineState *pcms,
1363 MemoryRegion *system_memory,
1364 MemoryRegion *rom_memory,
1365 MemoryRegion **ram_memory)
1366{
1367 int linux_boot, i;
1368 MemoryRegion *ram, *option_rom_mr;
1369 MemoryRegion *ram_below_4g, *ram_above_4g;
1370 FWCfgState *fw_cfg;
1371 MachineState *machine = MACHINE(pcms);
1372 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1373
1374 assert(machine->ram_size == pcms->below_4g_mem_size +
1375 pcms->above_4g_mem_size);
1376
1377 linux_boot = (machine->kernel_filename != NULL);
1378
1379
1380
1381
1382
1383 ram = g_malloc(sizeof(*ram));
1384 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1385 machine->ram_size);
1386 *ram_memory = ram;
1387 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1388 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1389 0, pcms->below_4g_mem_size);
1390 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1391 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1392 if (pcms->above_4g_mem_size > 0) {
1393 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1394 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1395 pcms->below_4g_mem_size,
1396 pcms->above_4g_mem_size);
1397 memory_region_add_subregion(system_memory, 0x100000000ULL,
1398 ram_above_4g);
1399 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1400 }
1401
1402 if (!pcmc->has_reserved_memory &&
1403 (machine->ram_slots ||
1404 (machine->maxram_size > machine->ram_size))) {
1405 MachineClass *mc = MACHINE_GET_CLASS(machine);
1406
1407 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1408 mc->name);
1409 exit(EXIT_FAILURE);
1410 }
1411
1412
1413 if (pcmc->has_reserved_memory &&
1414 (machine->ram_size < machine->maxram_size)) {
1415 ram_addr_t hotplug_mem_size =
1416 machine->maxram_size - machine->ram_size;
1417
1418 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1419 error_report("unsupported amount of memory slots: %"PRIu64,
1420 machine->ram_slots);
1421 exit(EXIT_FAILURE);
1422 }
1423
1424 if (QEMU_ALIGN_UP(machine->maxram_size,
1425 TARGET_PAGE_SIZE) != machine->maxram_size) {
1426 error_report("maximum memory size must by aligned to multiple of "
1427 "%d bytes", TARGET_PAGE_SIZE);
1428 exit(EXIT_FAILURE);
1429 }
1430
1431 pcms->hotplug_memory.base =
1432 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30);
1433
1434 if (pcmc->enforce_aligned_dimm) {
1435
1436 hotplug_mem_size += (1ULL << 30) * machine->ram_slots;
1437 }
1438
1439 if ((pcms->hotplug_memory.base + hotplug_mem_size) <
1440 hotplug_mem_size) {
1441 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1442 machine->maxram_size);
1443 exit(EXIT_FAILURE);
1444 }
1445
1446 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms),
1447 "hotplug-memory", hotplug_mem_size);
1448 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base,
1449 &pcms->hotplug_memory.mr);
1450 }
1451
1452
1453 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
1454
1455 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1456 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1457 &error_fatal);
1458 vmstate_register_ram_global(option_rom_mr);
1459 memory_region_add_subregion_overlap(rom_memory,
1460 PC_ROM_MIN_VGA,
1461 option_rom_mr,
1462 1);
1463
1464 fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1465
1466 rom_set_fw(fw_cfg);
1467
1468 if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) {
1469 uint64_t *val = g_malloc(sizeof(*val));
1470 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1471 uint64_t res_mem_end = pcms->hotplug_memory.base;
1472
1473 if (!pcmc->broken_reserved_end) {
1474 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr);
1475 }
1476 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30));
1477 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1478 }
1479
1480 if (linux_boot) {
1481 load_linux(pcms, fw_cfg);
1482 }
1483
1484 for (i = 0; i < nb_option_roms; i++) {
1485 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1486 }
1487 pcms->fw_cfg = fw_cfg;
1488
1489
1490 pcms->ioapic_as = &address_space_memory;
1491}
1492
1493qemu_irq pc_allocate_cpu_irq(void)
1494{
1495 return qemu_allocate_irq(pic_irq_request, NULL, 0);
1496}
1497
1498DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1499{
1500 DeviceState *dev = NULL;
1501
1502 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1503 if (pci_bus) {
1504 PCIDevice *pcidev = pci_vga_init(pci_bus);
1505 dev = pcidev ? &pcidev->qdev : NULL;
1506 } else if (isa_bus) {
1507 ISADevice *isadev = isa_vga_init(isa_bus);
1508 dev = isadev ? DEVICE(isadev) : NULL;
1509 }
1510 rom_reset_order_override();
1511 return dev;
1512}
1513
1514static const MemoryRegionOps ioport80_io_ops = {
1515 .write = ioport80_write,
1516 .read = ioport80_read,
1517 .endianness = DEVICE_NATIVE_ENDIAN,
1518 .impl = {
1519 .min_access_size = 1,
1520 .max_access_size = 1,
1521 },
1522};
1523
1524static const MemoryRegionOps ioportF0_io_ops = {
1525 .write = ioportF0_write,
1526 .read = ioportF0_read,
1527 .endianness = DEVICE_NATIVE_ENDIAN,
1528 .impl = {
1529 .min_access_size = 1,
1530 .max_access_size = 1,
1531 },
1532};
1533
1534void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1535 ISADevice **rtc_state,
1536 bool create_fdctrl,
1537 bool no_vmport,
1538 uint32_t hpet_irqs)
1539{
1540 int i;
1541 DriveInfo *fd[MAX_FD];
1542 DeviceState *hpet = NULL;
1543 int pit_isa_irq = 0;
1544 qemu_irq pit_alt_irq = NULL;
1545 qemu_irq rtc_irq = NULL;
1546 qemu_irq *a20_line;
1547 ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1548 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1549 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1550
1551 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1552 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1553
1554 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1555 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1556
1557
1558
1559
1560
1561
1562
1563 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1564
1565 hpet = qdev_try_create(NULL, TYPE_HPET);
1566 if (hpet) {
1567
1568
1569
1570
1571 uint8_t compat = object_property_get_int(OBJECT(hpet),
1572 HPET_INTCAP, NULL);
1573 if (!compat) {
1574 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1575 }
1576 qdev_init_nofail(hpet);
1577 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1578
1579 for (i = 0; i < GSI_NUM_PINS; i++) {
1580 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1581 }
1582 pit_isa_irq = -1;
1583 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1584 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1585 }
1586 }
1587 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1588
1589 qemu_register_boot_set(pc_boot_set, *rtc_state);
1590
1591 if (!xen_enabled()) {
1592 if (kvm_pit_in_kernel()) {
1593 pit = kvm_pit_init(isa_bus, 0x40);
1594 } else {
1595 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1596 }
1597 if (hpet) {
1598
1599 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1600 }
1601 pcspk_init(isa_bus, pit);
1602 }
1603
1604 serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS);
1605 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1606
1607 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1608 i8042 = isa_create_simple(isa_bus, "i8042");
1609 i8042_setup_a20_line(i8042, a20_line[0]);
1610 if (!no_vmport) {
1611 vmport_init(isa_bus);
1612 vmmouse = isa_try_create(isa_bus, "vmmouse");
1613 } else {
1614 vmmouse = NULL;
1615 }
1616 if (vmmouse) {
1617 DeviceState *dev = DEVICE(vmmouse);
1618 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1619 qdev_init_nofail(dev);
1620 }
1621 port92 = isa_create_simple(isa_bus, "port92");
1622 port92_init(port92, a20_line[1]);
1623 g_free(a20_line);
1624
1625 DMA_init(isa_bus, 0);
1626
1627 for(i = 0; i < MAX_FD; i++) {
1628 fd[i] = drive_get(IF_FLOPPY, 0, i);
1629 create_fdctrl |= !!fd[i];
1630 }
1631 if (create_fdctrl) {
1632 fdctrl_init_isa(isa_bus, fd);
1633 }
1634}
1635
1636void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1637{
1638 int i;
1639
1640 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1641 for (i = 0; i < nb_nics; i++) {
1642 NICInfo *nd = &nd_table[i];
1643
1644 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1645 pc_init_ne2k_isa(isa_bus, nd);
1646 } else {
1647 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1648 }
1649 }
1650 rom_reset_order_override();
1651}
1652
1653void pc_pci_device_init(PCIBus *pci_bus)
1654{
1655 int max_bus;
1656 int bus;
1657
1658 max_bus = drive_get_max_bus(IF_SCSI);
1659 for (bus = 0; bus <= max_bus; bus++) {
1660 pci_create_simple(pci_bus, -1, "lsi53c895a");
1661 }
1662}
1663
1664void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1665{
1666 DeviceState *dev;
1667 SysBusDevice *d;
1668 unsigned int i;
1669
1670 if (kvm_ioapic_in_kernel()) {
1671 dev = qdev_create(NULL, "kvm-ioapic");
1672 } else {
1673 dev = qdev_create(NULL, "ioapic");
1674 }
1675 if (parent_name) {
1676 object_property_add_child(object_resolve_path(parent_name, NULL),
1677 "ioapic", OBJECT(dev), NULL);
1678 }
1679 qdev_init_nofail(dev);
1680 d = SYS_BUS_DEVICE(dev);
1681 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1682
1683 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1684 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1685 }
1686}
1687
1688static void pc_dimm_plug(HotplugHandler *hotplug_dev,
1689 DeviceState *dev, Error **errp)
1690{
1691 HotplugHandlerClass *hhc;
1692 Error *local_err = NULL;
1693 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1694 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1695 PCDIMMDevice *dimm = PC_DIMM(dev);
1696 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1697 MemoryRegion *mr = ddc->get_memory_region(dimm);
1698 uint64_t align = TARGET_PAGE_SIZE;
1699
1700 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) {
1701 align = memory_region_get_alignment(mr);
1702 }
1703
1704 if (!pcms->acpi_dev) {
1705 error_setg(&local_err,
1706 "memory hotplug is not enabled: missing acpi device");
1707 goto out;
1708 }
1709
1710 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err);
1711 if (local_err) {
1712 goto out;
1713 }
1714
1715 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1716 nvdimm_plug(&pcms->acpi_nvdimm_state);
1717 }
1718
1719 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1720 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1721out:
1722 error_propagate(errp, local_err);
1723}
1724
1725static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev,
1726 DeviceState *dev, Error **errp)
1727{
1728 HotplugHandlerClass *hhc;
1729 Error *local_err = NULL;
1730 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1731
1732 if (!pcms->acpi_dev) {
1733 error_setg(&local_err,
1734 "memory hotplug is not enabled: missing acpi device");
1735 goto out;
1736 }
1737
1738 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1739 error_setg(&local_err,
1740 "nvdimm device hot unplug is not supported yet.");
1741 goto out;
1742 }
1743
1744 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1745 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1746
1747out:
1748 error_propagate(errp, local_err);
1749}
1750
1751static void pc_dimm_unplug(HotplugHandler *hotplug_dev,
1752 DeviceState *dev, Error **errp)
1753{
1754 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1755 PCDIMMDevice *dimm = PC_DIMM(dev);
1756 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1757 MemoryRegion *mr = ddc->get_memory_region(dimm);
1758 HotplugHandlerClass *hhc;
1759 Error *local_err = NULL;
1760
1761 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1762 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1763
1764 if (local_err) {
1765 goto out;
1766 }
1767
1768 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr);
1769 object_unparent(OBJECT(dev));
1770
1771 out:
1772 error_propagate(errp, local_err);
1773}
1774
1775static int pc_apic_cmp(const void *a, const void *b)
1776{
1777 CPUArchId *apic_a = (CPUArchId *)a;
1778 CPUArchId *apic_b = (CPUArchId *)b;
1779
1780 return apic_a->arch_id - apic_b->arch_id;
1781}
1782
1783
1784
1785
1786
1787static CPUArchId *pc_find_cpu_slot(PCMachineState *pcms, CPUState *cpu,
1788 int *idx)
1789{
1790 CPUClass *cc = CPU_GET_CLASS(cpu);
1791 CPUArchId apic_id, *found_cpu;
1792
1793 apic_id.arch_id = cc->get_arch_id(CPU(cpu));
1794 found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus,
1795 pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus),
1796 pc_apic_cmp);
1797 if (found_cpu && idx) {
1798 *idx = found_cpu - pcms->possible_cpus->cpus;
1799 }
1800 return found_cpu;
1801}
1802
1803static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1804 DeviceState *dev, Error **errp)
1805{
1806 CPUArchId *found_cpu;
1807 HotplugHandlerClass *hhc;
1808 Error *local_err = NULL;
1809 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1810
1811 if (pcms->acpi_dev) {
1812 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1813 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1814 if (local_err) {
1815 goto out;
1816 }
1817 }
1818
1819
1820 pcms->boot_cpus++;
1821 if (pcms->rtc) {
1822 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1823 }
1824 if (pcms->fw_cfg) {
1825 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1826 }
1827
1828 found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL);
1829 found_cpu->cpu = CPU(dev);
1830out:
1831 error_propagate(errp, local_err);
1832}
1833static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1834 DeviceState *dev, Error **errp)
1835{
1836 int idx = -1;
1837 HotplugHandlerClass *hhc;
1838 Error *local_err = NULL;
1839 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1840
1841 pc_find_cpu_slot(pcms, CPU(dev), &idx);
1842 assert(idx != -1);
1843 if (idx == 0) {
1844 error_setg(&local_err, "Boot CPU is unpluggable");
1845 goto out;
1846 }
1847
1848 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1849 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1850
1851 if (local_err) {
1852 goto out;
1853 }
1854
1855 out:
1856 error_propagate(errp, local_err);
1857
1858}
1859
1860static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1861 DeviceState *dev, Error **errp)
1862{
1863 CPUArchId *found_cpu;
1864 HotplugHandlerClass *hhc;
1865 Error *local_err = NULL;
1866 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1867
1868 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1869 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1870
1871 if (local_err) {
1872 goto out;
1873 }
1874
1875 found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL);
1876 found_cpu->cpu = NULL;
1877 object_unparent(OBJECT(dev));
1878
1879
1880 pcms->boot_cpus--;
1881
1882 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1883 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1884 out:
1885 error_propagate(errp, local_err);
1886}
1887
1888static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1889 DeviceState *dev, Error **errp)
1890{
1891 int idx;
1892 CPUState *cs;
1893 CPUArchId *cpu_slot;
1894 X86CPUTopoInfo topo;
1895 X86CPU *cpu = X86_CPU(dev);
1896 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1897
1898
1899 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1900 int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
1901
1902 if (cpu->socket_id < 0) {
1903 error_setg(errp, "CPU socket-id is not set");
1904 return;
1905 } else if (cpu->socket_id > max_socket) {
1906 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1907 cpu->socket_id, max_socket);
1908 return;
1909 }
1910 if (cpu->core_id < 0) {
1911 error_setg(errp, "CPU core-id is not set");
1912 return;
1913 } else if (cpu->core_id > (smp_cores - 1)) {
1914 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1915 cpu->core_id, smp_cores - 1);
1916 return;
1917 }
1918 if (cpu->thread_id < 0) {
1919 error_setg(errp, "CPU thread-id is not set");
1920 return;
1921 } else if (cpu->thread_id > (smp_threads - 1)) {
1922 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1923 cpu->thread_id, smp_threads - 1);
1924 return;
1925 }
1926
1927 topo.pkg_id = cpu->socket_id;
1928 topo.core_id = cpu->core_id;
1929 topo.smt_id = cpu->thread_id;
1930 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
1931 }
1932
1933 cpu_slot = pc_find_cpu_slot(pcms, CPU(dev), &idx);
1934 if (!cpu_slot) {
1935 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1936 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
1937 " APIC ID %" PRIu32 ", valid index range 0:%d",
1938 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
1939 pcms->possible_cpus->len - 1);
1940 return;
1941 }
1942
1943 if (cpu_slot->cpu) {
1944 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1945 idx, cpu->apic_id);
1946 return;
1947 }
1948
1949
1950
1951
1952
1953
1954
1955 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1956 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1957 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1958 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1959 return;
1960 }
1961 cpu->socket_id = topo.pkg_id;
1962
1963 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1964 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1965 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1966 return;
1967 }
1968 cpu->core_id = topo.core_id;
1969
1970 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
1971 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1972 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
1973 return;
1974 }
1975 cpu->thread_id = topo.smt_id;
1976
1977 cs = CPU(cpu);
1978 cs->cpu_index = idx;
1979}
1980
1981static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1982 DeviceState *dev, Error **errp)
1983{
1984 if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1985 pc_cpu_pre_plug(hotplug_dev, dev, errp);
1986 }
1987}
1988
1989static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1990 DeviceState *dev, Error **errp)
1991{
1992 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1993 pc_dimm_plug(hotplug_dev, dev, errp);
1994 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1995 pc_cpu_plug(hotplug_dev, dev, errp);
1996 }
1997}
1998
1999static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2000 DeviceState *dev, Error **errp)
2001{
2002 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2003 pc_dimm_unplug_request(hotplug_dev, dev, errp);
2004 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2005 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2006 } else {
2007 error_setg(errp, "acpi: device unplug request for not supported device"
2008 " type: %s", object_get_typename(OBJECT(dev)));
2009 }
2010}
2011
2012static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2013 DeviceState *dev, Error **errp)
2014{
2015 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2016 pc_dimm_unplug(hotplug_dev, dev, errp);
2017 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2018 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2019 } else {
2020 error_setg(errp, "acpi: device unplug for not supported device"
2021 " type: %s", object_get_typename(OBJECT(dev)));
2022 }
2023}
2024
2025static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
2026 DeviceState *dev)
2027{
2028 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
2029
2030 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2031 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2032 return HOTPLUG_HANDLER(machine);
2033 }
2034
2035 return pcmc->get_hotplug_handler ?
2036 pcmc->get_hotplug_handler(machine, dev) : NULL;
2037}
2038
2039static void
2040pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v,
2041 const char *name, void *opaque,
2042 Error **errp)
2043{
2044 PCMachineState *pcms = PC_MACHINE(obj);
2045 int64_t value = memory_region_size(&pcms->hotplug_memory.mr);
2046
2047 visit_type_int(v, name, &value, errp);
2048}
2049
2050static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2051 const char *name, void *opaque,
2052 Error **errp)
2053{
2054 PCMachineState *pcms = PC_MACHINE(obj);
2055 uint64_t value = pcms->max_ram_below_4g;
2056
2057 visit_type_size(v, name, &value, errp);
2058}
2059
2060static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2061 const char *name, void *opaque,
2062 Error **errp)
2063{
2064 PCMachineState *pcms = PC_MACHINE(obj);
2065 Error *error = NULL;
2066 uint64_t value;
2067
2068 visit_type_size(v, name, &value, &error);
2069 if (error) {
2070 error_propagate(errp, error);
2071 return;
2072 }
2073 if (value > (1ULL << 32)) {
2074 error_setg(&error,
2075 "Machine option 'max-ram-below-4g=%"PRIu64
2076 "' expects size less than or equal to 4G", value);
2077 error_propagate(errp, error);
2078 return;
2079 }
2080
2081 if (value < (1ULL << 20)) {
2082 error_report("Warning: small max_ram_below_4g(%"PRIu64
2083 ") less than 1M. BIOS may not work..",
2084 value);
2085 }
2086
2087 pcms->max_ram_below_4g = value;
2088}
2089
2090static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2091 void *opaque, Error **errp)
2092{
2093 PCMachineState *pcms = PC_MACHINE(obj);
2094 OnOffAuto vmport = pcms->vmport;
2095
2096 visit_type_OnOffAuto(v, name, &vmport, errp);
2097}
2098
2099static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2100 void *opaque, Error **errp)
2101{
2102 PCMachineState *pcms = PC_MACHINE(obj);
2103
2104 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2105}
2106
2107bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2108{
2109 bool smm_available = false;
2110
2111 if (pcms->smm == ON_OFF_AUTO_OFF) {
2112 return false;
2113 }
2114
2115 if (tcg_enabled() || qtest_enabled()) {
2116 smm_available = true;
2117 } else if (kvm_enabled()) {
2118 smm_available = kvm_has_smm();
2119 }
2120
2121 if (smm_available) {
2122 return true;
2123 }
2124
2125 if (pcms->smm == ON_OFF_AUTO_ON) {
2126 error_report("System Management Mode not supported by this hypervisor.");
2127 exit(1);
2128 }
2129 return false;
2130}
2131
2132static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2133 void *opaque, Error **errp)
2134{
2135 PCMachineState *pcms = PC_MACHINE(obj);
2136 OnOffAuto smm = pcms->smm;
2137
2138 visit_type_OnOffAuto(v, name, &smm, errp);
2139}
2140
2141static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2142 void *opaque, Error **errp)
2143{
2144 PCMachineState *pcms = PC_MACHINE(obj);
2145
2146 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2147}
2148
2149static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2150{
2151 PCMachineState *pcms = PC_MACHINE(obj);
2152
2153 return pcms->acpi_nvdimm_state.is_enabled;
2154}
2155
2156static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2157{
2158 PCMachineState *pcms = PC_MACHINE(obj);
2159
2160 pcms->acpi_nvdimm_state.is_enabled = value;
2161}
2162
2163static void pc_machine_initfn(Object *obj)
2164{
2165 PCMachineState *pcms = PC_MACHINE(obj);
2166
2167 pcms->max_ram_below_4g = 0;
2168 pcms->smm = ON_OFF_AUTO_AUTO;
2169 pcms->vmport = ON_OFF_AUTO_AUTO;
2170
2171 pcms->acpi_nvdimm_state.is_enabled = false;
2172
2173 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2174}
2175
2176static void pc_machine_reset(void)
2177{
2178 CPUState *cs;
2179 X86CPU *cpu;
2180
2181 qemu_devices_reset();
2182
2183
2184
2185
2186 CPU_FOREACH(cs) {
2187 cpu = X86_CPU(cs);
2188
2189 if (cpu->apic_state) {
2190 device_reset(cpu->apic_state);
2191 }
2192 }
2193}
2194
2195static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index)
2196{
2197 X86CPUTopoInfo topo;
2198 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index,
2199 &topo);
2200 return topo.pkg_id;
2201}
2202
2203static CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine)
2204{
2205 PCMachineState *pcms = PC_MACHINE(machine);
2206 int len = sizeof(CPUArchIdList) +
2207 sizeof(CPUArchId) * (pcms->possible_cpus->len);
2208 CPUArchIdList *list = g_malloc(len);
2209
2210 memcpy(list, pcms->possible_cpus, len);
2211 return list;
2212}
2213
2214static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine)
2215{
2216 int i;
2217 CPUState *cpu;
2218 HotpluggableCPUList *head = NULL;
2219 PCMachineState *pcms = PC_MACHINE(machine);
2220 const char *cpu_type;
2221
2222 cpu = pcms->possible_cpus->cpus[0].cpu;
2223 assert(cpu);
2224 cpu_type = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(cpu)));
2225
2226 for (i = 0; i < pcms->possible_cpus->len; i++) {
2227 X86CPUTopoInfo topo;
2228 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2229 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2230 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2231 const uint32_t apic_id = pcms->possible_cpus->cpus[i].arch_id;
2232
2233 x86_topo_ids_from_apicid(apic_id, smp_cores, smp_threads, &topo);
2234
2235 cpu_item->type = g_strdup(cpu_type);
2236 cpu_item->vcpus_count = 1;
2237 cpu_props->has_socket_id = true;
2238 cpu_props->socket_id = topo.pkg_id;
2239 cpu_props->has_core_id = true;
2240 cpu_props->core_id = topo.core_id;
2241 cpu_props->has_thread_id = true;
2242 cpu_props->thread_id = topo.smt_id;
2243 cpu_item->props = cpu_props;
2244
2245 cpu = pcms->possible_cpus->cpus[i].cpu;
2246 if (cpu) {
2247 cpu_item->has_qom_path = true;
2248 cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu));
2249 }
2250
2251 list_item->value = cpu_item;
2252 list_item->next = head;
2253 head = list_item;
2254 }
2255 return head;
2256}
2257
2258static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2259{
2260
2261 CPUState *cs;
2262
2263 CPU_FOREACH(cs) {
2264 X86CPU *cpu = X86_CPU(cs);
2265
2266 if (!cpu->apic_state) {
2267 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2268 } else {
2269 apic_deliver_nmi(cpu->apic_state);
2270 }
2271 }
2272}
2273
2274static void pc_machine_class_init(ObjectClass *oc, void *data)
2275{
2276 MachineClass *mc = MACHINE_CLASS(oc);
2277 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2278 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2279 NMIClass *nc = NMI_CLASS(oc);
2280
2281 pcmc->get_hotplug_handler = mc->get_hotplug_handler;
2282 pcmc->pci_enabled = true;
2283 pcmc->has_acpi_build = true;
2284 pcmc->rsdp_in_ram = true;
2285 pcmc->smbios_defaults = true;
2286 pcmc->smbios_uuid_encoded = true;
2287 pcmc->gigabyte_align = true;
2288 pcmc->has_reserved_memory = true;
2289 pcmc->kvmclock_enabled = true;
2290 pcmc->enforce_aligned_dimm = true;
2291
2292
2293 pcmc->acpi_data_size = 0x20000 + 0x8000;
2294 pcmc->save_tsc_khz = true;
2295 mc->get_hotplug_handler = pc_get_hotpug_handler;
2296 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id;
2297 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2298 mc->query_hotpluggable_cpus = pc_query_hotpluggable_cpus;
2299 mc->default_boot_order = "cad";
2300 mc->hot_add_cpu = pc_hot_add_cpu;
2301 mc->max_cpus = 255;
2302 mc->reset = pc_machine_reset;
2303 hc->pre_plug = pc_machine_device_pre_plug_cb;
2304 hc->plug = pc_machine_device_plug_cb;
2305 hc->unplug_request = pc_machine_device_unplug_request_cb;
2306 hc->unplug = pc_machine_device_unplug_cb;
2307 nc->nmi_monitor_handler = x86_nmi;
2308
2309 object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int",
2310 pc_machine_get_hotplug_memory_region_size, NULL,
2311 NULL, NULL, &error_abort);
2312
2313 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2314 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2315 NULL, NULL, &error_abort);
2316
2317 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2318 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2319
2320 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2321 pc_machine_get_smm, pc_machine_set_smm,
2322 NULL, NULL, &error_abort);
2323 object_class_property_set_description(oc, PC_MACHINE_SMM,
2324 "Enable SMM (pc & q35)", &error_abort);
2325
2326 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2327 pc_machine_get_vmport, pc_machine_set_vmport,
2328 NULL, NULL, &error_abort);
2329 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2330 "Enable vmport (pc & q35)", &error_abort);
2331
2332 object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
2333 pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
2334}
2335
2336static const TypeInfo pc_machine_info = {
2337 .name = TYPE_PC_MACHINE,
2338 .parent = TYPE_MACHINE,
2339 .abstract = true,
2340 .instance_size = sizeof(PCMachineState),
2341 .instance_init = pc_machine_initfn,
2342 .class_size = sizeof(PCMachineClass),
2343 .class_init = pc_machine_class_init,
2344 .interfaces = (InterfaceInfo[]) {
2345 { TYPE_HOTPLUG_HANDLER },
2346 { TYPE_NMI },
2347 { }
2348 },
2349};
2350
2351static void pc_machine_register_types(void)
2352{
2353 type_register_static(&pc_machine_info);
2354}
2355
2356type_init(pc_machine_register_types)
2357