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20#include "qemu/osdep.h"
21#include "qemu/error-report.h"
22#include "qapi/error.h"
23#include "qemu-common.h"
24#include "cpu.h"
25#include "qapi/visitor.h"
26#include "hw/i386/apic.h"
27#include "hw/i386/apic_internal.h"
28#include "trace.h"
29#include "sysemu/kvm.h"
30#include "hw/qdev.h"
31#include "hw/sysbus.h"
32
33static int apic_irq_delivered;
34bool apic_report_tpr_access;
35
36void cpu_set_apic_base(DeviceState *dev, uint64_t val)
37{
38 trace_cpu_set_apic_base(val);
39
40 if (dev) {
41 APICCommonState *s = APIC_COMMON(dev);
42 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
43
44 if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) &&
45 (val & MSR_IA32_APICBASE_EXTD)) {
46 s->id = s->initial_apic_id;
47 }
48 info->set_base(s, val);
49 }
50}
51
52uint64_t cpu_get_apic_base(DeviceState *dev)
53{
54 if (dev) {
55 APICCommonState *s = APIC_COMMON(dev);
56 trace_cpu_get_apic_base((uint64_t)s->apicbase);
57 return s->apicbase;
58 } else {
59 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
60 return MSR_IA32_APICBASE_BSP;
61 }
62}
63
64void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
65{
66 APICCommonState *s;
67 APICCommonClass *info;
68
69 if (!dev) {
70 return;
71 }
72
73 s = APIC_COMMON(dev);
74 info = APIC_COMMON_GET_CLASS(s);
75
76 info->set_tpr(s, val);
77}
78
79uint8_t cpu_get_apic_tpr(DeviceState *dev)
80{
81 APICCommonState *s;
82 APICCommonClass *info;
83
84 if (!dev) {
85 return 0;
86 }
87
88 s = APIC_COMMON(dev);
89 info = APIC_COMMON_GET_CLASS(s);
90
91 return info->get_tpr(s);
92}
93
94void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
95{
96 APICCommonState *s = APIC_COMMON(dev);
97 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
98
99 apic_report_tpr_access = enable;
100 if (info->enable_tpr_reporting) {
101 info->enable_tpr_reporting(s, enable);
102 }
103}
104
105void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
106{
107 APICCommonState *s = APIC_COMMON(dev);
108 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
109
110 s->vapic_paddr = paddr;
111 info->vapic_base_update(s);
112}
113
114void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
115 TPRAccess access)
116{
117 APICCommonState *s = APIC_COMMON(dev);
118
119 vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
120}
121
122void apic_report_irq_delivered(int delivered)
123{
124 apic_irq_delivered += delivered;
125
126 trace_apic_report_irq_delivered(apic_irq_delivered);
127}
128
129void apic_reset_irq_delivered(void)
130{
131
132
133
134
135 volatile int a_i_d = apic_irq_delivered;
136 trace_apic_reset_irq_delivered(a_i_d);
137
138 apic_irq_delivered = 0;
139}
140
141int apic_get_irq_delivered(void)
142{
143 trace_apic_get_irq_delivered(apic_irq_delivered);
144
145 return apic_irq_delivered;
146}
147
148void apic_deliver_nmi(DeviceState *dev)
149{
150 APICCommonState *s = APIC_COMMON(dev);
151 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
152
153 info->external_nmi(s);
154}
155
156bool apic_next_timer(APICCommonState *s, int64_t current_time)
157{
158 int64_t d;
159
160
161
162
163
164 s->timer_expiry = -1;
165
166 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
167 return false;
168 }
169
170 d = (current_time - s->initial_count_load_time) >> s->count_shift;
171
172 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
173 if (!s->initial_count) {
174 return false;
175 }
176 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
177 ((uint64_t)s->initial_count + 1);
178 } else {
179 if (d >= s->initial_count) {
180 return false;
181 }
182 d = (uint64_t)s->initial_count + 1;
183 }
184 s->next_time = s->initial_count_load_time + (d << s->count_shift);
185 s->timer_expiry = s->next_time;
186 return true;
187}
188
189void apic_init_reset(DeviceState *dev)
190{
191 APICCommonState *s;
192 APICCommonClass *info;
193 int i;
194
195 if (!dev) {
196 return;
197 }
198 s = APIC_COMMON(dev);
199 s->tpr = 0;
200 s->spurious_vec = 0xff;
201 s->log_dest = 0;
202 s->dest_mode = 0xf;
203 memset(s->isr, 0, sizeof(s->isr));
204 memset(s->tmr, 0, sizeof(s->tmr));
205 memset(s->irr, 0, sizeof(s->irr));
206 for (i = 0; i < APIC_LVT_NB; i++) {
207 s->lvt[i] = APIC_LVT_MASKED;
208 }
209 s->esr = 0;
210 memset(s->icr, 0, sizeof(s->icr));
211 s->divide_conf = 0;
212 s->count_shift = 0;
213 s->initial_count = 0;
214 s->initial_count_load_time = 0;
215 s->next_time = 0;
216 s->wait_for_sipi = !cpu_is_bsp(s->cpu);
217
218 if (s->timer) {
219 timer_del(s->timer);
220 }
221 s->timer_expiry = -1;
222
223 info = APIC_COMMON_GET_CLASS(s);
224 if (info->reset) {
225 info->reset(s);
226 }
227}
228
229void apic_designate_bsp(DeviceState *dev, bool bsp)
230{
231 if (dev == NULL) {
232 return;
233 }
234
235 APICCommonState *s = APIC_COMMON(dev);
236 if (bsp) {
237 s->apicbase |= MSR_IA32_APICBASE_BSP;
238 } else {
239 s->apicbase &= ~MSR_IA32_APICBASE_BSP;
240 }
241}
242
243static void apic_reset_common(DeviceState *dev)
244{
245 APICCommonState *s = APIC_COMMON(dev);
246 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
247 uint32_t bsp;
248
249 bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
250 s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
251 s->id = s->initial_apic_id;
252
253 apic_reset_irq_delivered();
254
255 s->vapic_paddr = 0;
256 info->vapic_base_update(s);
257
258 apic_init_reset(dev);
259}
260
261
262static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
263{
264 APICCommonState *s = opaque;
265 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
266 int i;
267
268 if (version_id > 2) {
269 return -EINVAL;
270 }
271
272
273 qemu_get_be32s(f, &s->apicbase);
274 qemu_get_8s(f, &s->id);
275 qemu_get_8s(f, &s->arb_id);
276 qemu_get_8s(f, &s->tpr);
277 qemu_get_be32s(f, &s->spurious_vec);
278 qemu_get_8s(f, &s->log_dest);
279 qemu_get_8s(f, &s->dest_mode);
280 for (i = 0; i < 8; i++) {
281 qemu_get_be32s(f, &s->isr[i]);
282 qemu_get_be32s(f, &s->tmr[i]);
283 qemu_get_be32s(f, &s->irr[i]);
284 }
285 for (i = 0; i < APIC_LVT_NB; i++) {
286 qemu_get_be32s(f, &s->lvt[i]);
287 }
288 qemu_get_be32s(f, &s->esr);
289 qemu_get_be32s(f, &s->icr[0]);
290 qemu_get_be32s(f, &s->icr[1]);
291 qemu_get_be32s(f, &s->divide_conf);
292 s->count_shift = qemu_get_be32(f);
293 qemu_get_be32s(f, &s->initial_count);
294 s->initial_count_load_time = qemu_get_be64(f);
295 s->next_time = qemu_get_be64(f);
296
297 if (version_id >= 2) {
298 s->timer_expiry = qemu_get_be64(f);
299 }
300
301 if (info->post_load) {
302 info->post_load(s);
303 }
304 return 0;
305}
306
307static const VMStateDescription vmstate_apic_common;
308
309static void apic_common_realize(DeviceState *dev, Error **errp)
310{
311 APICCommonState *s = APIC_COMMON(dev);
312 APICCommonClass *info;
313 static DeviceState *vapic;
314 int instance_id = s->id;
315
316 info = APIC_COMMON_GET_CLASS(s);
317 info->realize(dev, errp);
318
319
320 if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
321 ram_size >= 1024 * 1024) {
322 vapic = sysbus_create_simple("kvmvapic", -1, NULL);
323 }
324 s->vapic = vapic;
325 if (apic_report_tpr_access && info->enable_tpr_reporting) {
326 info->enable_tpr_reporting(s, true);
327 }
328
329 if (s->legacy_instance_id) {
330 instance_id = -1;
331 }
332 vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,
333 s, -1, 0);
334}
335
336static void apic_common_unrealize(DeviceState *dev, Error **errp)
337{
338 APICCommonState *s = APIC_COMMON(dev);
339 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
340
341 vmstate_unregister(NULL, &vmstate_apic_common, s);
342 info->unrealize(dev, errp);
343
344 if (apic_report_tpr_access && info->enable_tpr_reporting) {
345 info->enable_tpr_reporting(s, false);
346 }
347}
348
349static int apic_pre_load(void *opaque)
350{
351 APICCommonState *s = APIC_COMMON(opaque);
352
353
354
355
356
357
358 s->wait_for_sipi = 0;
359 return 0;
360}
361
362static void apic_dispatch_pre_save(void *opaque)
363{
364 APICCommonState *s = APIC_COMMON(opaque);
365 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
366
367 if (info->pre_save) {
368 info->pre_save(s);
369 }
370}
371
372static int apic_dispatch_post_load(void *opaque, int version_id)
373{
374 APICCommonState *s = APIC_COMMON(opaque);
375 APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
376
377 if (info->post_load) {
378 info->post_load(s);
379 }
380 return 0;
381}
382
383static bool apic_common_sipi_needed(void *opaque)
384{
385 APICCommonState *s = APIC_COMMON(opaque);
386 return s->wait_for_sipi != 0;
387}
388
389static const VMStateDescription vmstate_apic_common_sipi = {
390 .name = "apic_sipi",
391 .version_id = 1,
392 .minimum_version_id = 1,
393 .needed = apic_common_sipi_needed,
394 .fields = (VMStateField[]) {
395 VMSTATE_INT32(sipi_vector, APICCommonState),
396 VMSTATE_INT32(wait_for_sipi, APICCommonState),
397 VMSTATE_END_OF_LIST()
398 }
399};
400
401static const VMStateDescription vmstate_apic_common = {
402 .name = "apic",
403 .version_id = 3,
404 .minimum_version_id = 3,
405 .minimum_version_id_old = 1,
406 .load_state_old = apic_load_old,
407 .pre_load = apic_pre_load,
408 .pre_save = apic_dispatch_pre_save,
409 .post_load = apic_dispatch_post_load,
410 .fields = (VMStateField[]) {
411 VMSTATE_UINT32(apicbase, APICCommonState),
412 VMSTATE_UINT8(id, APICCommonState),
413 VMSTATE_UINT8(arb_id, APICCommonState),
414 VMSTATE_UINT8(tpr, APICCommonState),
415 VMSTATE_UINT32(spurious_vec, APICCommonState),
416 VMSTATE_UINT8(log_dest, APICCommonState),
417 VMSTATE_UINT8(dest_mode, APICCommonState),
418 VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
419 VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
420 VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
421 VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
422 VMSTATE_UINT32(esr, APICCommonState),
423 VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
424 VMSTATE_UINT32(divide_conf, APICCommonState),
425 VMSTATE_INT32(count_shift, APICCommonState),
426 VMSTATE_UINT32(initial_count, APICCommonState),
427 VMSTATE_INT64(initial_count_load_time, APICCommonState),
428 VMSTATE_INT64(next_time, APICCommonState),
429 VMSTATE_INT64(timer_expiry,
430 APICCommonState),
431 VMSTATE_END_OF_LIST()
432 },
433 .subsections = (const VMStateDescription*[]) {
434 &vmstate_apic_common_sipi,
435 NULL
436 }
437};
438
439static Property apic_properties_common[] = {
440 DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
441 DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
442 true),
443 DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
444 false),
445 DEFINE_PROP_END_OF_LIST(),
446};
447
448static void apic_common_get_id(Object *obj, Visitor *v, const char *name,
449 void *opaque, Error **errp)
450{
451 APICCommonState *s = APIC_COMMON(obj);
452 int64_t value;
453
454 value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id;
455 visit_type_int(v, name, &value, errp);
456}
457
458static void apic_common_set_id(Object *obj, Visitor *v, const char *name,
459 void *opaque, Error **errp)
460{
461 APICCommonState *s = APIC_COMMON(obj);
462 DeviceState *dev = DEVICE(obj);
463 Error *local_err = NULL;
464 int64_t value;
465
466 if (dev->realized) {
467 qdev_prop_set_after_realize(dev, name, errp);
468 return;
469 }
470
471 visit_type_int(v, name, &value, &local_err);
472 if (local_err) {
473 error_propagate(errp, local_err);
474 return;
475 }
476
477 s->initial_apic_id = value;
478 s->id = (uint8_t)value;
479}
480
481static void apic_common_initfn(Object *obj)
482{
483 APICCommonState *s = APIC_COMMON(obj);
484
485 s->id = s->initial_apic_id = -1;
486 object_property_add(obj, "id", "int",
487 apic_common_get_id,
488 apic_common_set_id, NULL, NULL, NULL);
489}
490
491static void apic_common_class_init(ObjectClass *klass, void *data)
492{
493 DeviceClass *dc = DEVICE_CLASS(klass);
494
495 dc->reset = apic_reset_common;
496 dc->props = apic_properties_common;
497 dc->realize = apic_common_realize;
498 dc->unrealize = apic_common_unrealize;
499
500
501
502
503 dc->cannot_instantiate_with_device_add_yet = true;
504}
505
506static const TypeInfo apic_common_type = {
507 .name = TYPE_APIC_COMMON,
508 .parent = TYPE_DEVICE,
509 .instance_size = sizeof(APICCommonState),
510 .instance_init = apic_common_initfn,
511 .class_size = sizeof(APICCommonClass),
512 .class_init = apic_common_class_init,
513 .abstract = true,
514};
515
516static void apic_common_register_types(void)
517{
518 type_register_static(&apic_common_type);
519}
520
521type_init(apic_common_register_types)
522