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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qom/cpu.h"
27#include "hw/intc/arm_gicv3_common.h"
28#include "gicv3_internal.h"
29#include "hw/arm/linux-boot-if.h"
30
31static void gicv3_pre_save(void *opaque)
32{
33 GICv3State *s = (GICv3State *)opaque;
34 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
35
36 if (c->pre_save) {
37 c->pre_save(s);
38 }
39}
40
41static int gicv3_post_load(void *opaque, int version_id)
42{
43 GICv3State *s = (GICv3State *)opaque;
44 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
45
46 if (c->post_load) {
47 c->post_load(s);
48 }
49 return 0;
50}
51
52static const VMStateDescription vmstate_gicv3_cpu = {
53 .name = "arm_gicv3_cpu",
54 .version_id = 1,
55 .minimum_version_id = 1,
56 .fields = (VMStateField[]) {
57 VMSTATE_UINT32(level, GICv3CPUState),
58 VMSTATE_UINT32(gicr_ctlr, GICv3CPUState),
59 VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2),
60 VMSTATE_UINT32(gicr_waker, GICv3CPUState),
61 VMSTATE_UINT64(gicr_propbaser, GICv3CPUState),
62 VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState),
63 VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState),
64 VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState),
65 VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState),
66 VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState),
67 VMSTATE_UINT32(edge_trigger, GICv3CPUState),
68 VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState),
69 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
70 VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL),
71 VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2),
72 VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState),
73 VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3),
74 VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4),
75 VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3),
76 VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState),
77 VMSTATE_END_OF_LIST()
78 }
79};
80
81static const VMStateDescription vmstate_gicv3 = {
82 .name = "arm_gicv3",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .pre_save = gicv3_pre_save,
86 .post_load = gicv3_post_load,
87 .fields = (VMStateField[]) {
88 VMSTATE_UINT32(gicd_ctlr, GICv3State),
89 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
90 VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE),
91 VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE),
92 VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE),
93 VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE),
94 VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE),
95 VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE),
96 VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE),
97 VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ),
98 VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ),
99 VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State,
100 DIV_ROUND_UP(GICV3_MAXIRQ, 16)),
101 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
102 vmstate_gicv3_cpu, GICv3CPUState),
103 VMSTATE_END_OF_LIST()
104 }
105};
106
107void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
108 const MemoryRegionOps *ops)
109{
110 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
111 int i;
112
113
114
115
116
117
118
119
120 i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
121 qdev_init_gpio_in(DEVICE(s), handler, i);
122
123 for (i = 0; i < s->num_cpu; i++) {
124 sysbus_init_irq(sbd, &s->cpu[i].parent_irq);
125 }
126 for (i = 0; i < s->num_cpu; i++) {
127 sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
128 }
129
130 memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
131 "gicv3_dist", 0x10000);
132 memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s,
133 "gicv3_redist", 0x20000 * s->num_cpu);
134
135 sysbus_init_mmio(sbd, &s->iomem_dist);
136 sysbus_init_mmio(sbd, &s->iomem_redist);
137}
138
139static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
140{
141 GICv3State *s = ARM_GICV3_COMMON(dev);
142 int i;
143
144
145
146
147
148
149 if (s->revision != 3) {
150 error_setg(errp, "unsupported GIC revision %d", s->revision);
151 return;
152 }
153
154 if (s->num_irq > GICV3_MAXIRQ) {
155 error_setg(errp,
156 "requested %u interrupt lines exceeds GIC maximum %d",
157 s->num_irq, GICV3_MAXIRQ);
158 return;
159 }
160 if (s->num_irq < GIC_INTERNAL) {
161 error_setg(errp,
162 "requested %u interrupt lines is below GIC minimum %d",
163 s->num_irq, GIC_INTERNAL);
164 return;
165 }
166
167
168
169
170
171
172 if (s->num_irq % 32) {
173 error_setg(errp,
174 "%d interrupt lines unsupported: not divisible by 32",
175 s->num_irq);
176 return;
177 }
178
179 s->cpu = g_new0(GICv3CPUState, s->num_cpu);
180
181 for (i = 0; i < s->num_cpu; i++) {
182 CPUState *cpu = qemu_get_cpu(i);
183 uint64_t cpu_affid;
184 int last;
185
186 s->cpu[i].cpu = cpu;
187 s->cpu[i].gic = s;
188
189
190
191
192
193
194
195
196
197
198
199
200
201 cpu_affid = object_property_get_int(OBJECT(cpu), "mp-affinity", NULL);
202 last = (i == s->num_cpu - 1);
203
204
205
206
207 cpu_affid = (cpu_affid & 0xFF00000000ULL >> 8) | (cpu_affid & 0xFFFFFF);
208 s->cpu[i].gicr_typer = (cpu_affid << 32) |
209 (1 << 24) |
210 (i << 8) |
211 (last << 4);
212 }
213}
214
215static void arm_gicv3_common_reset(DeviceState *dev)
216{
217 GICv3State *s = ARM_GICV3_COMMON(dev);
218 int i;
219
220 for (i = 0; i < s->num_cpu; i++) {
221 GICv3CPUState *cs = &s->cpu[i];
222
223 cs->level = 0;
224 cs->gicr_ctlr = 0;
225 cs->gicr_statusr[GICV3_S] = 0;
226 cs->gicr_statusr[GICV3_NS] = 0;
227 cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;
228 cs->gicr_propbaser = 0;
229 cs->gicr_pendbaser = 0;
230
231
232
233
234
235 if (s->irq_reset_nonsecure) {
236 cs->gicr_igroupr0 = 0xffffffff;
237 } else {
238 cs->gicr_igroupr0 = 0;
239 }
240
241 cs->gicr_ienabler0 = 0;
242 cs->gicr_ipendr0 = 0;
243 cs->gicr_iactiver0 = 0;
244 cs->edge_trigger = 0xffff;
245 cs->gicr_igrpmodr0 = 0;
246 cs->gicr_nsacr = 0;
247 memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
248
249 cs->hppi.prio = 0xff;
250
251
252
253
254 }
255
256
257 if (s->security_extn) {
258 s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS;
259 } else {
260 s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE;
261 }
262
263 s->gicd_statusr[GICV3_S] = 0;
264 s->gicd_statusr[GICV3_NS] = 0;
265
266 memset(s->group, 0, sizeof(s->group));
267 memset(s->grpmod, 0, sizeof(s->grpmod));
268 memset(s->enabled, 0, sizeof(s->enabled));
269 memset(s->pending, 0, sizeof(s->pending));
270 memset(s->active, 0, sizeof(s->active));
271 memset(s->level, 0, sizeof(s->level));
272 memset(s->edge_trigger, 0, sizeof(s->edge_trigger));
273 memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority));
274 memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter));
275 memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr));
276
277
278
279
280
281
282 gicv3_cache_all_target_cpustates(s);
283
284 if (s->irq_reset_nonsecure) {
285
286
287
288
289
290 for (i = GIC_INTERNAL; i < s->num_irq; i++) {
291 gicv3_gicd_group_set(s, i);
292 }
293 }
294}
295
296static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
297 bool secure_boot)
298{
299 GICv3State *s = ARM_GICV3_COMMON(obj);
300
301 if (s->security_extn && !secure_boot) {
302
303
304
305
306
307
308
309 s->irq_reset_nonsecure = true;
310 }
311}
312
313static Property arm_gicv3_common_properties[] = {
314 DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
315 DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
316 DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
317 DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
318 DEFINE_PROP_END_OF_LIST(),
319};
320
321static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
322{
323 DeviceClass *dc = DEVICE_CLASS(klass);
324 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
325
326 dc->reset = arm_gicv3_common_reset;
327 dc->realize = arm_gicv3_common_realize;
328 dc->props = arm_gicv3_common_properties;
329 dc->vmsd = &vmstate_gicv3;
330 albifc->arm_linux_init = arm_gic_common_linux_init;
331}
332
333static const TypeInfo arm_gicv3_common_type = {
334 .name = TYPE_ARM_GICV3_COMMON,
335 .parent = TYPE_SYS_BUS_DEVICE,
336 .instance_size = sizeof(GICv3State),
337 .class_size = sizeof(ARMGICv3CommonClass),
338 .class_init = arm_gicv3_common_class_init,
339 .abstract = true,
340 .interfaces = (InterfaceInfo []) {
341 { TYPE_ARM_LINUX_BOOT_IF },
342 { },
343 },
344};
345
346static void register_types(void)
347{
348 type_register_static(&arm_gicv3_common_type);
349}
350
351type_init(register_types)
352