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20#include "qemu/osdep.h"
21#include "qemu-common.h"
22#include "cpu.h"
23#include "hw/sysbus.h"
24#include "hw/hw.h"
25#include "hw/block/flash.h"
26#include "hw/devices.h"
27#include "hw/boards.h"
28#include "hw/loader.h"
29#include "sysemu/block-backend.h"
30#include "elf.h"
31#include "lm32_hwsetup.h"
32#include "lm32.h"
33#include "exec/address-spaces.h"
34#include "sysemu/sysemu.h"
35
36typedef struct {
37 LM32CPU *cpu;
38 hwaddr bootstrap_pc;
39 hwaddr flash_base;
40 hwaddr hwsetup_base;
41 hwaddr initrd_base;
42 size_t initrd_size;
43 hwaddr cmdline_base;
44} ResetInfo;
45
46static void cpu_irq_handler(void *opaque, int irq, int level)
47{
48 LM32CPU *cpu = opaque;
49 CPUState *cs = CPU(cpu);
50
51 if (level) {
52 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
53 } else {
54 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
55 }
56}
57
58static void main_cpu_reset(void *opaque)
59{
60 ResetInfo *reset_info = opaque;
61 CPULM32State *env = &reset_info->cpu->env;
62
63 cpu_reset(CPU(reset_info->cpu));
64
65
66 env->pc = (uint32_t)reset_info->bootstrap_pc;
67 env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
68 env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
69 env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
70 env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
71 reset_info->initrd_size);
72 env->eba = reset_info->flash_base;
73 env->deba = reset_info->flash_base;
74}
75
76static void lm32_evr_init(MachineState *machine)
77{
78 const char *cpu_model = machine->cpu_model;
79 const char *kernel_filename = machine->kernel_filename;
80 LM32CPU *cpu;
81 CPULM32State *env;
82 DriveInfo *dinfo;
83 MemoryRegion *address_space_mem = get_system_memory();
84 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
85 qemu_irq irq[32];
86 ResetInfo *reset_info;
87 int i;
88
89
90 hwaddr flash_base = 0x04000000;
91 size_t flash_sector_size = 256 * 1024;
92 size_t flash_size = 32 * 1024 * 1024;
93 hwaddr ram_base = 0x08000000;
94 size_t ram_size = 64 * 1024 * 1024;
95 hwaddr timer0_base = 0x80002000;
96 hwaddr uart0_base = 0x80006000;
97 hwaddr timer1_base = 0x8000a000;
98 int uart0_irq = 0;
99 int timer0_irq = 1;
100 int timer1_irq = 3;
101
102 reset_info = g_malloc0(sizeof(ResetInfo));
103
104 if (cpu_model == NULL) {
105 cpu_model = "lm32-full";
106 }
107 cpu = cpu_lm32_init(cpu_model);
108 if (cpu == NULL) {
109 fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
110 exit(1);
111 }
112
113 env = &cpu->env;
114 reset_info->cpu = cpu;
115
116 reset_info->flash_base = flash_base;
117
118 memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
119 ram_size);
120 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
121
122 dinfo = drive_get(IF_PFLASH, 0, 0);
123
124 pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
125 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
126 flash_sector_size, flash_size / flash_sector_size,
127 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
128
129
130 env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
131 for (i = 0; i < 32; i++) {
132 irq[i] = qdev_get_gpio_in(env->pic_state, i);
133 }
134
135 lm32_uart_create(uart0_base, irq[uart0_irq], serial_hds[0]);
136 sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
137 sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
138
139
140 env->juart_state = lm32_juart_init(serial_hds[1]);
141
142 reset_info->bootstrap_pc = flash_base;
143
144 if (kernel_filename) {
145 uint64_t entry;
146 int kernel_size;
147
148 kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
149 1, EM_LATTICEMICO32, 0, 0);
150 reset_info->bootstrap_pc = entry;
151
152 if (kernel_size < 0) {
153 kernel_size = load_image_targphys(kernel_filename, ram_base,
154 ram_size);
155 reset_info->bootstrap_pc = ram_base;
156 }
157
158 if (kernel_size < 0) {
159 fprintf(stderr, "qemu: could not load kernel '%s'\n",
160 kernel_filename);
161 exit(1);
162 }
163 }
164
165 qemu_register_reset(main_cpu_reset, reset_info);
166}
167
168static void lm32_uclinux_init(MachineState *machine)
169{
170 const char *cpu_model = machine->cpu_model;
171 const char *kernel_filename = machine->kernel_filename;
172 const char *kernel_cmdline = machine->kernel_cmdline;
173 const char *initrd_filename = machine->initrd_filename;
174 LM32CPU *cpu;
175 CPULM32State *env;
176 DriveInfo *dinfo;
177 MemoryRegion *address_space_mem = get_system_memory();
178 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
179 qemu_irq irq[32];
180 HWSetup *hw;
181 ResetInfo *reset_info;
182 int i;
183
184
185 hwaddr flash_base = 0x04000000;
186 size_t flash_sector_size = 256 * 1024;
187 size_t flash_size = 32 * 1024 * 1024;
188 hwaddr ram_base = 0x08000000;
189 size_t ram_size = 64 * 1024 * 1024;
190 hwaddr uart0_base = 0x80000000;
191 hwaddr timer0_base = 0x80002000;
192 hwaddr timer1_base = 0x80010000;
193 hwaddr timer2_base = 0x80012000;
194 int uart0_irq = 0;
195 int timer0_irq = 1;
196 int timer1_irq = 20;
197 int timer2_irq = 21;
198 hwaddr hwsetup_base = 0x0bffe000;
199 hwaddr cmdline_base = 0x0bfff000;
200 hwaddr initrd_base = 0x08400000;
201 size_t initrd_max = 0x01000000;
202
203 reset_info = g_malloc0(sizeof(ResetInfo));
204
205 if (cpu_model == NULL) {
206 cpu_model = "lm32-full";
207 }
208 cpu = cpu_lm32_init(cpu_model);
209 if (cpu == NULL) {
210 fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
211 exit(1);
212 }
213
214 env = &cpu->env;
215 reset_info->cpu = cpu;
216
217 reset_info->flash_base = flash_base;
218
219 memory_region_allocate_system_memory(phys_ram, NULL,
220 "lm32_uclinux.sdram", ram_size);
221 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
222
223 dinfo = drive_get(IF_PFLASH, 0, 0);
224
225 pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
226 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
227 flash_sector_size, flash_size / flash_sector_size,
228 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
229
230
231 env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
232 for (i = 0; i < 32; i++) {
233 irq[i] = qdev_get_gpio_in(env->pic_state, i);
234 }
235
236 lm32_uart_create(uart0_base, irq[uart0_irq], serial_hds[0]);
237 sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
238 sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
239 sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
240
241
242 env->juart_state = lm32_juart_init(serial_hds[1]);
243
244 reset_info->bootstrap_pc = flash_base;
245
246 if (kernel_filename) {
247 uint64_t entry;
248 int kernel_size;
249
250 kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
251 1, EM_LATTICEMICO32, 0, 0);
252 reset_info->bootstrap_pc = entry;
253
254 if (kernel_size < 0) {
255 kernel_size = load_image_targphys(kernel_filename, ram_base,
256 ram_size);
257 reset_info->bootstrap_pc = ram_base;
258 }
259
260 if (kernel_size < 0) {
261 fprintf(stderr, "qemu: could not load kernel '%s'\n",
262 kernel_filename);
263 exit(1);
264 }
265 }
266
267
268 hw = hwsetup_init();
269 hwsetup_add_cpu(hw, "LM32", 75000000);
270 hwsetup_add_flash(hw, "flash", flash_base, flash_size);
271 hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
272 hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
273 hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
274 hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
275 hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
276 hwsetup_add_trailer(hw);
277 hwsetup_create_rom(hw, hwsetup_base);
278 hwsetup_free(hw);
279
280 reset_info->hwsetup_base = hwsetup_base;
281
282 if (kernel_cmdline && strlen(kernel_cmdline)) {
283 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
284 kernel_cmdline);
285 reset_info->cmdline_base = cmdline_base;
286 }
287
288 if (initrd_filename) {
289 size_t initrd_size;
290 initrd_size = load_image_targphys(initrd_filename, initrd_base,
291 initrd_max);
292 reset_info->initrd_base = initrd_base;
293 reset_info->initrd_size = initrd_size;
294 }
295
296 qemu_register_reset(main_cpu_reset, reset_info);
297}
298
299static void lm32_evr_class_init(ObjectClass *oc, void *data)
300{
301 MachineClass *mc = MACHINE_CLASS(oc);
302
303 mc->desc = "LatticeMico32 EVR32 eval system";
304 mc->init = lm32_evr_init;
305 mc->is_default = 1;
306}
307
308static const TypeInfo lm32_evr_type = {
309 .name = MACHINE_TYPE_NAME("lm32-evr"),
310 .parent = TYPE_MACHINE,
311 .class_init = lm32_evr_class_init,
312};
313
314static void lm32_uclinux_class_init(ObjectClass *oc, void *data)
315{
316 MachineClass *mc = MACHINE_CLASS(oc);
317
318 mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
319 mc->init = lm32_uclinux_init;
320 mc->is_default = 0;
321}
322
323static const TypeInfo lm32_uclinux_type = {
324 .name = MACHINE_TYPE_NAME("lm32-uclinux"),
325 .parent = TYPE_MACHINE,
326 .class_init = lm32_uclinux_class_init,
327};
328
329static void lm32_machine_init(void)
330{
331 type_register_static(&lm32_evr_type);
332 type_register_static(&lm32_uclinux_type);
333}
334
335type_init(lm32_machine_init)
336
