qemu/hw/mips/gt64xxx_pci.c
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   1/*
   2 * QEMU GT64120 PCI host
   3 *
   4 * Copyright (c) 2006,2007 Aurelien Jarno
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "hw/hw.h"
  27#include "hw/mips/mips.h"
  28#include "hw/pci/pci.h"
  29#include "hw/pci/pci_host.h"
  30#include "hw/i386/pc.h"
  31#include "exec/address-spaces.h"
  32
  33//#define DEBUG
  34
  35#ifdef DEBUG
  36#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  37#else
  38#define DPRINTF(fmt, ...)
  39#endif
  40
  41#define GT_REGS                 (0x1000 >> 2)
  42
  43/* CPU Configuration */
  44#define GT_CPU                  (0x000 >> 2)
  45#define GT_MULTI                (0x120 >> 2)
  46
  47/* CPU Address Decode */
  48#define GT_SCS10LD              (0x008 >> 2)
  49#define GT_SCS10HD              (0x010 >> 2)
  50#define GT_SCS32LD              (0x018 >> 2)
  51#define GT_SCS32HD              (0x020 >> 2)
  52#define GT_CS20LD               (0x028 >> 2)
  53#define GT_CS20HD               (0x030 >> 2)
  54#define GT_CS3BOOTLD            (0x038 >> 2)
  55#define GT_CS3BOOTHD            (0x040 >> 2)
  56#define GT_PCI0IOLD             (0x048 >> 2)
  57#define GT_PCI0IOHD             (0x050 >> 2)
  58#define GT_PCI0M0LD             (0x058 >> 2)
  59#define GT_PCI0M0HD             (0x060 >> 2)
  60#define GT_PCI0M1LD             (0x080 >> 2)
  61#define GT_PCI0M1HD             (0x088 >> 2)
  62#define GT_PCI1IOLD             (0x090 >> 2)
  63#define GT_PCI1IOHD             (0x098 >> 2)
  64#define GT_PCI1M0LD             (0x0a0 >> 2)
  65#define GT_PCI1M0HD             (0x0a8 >> 2)
  66#define GT_PCI1M1LD             (0x0b0 >> 2)
  67#define GT_PCI1M1HD             (0x0b8 >> 2)
  68#define GT_ISD                  (0x068 >> 2)
  69
  70#define GT_SCS10AR              (0x0d0 >> 2)
  71#define GT_SCS32AR              (0x0d8 >> 2)
  72#define GT_CS20R                (0x0e0 >> 2)
  73#define GT_CS3BOOTR             (0x0e8 >> 2)
  74
  75#define GT_PCI0IOREMAP          (0x0f0 >> 2)
  76#define GT_PCI0M0REMAP          (0x0f8 >> 2)
  77#define GT_PCI0M1REMAP          (0x100 >> 2)
  78#define GT_PCI1IOREMAP          (0x108 >> 2)
  79#define GT_PCI1M0REMAP          (0x110 >> 2)
  80#define GT_PCI1M1REMAP          (0x118 >> 2)
  81
  82/* CPU Error Report */
  83#define GT_CPUERR_ADDRLO        (0x070 >> 2)
  84#define GT_CPUERR_ADDRHI        (0x078 >> 2)
  85#define GT_CPUERR_DATALO        (0x128 >> 2)            /* GT-64120A only  */
  86#define GT_CPUERR_DATAHI        (0x130 >> 2)            /* GT-64120A only  */
  87#define GT_CPUERR_PARITY        (0x138 >> 2)            /* GT-64120A only  */
  88
  89/* CPU Sync Barrier */
  90#define GT_PCI0SYNC             (0x0c0 >> 2)
  91#define GT_PCI1SYNC             (0x0c8 >> 2)
  92
  93/* SDRAM and Device Address Decode */
  94#define GT_SCS0LD               (0x400 >> 2)
  95#define GT_SCS0HD               (0x404 >> 2)
  96#define GT_SCS1LD               (0x408 >> 2)
  97#define GT_SCS1HD               (0x40c >> 2)
  98#define GT_SCS2LD               (0x410 >> 2)
  99#define GT_SCS2HD               (0x414 >> 2)
 100#define GT_SCS3LD               (0x418 >> 2)
 101#define GT_SCS3HD               (0x41c >> 2)
 102#define GT_CS0LD                (0x420 >> 2)
 103#define GT_CS0HD                (0x424 >> 2)
 104#define GT_CS1LD                (0x428 >> 2)
 105#define GT_CS1HD                (0x42c >> 2)
 106#define GT_CS2LD                (0x430 >> 2)
 107#define GT_CS2HD                (0x434 >> 2)
 108#define GT_CS3LD                (0x438 >> 2)
 109#define GT_CS3HD                (0x43c >> 2)
 110#define GT_BOOTLD               (0x440 >> 2)
 111#define GT_BOOTHD               (0x444 >> 2)
 112#define GT_ADERR                (0x470 >> 2)
 113
 114/* SDRAM Configuration */
 115#define GT_SDRAM_CFG            (0x448 >> 2)
 116#define GT_SDRAM_OPMODE         (0x474 >> 2)
 117#define GT_SDRAM_BM             (0x478 >> 2)
 118#define GT_SDRAM_ADDRDECODE     (0x47c >> 2)
 119
 120/* SDRAM Parameters */
 121#define GT_SDRAM_B0             (0x44c >> 2)
 122#define GT_SDRAM_B1             (0x450 >> 2)
 123#define GT_SDRAM_B2             (0x454 >> 2)
 124#define GT_SDRAM_B3             (0x458 >> 2)
 125
 126/* Device Parameters */
 127#define GT_DEV_B0               (0x45c >> 2)
 128#define GT_DEV_B1               (0x460 >> 2)
 129#define GT_DEV_B2               (0x464 >> 2)
 130#define GT_DEV_B3               (0x468 >> 2)
 131#define GT_DEV_BOOT             (0x46c >> 2)
 132
 133/* ECC */
 134#define GT_ECC_ERRDATALO        (0x480 >> 2)            /* GT-64120A only  */
 135#define GT_ECC_ERRDATAHI        (0x484 >> 2)            /* GT-64120A only  */
 136#define GT_ECC_MEM              (0x488 >> 2)            /* GT-64120A only  */
 137#define GT_ECC_CALC             (0x48c >> 2)            /* GT-64120A only  */
 138#define GT_ECC_ERRADDR          (0x490 >> 2)            /* GT-64120A only  */
 139
 140/* DMA Record */
 141#define GT_DMA0_CNT             (0x800 >> 2)
 142#define GT_DMA1_CNT             (0x804 >> 2)
 143#define GT_DMA2_CNT             (0x808 >> 2)
 144#define GT_DMA3_CNT             (0x80c >> 2)
 145#define GT_DMA0_SA              (0x810 >> 2)
 146#define GT_DMA1_SA              (0x814 >> 2)
 147#define GT_DMA2_SA              (0x818 >> 2)
 148#define GT_DMA3_SA              (0x81c >> 2)
 149#define GT_DMA0_DA              (0x820 >> 2)
 150#define GT_DMA1_DA              (0x824 >> 2)
 151#define GT_DMA2_DA              (0x828 >> 2)
 152#define GT_DMA3_DA              (0x82c >> 2)
 153#define GT_DMA0_NEXT            (0x830 >> 2)
 154#define GT_DMA1_NEXT            (0x834 >> 2)
 155#define GT_DMA2_NEXT            (0x838 >> 2)
 156#define GT_DMA3_NEXT            (0x83c >> 2)
 157#define GT_DMA0_CUR             (0x870 >> 2)
 158#define GT_DMA1_CUR             (0x874 >> 2)
 159#define GT_DMA2_CUR             (0x878 >> 2)
 160#define GT_DMA3_CUR             (0x87c >> 2)
 161
 162/* DMA Channel Control */
 163#define GT_DMA0_CTRL            (0x840 >> 2)
 164#define GT_DMA1_CTRL            (0x844 >> 2)
 165#define GT_DMA2_CTRL            (0x848 >> 2)
 166#define GT_DMA3_CTRL            (0x84c >> 2)
 167
 168/* DMA Arbiter */
 169#define GT_DMA_ARB              (0x860 >> 2)
 170
 171/* Timer/Counter */
 172#define GT_TC0                  (0x850 >> 2)
 173#define GT_TC1                  (0x854 >> 2)
 174#define GT_TC2                  (0x858 >> 2)
 175#define GT_TC3                  (0x85c >> 2)
 176#define GT_TC_CONTROL           (0x864 >> 2)
 177
 178/* PCI Internal */
 179#define GT_PCI0_CMD             (0xc00 >> 2)
 180#define GT_PCI0_TOR             (0xc04 >> 2)
 181#define GT_PCI0_BS_SCS10        (0xc08 >> 2)
 182#define GT_PCI0_BS_SCS32        (0xc0c >> 2)
 183#define GT_PCI0_BS_CS20         (0xc10 >> 2)
 184#define GT_PCI0_BS_CS3BT        (0xc14 >> 2)
 185#define GT_PCI1_IACK            (0xc30 >> 2)
 186#define GT_PCI0_IACK            (0xc34 >> 2)
 187#define GT_PCI0_BARE            (0xc3c >> 2)
 188#define GT_PCI0_PREFMBR         (0xc40 >> 2)
 189#define GT_PCI0_SCS10_BAR       (0xc48 >> 2)
 190#define GT_PCI0_SCS32_BAR       (0xc4c >> 2)
 191#define GT_PCI0_CS20_BAR        (0xc50 >> 2)
 192#define GT_PCI0_CS3BT_BAR       (0xc54 >> 2)
 193#define GT_PCI0_SSCS10_BAR      (0xc58 >> 2)
 194#define GT_PCI0_SSCS32_BAR      (0xc5c >> 2)
 195#define GT_PCI0_SCS3BT_BAR      (0xc64 >> 2)
 196#define GT_PCI1_CMD             (0xc80 >> 2)
 197#define GT_PCI1_TOR             (0xc84 >> 2)
 198#define GT_PCI1_BS_SCS10        (0xc88 >> 2)
 199#define GT_PCI1_BS_SCS32        (0xc8c >> 2)
 200#define GT_PCI1_BS_CS20         (0xc90 >> 2)
 201#define GT_PCI1_BS_CS3BT        (0xc94 >> 2)
 202#define GT_PCI1_BARE            (0xcbc >> 2)
 203#define GT_PCI1_PREFMBR         (0xcc0 >> 2)
 204#define GT_PCI1_SCS10_BAR       (0xcc8 >> 2)
 205#define GT_PCI1_SCS32_BAR       (0xccc >> 2)
 206#define GT_PCI1_CS20_BAR        (0xcd0 >> 2)
 207#define GT_PCI1_CS3BT_BAR       (0xcd4 >> 2)
 208#define GT_PCI1_SSCS10_BAR      (0xcd8 >> 2)
 209#define GT_PCI1_SSCS32_BAR      (0xcdc >> 2)
 210#define GT_PCI1_SCS3BT_BAR      (0xce4 >> 2)
 211#define GT_PCI1_CFGADDR         (0xcf0 >> 2)
 212#define GT_PCI1_CFGDATA         (0xcf4 >> 2)
 213#define GT_PCI0_CFGADDR         (0xcf8 >> 2)
 214#define GT_PCI0_CFGDATA         (0xcfc >> 2)
 215
 216/* Interrupts */
 217#define GT_INTRCAUSE            (0xc18 >> 2)
 218#define GT_INTRMASK             (0xc1c >> 2)
 219#define GT_PCI0_ICMASK          (0xc24 >> 2)
 220#define GT_PCI0_SERR0MASK       (0xc28 >> 2)
 221#define GT_CPU_INTSEL           (0xc70 >> 2)
 222#define GT_PCI0_INTSEL          (0xc74 >> 2)
 223#define GT_HINTRCAUSE           (0xc98 >> 2)
 224#define GT_HINTRMASK            (0xc9c >> 2)
 225#define GT_PCI0_HICMASK         (0xca4 >> 2)
 226#define GT_PCI1_SERR1MASK       (0xca8 >> 2)
 227
 228#define PCI_MAPPING_ENTRY(regname)            \
 229    hwaddr regname ##_start;      \
 230    hwaddr regname ##_length;     \
 231    MemoryRegion regname ##_mem
 232
 233#define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
 234
 235#define GT64120_PCI_HOST_BRIDGE(obj) \
 236    OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE)
 237
 238typedef struct GT64120State {
 239    PCIHostState parent_obj;
 240
 241    uint32_t regs[GT_REGS];
 242    PCI_MAPPING_ENTRY(PCI0IO);
 243    PCI_MAPPING_ENTRY(PCI0M0);
 244    PCI_MAPPING_ENTRY(PCI0M1);
 245    PCI_MAPPING_ENTRY(ISD);
 246    MemoryRegion pci0_mem;
 247    AddressSpace pci0_mem_as;
 248} GT64120State;
 249
 250/* Adjust range to avoid touching space which isn't mappable via PCI */
 251/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
 252                                    0x1fc00000 - 0x1fd00000  */
 253static void check_reserved_space (hwaddr *start,
 254                                  hwaddr *length)
 255{
 256    hwaddr begin = *start;
 257    hwaddr end = *start + *length;
 258
 259    if (end >= 0x1e000000LL && end < 0x1f100000LL)
 260        end = 0x1e000000LL;
 261    if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
 262        begin = 0x1f100000LL;
 263    if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
 264        end = 0x1fc00000LL;
 265    if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
 266        begin = 0x1fd00000LL;
 267    /* XXX: This is broken when a reserved range splits the requested range */
 268    if (end >= 0x1f100000LL && begin < 0x1e000000LL)
 269        end = 0x1e000000LL;
 270    if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
 271        end = 0x1fc00000LL;
 272
 273    *start = begin;
 274    *length = end - begin;
 275}
 276
 277static void gt64120_isd_mapping(GT64120State *s)
 278{
 279    /* Bits 14:0 of ISD map to bits 35:21 of the start address.  */
 280    hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
 281    hwaddr length = 0x1000;
 282
 283    if (s->ISD_length) {
 284        memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
 285    }
 286    check_reserved_space(&start, &length);
 287    length = 0x1000;
 288    /* Map new address */
 289    DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx
 290        " -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n",
 291        s->ISD_length, s->ISD_start, length, start);
 292    s->ISD_start = start;
 293    s->ISD_length = length;
 294    memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
 295}
 296
 297static void gt64120_pci_mapping(GT64120State *s)
 298{
 299    /* Update PCI0IO mapping */
 300    if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
 301        /* Unmap old IO address */
 302        if (s->PCI0IO_length) {
 303            memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
 304            object_unparent(OBJECT(&s->PCI0IO_mem));
 305        }
 306        /* Map new IO address */
 307        s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
 308        s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
 309                            (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
 310        if (s->PCI0IO_length) {
 311            memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
 312                                     get_system_io(), 0, s->PCI0IO_length);
 313            memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
 314                                        &s->PCI0IO_mem);
 315        }
 316    }
 317
 318    /* Update PCI0M0 mapping */
 319    if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
 320        /* Unmap old MEM address */
 321        if (s->PCI0M0_length) {
 322            memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
 323            object_unparent(OBJECT(&s->PCI0M0_mem));
 324        }
 325        /* Map new mem address */
 326        s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
 327        s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
 328                            (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
 329        if (s->PCI0M0_length) {
 330            memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
 331                                     &s->pci0_mem, s->PCI0M0_start,
 332                                     s->PCI0M0_length);
 333            memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
 334                                        &s->PCI0M0_mem);
 335        }
 336    }
 337
 338    /* Update PCI0M1 mapping */
 339    if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
 340        /* Unmap old MEM address */
 341        if (s->PCI0M1_length) {
 342            memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
 343            object_unparent(OBJECT(&s->PCI0M1_mem));
 344        }
 345        /* Map new mem address */
 346        s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
 347        s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
 348                            (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
 349        if (s->PCI0M1_length) {
 350            memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
 351                                     &s->pci0_mem, s->PCI0M1_start,
 352                                     s->PCI0M1_length);
 353            memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
 354                                        &s->PCI0M1_mem);
 355        }
 356    }
 357}
 358
 359static int gt64120_post_load(void *opaque, int version_id)
 360{
 361    GT64120State *s = opaque;
 362
 363    gt64120_isd_mapping(s);
 364    gt64120_pci_mapping(s);
 365
 366    return 0;
 367}
 368
 369static const VMStateDescription vmstate_gt64120 = {
 370    .name = "gt64120",
 371    .version_id = 1,
 372    .minimum_version_id = 1,
 373    .post_load = gt64120_post_load,
 374    .fields = (VMStateField[]) {
 375        VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
 376        VMSTATE_END_OF_LIST()
 377    }
 378};
 379
 380static void gt64120_writel (void *opaque, hwaddr addr,
 381                            uint64_t val, unsigned size)
 382{
 383    GT64120State *s = opaque;
 384    PCIHostState *phb = PCI_HOST_BRIDGE(s);
 385    uint32_t saddr;
 386
 387    if (!(s->regs[GT_CPU] & 0x00001000))
 388        val = bswap32(val);
 389
 390    saddr = (addr & 0xfff) >> 2;
 391    switch (saddr) {
 392
 393    /* CPU Configuration */
 394    case GT_CPU:
 395        s->regs[GT_CPU] = val;
 396        break;
 397    case GT_MULTI:
 398        /* Read-only register as only one GT64xxx is present on the CPU bus */
 399        break;
 400
 401    /* CPU Address Decode */
 402    case GT_PCI0IOLD:
 403        s->regs[GT_PCI0IOLD]    = val & 0x00007fff;
 404        s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
 405        gt64120_pci_mapping(s);
 406        break;
 407    case GT_PCI0M0LD:
 408        s->regs[GT_PCI0M0LD]    = val & 0x00007fff;
 409        s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
 410        gt64120_pci_mapping(s);
 411        break;
 412    case GT_PCI0M1LD:
 413        s->regs[GT_PCI0M1LD]    = val & 0x00007fff;
 414        s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
 415        gt64120_pci_mapping(s);
 416        break;
 417    case GT_PCI1IOLD:
 418        s->regs[GT_PCI1IOLD]    = val & 0x00007fff;
 419        s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
 420        break;
 421    case GT_PCI1M0LD:
 422        s->regs[GT_PCI1M0LD]    = val & 0x00007fff;
 423        s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
 424        break;
 425    case GT_PCI1M1LD:
 426        s->regs[GT_PCI1M1LD]    = val & 0x00007fff;
 427        s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
 428        break;
 429    case GT_PCI0M0HD:
 430    case GT_PCI0M1HD:
 431    case GT_PCI0IOHD:
 432        s->regs[saddr] = val & 0x0000007f;
 433        gt64120_pci_mapping(s);
 434        break;
 435    case GT_PCI1IOHD:
 436    case GT_PCI1M0HD:
 437    case GT_PCI1M1HD:
 438        s->regs[saddr] = val & 0x0000007f;
 439        break;
 440    case GT_ISD:
 441        s->regs[saddr] = val & 0x00007fff;
 442        gt64120_isd_mapping(s);
 443        break;
 444
 445    case GT_PCI0IOREMAP:
 446    case GT_PCI0M0REMAP:
 447    case GT_PCI0M1REMAP:
 448    case GT_PCI1IOREMAP:
 449    case GT_PCI1M0REMAP:
 450    case GT_PCI1M1REMAP:
 451        s->regs[saddr] = val & 0x000007ff;
 452        break;
 453
 454    /* CPU Error Report */
 455    case GT_CPUERR_ADDRLO:
 456    case GT_CPUERR_ADDRHI:
 457    case GT_CPUERR_DATALO:
 458    case GT_CPUERR_DATAHI:
 459    case GT_CPUERR_PARITY:
 460        /* Read-only registers, do nothing */
 461        break;
 462
 463    /* CPU Sync Barrier */
 464    case GT_PCI0SYNC:
 465    case GT_PCI1SYNC:
 466        /* Read-only registers, do nothing */
 467        break;
 468
 469    /* SDRAM and Device Address Decode */
 470    case GT_SCS0LD:
 471    case GT_SCS0HD:
 472    case GT_SCS1LD:
 473    case GT_SCS1HD:
 474    case GT_SCS2LD:
 475    case GT_SCS2HD:
 476    case GT_SCS3LD:
 477    case GT_SCS3HD:
 478    case GT_CS0LD:
 479    case GT_CS0HD:
 480    case GT_CS1LD:
 481    case GT_CS1HD:
 482    case GT_CS2LD:
 483    case GT_CS2HD:
 484    case GT_CS3LD:
 485    case GT_CS3HD:
 486    case GT_BOOTLD:
 487    case GT_BOOTHD:
 488    case GT_ADERR:
 489    /* SDRAM Configuration */
 490    case GT_SDRAM_CFG:
 491    case GT_SDRAM_OPMODE:
 492    case GT_SDRAM_BM:
 493    case GT_SDRAM_ADDRDECODE:
 494        /* Accept and ignore SDRAM interleave configuration */
 495        s->regs[saddr] = val;
 496        break;
 497
 498    /* Device Parameters */
 499    case GT_DEV_B0:
 500    case GT_DEV_B1:
 501    case GT_DEV_B2:
 502    case GT_DEV_B3:
 503    case GT_DEV_BOOT:
 504        /* Not implemented */
 505        DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
 506        break;
 507
 508    /* ECC */
 509    case GT_ECC_ERRDATALO:
 510    case GT_ECC_ERRDATAHI:
 511    case GT_ECC_MEM:
 512    case GT_ECC_CALC:
 513    case GT_ECC_ERRADDR:
 514        /* Read-only registers, do nothing */
 515        break;
 516
 517    /* DMA Record */
 518    case GT_DMA0_CNT:
 519    case GT_DMA1_CNT:
 520    case GT_DMA2_CNT:
 521    case GT_DMA3_CNT:
 522    case GT_DMA0_SA:
 523    case GT_DMA1_SA:
 524    case GT_DMA2_SA:
 525    case GT_DMA3_SA:
 526    case GT_DMA0_DA:
 527    case GT_DMA1_DA:
 528    case GT_DMA2_DA:
 529    case GT_DMA3_DA:
 530    case GT_DMA0_NEXT:
 531    case GT_DMA1_NEXT:
 532    case GT_DMA2_NEXT:
 533    case GT_DMA3_NEXT:
 534    case GT_DMA0_CUR:
 535    case GT_DMA1_CUR:
 536    case GT_DMA2_CUR:
 537    case GT_DMA3_CUR:
 538        /* Not implemented */
 539        DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 540        break;
 541
 542    /* DMA Channel Control */
 543    case GT_DMA0_CTRL:
 544    case GT_DMA1_CTRL:
 545    case GT_DMA2_CTRL:
 546    case GT_DMA3_CTRL:
 547        /* Not implemented */
 548        DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 549        break;
 550
 551    /* DMA Arbiter */
 552    case GT_DMA_ARB:
 553        /* Not implemented */
 554        DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 555        break;
 556
 557    /* Timer/Counter */
 558    case GT_TC0:
 559    case GT_TC1:
 560    case GT_TC2:
 561    case GT_TC3:
 562    case GT_TC_CONTROL:
 563        /* Not implemented */
 564        DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
 565        break;
 566
 567    /* PCI Internal */
 568    case GT_PCI0_CMD:
 569    case GT_PCI1_CMD:
 570        s->regs[saddr] = val & 0x0401fc0f;
 571        break;
 572    case GT_PCI0_TOR:
 573    case GT_PCI0_BS_SCS10:
 574    case GT_PCI0_BS_SCS32:
 575    case GT_PCI0_BS_CS20:
 576    case GT_PCI0_BS_CS3BT:
 577    case GT_PCI1_IACK:
 578    case GT_PCI0_IACK:
 579    case GT_PCI0_BARE:
 580    case GT_PCI0_PREFMBR:
 581    case GT_PCI0_SCS10_BAR:
 582    case GT_PCI0_SCS32_BAR:
 583    case GT_PCI0_CS20_BAR:
 584    case GT_PCI0_CS3BT_BAR:
 585    case GT_PCI0_SSCS10_BAR:
 586    case GT_PCI0_SSCS32_BAR:
 587    case GT_PCI0_SCS3BT_BAR:
 588    case GT_PCI1_TOR:
 589    case GT_PCI1_BS_SCS10:
 590    case GT_PCI1_BS_SCS32:
 591    case GT_PCI1_BS_CS20:
 592    case GT_PCI1_BS_CS3BT:
 593    case GT_PCI1_BARE:
 594    case GT_PCI1_PREFMBR:
 595    case GT_PCI1_SCS10_BAR:
 596    case GT_PCI1_SCS32_BAR:
 597    case GT_PCI1_CS20_BAR:
 598    case GT_PCI1_CS3BT_BAR:
 599    case GT_PCI1_SSCS10_BAR:
 600    case GT_PCI1_SSCS32_BAR:
 601    case GT_PCI1_SCS3BT_BAR:
 602    case GT_PCI1_CFGADDR:
 603    case GT_PCI1_CFGDATA:
 604        /* not implemented */
 605        break;
 606    case GT_PCI0_CFGADDR:
 607        phb->config_reg = val & 0x80fffffc;
 608        break;
 609    case GT_PCI0_CFGDATA:
 610        if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
 611            val = bswap32(val);
 612        }
 613        if (phb->config_reg & (1u << 31)) {
 614            pci_data_write(phb->bus, phb->config_reg, val, 4);
 615        }
 616        break;
 617
 618    /* Interrupts */
 619    case GT_INTRCAUSE:
 620        /* not really implemented */
 621        s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
 622        s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
 623        DPRINTF("INTRCAUSE %" PRIx64 "\n", val);
 624        break;
 625    case GT_INTRMASK:
 626        s->regs[saddr] = val & 0x3c3ffffe;
 627        DPRINTF("INTRMASK %" PRIx64 "\n", val);
 628        break;
 629    case GT_PCI0_ICMASK:
 630        s->regs[saddr] = val & 0x03fffffe;
 631        DPRINTF("ICMASK %" PRIx64 "\n", val);
 632        break;
 633    case GT_PCI0_SERR0MASK:
 634        s->regs[saddr] = val & 0x0000003f;
 635        DPRINTF("SERR0MASK %" PRIx64 "\n", val);
 636        break;
 637
 638    /* Reserved when only PCI_0 is configured. */
 639    case GT_HINTRCAUSE:
 640    case GT_CPU_INTSEL:
 641    case GT_PCI0_INTSEL:
 642    case GT_HINTRMASK:
 643    case GT_PCI0_HICMASK:
 644    case GT_PCI1_SERR1MASK:
 645        /* not implemented */
 646        break;
 647
 648    /* SDRAM Parameters */
 649    case GT_SDRAM_B0:
 650    case GT_SDRAM_B1:
 651    case GT_SDRAM_B2:
 652    case GT_SDRAM_B3:
 653        /* We don't simulate electrical parameters of the SDRAM.
 654           Accept, but ignore the values. */
 655        s->regs[saddr] = val;
 656        break;
 657
 658    default:
 659        DPRINTF ("Bad register offset 0x%x\n", (int)addr);
 660        break;
 661    }
 662}
 663
 664static uint64_t gt64120_readl (void *opaque,
 665                               hwaddr addr, unsigned size)
 666{
 667    GT64120State *s = opaque;
 668    PCIHostState *phb = PCI_HOST_BRIDGE(s);
 669    uint32_t val;
 670    uint32_t saddr;
 671
 672    saddr = (addr & 0xfff) >> 2;
 673    switch (saddr) {
 674
 675    /* CPU Configuration */
 676    case GT_MULTI:
 677        /* Only one GT64xxx is present on the CPU bus, return
 678           the initial value */
 679        val = s->regs[saddr];
 680        break;
 681
 682    /* CPU Error Report */
 683    case GT_CPUERR_ADDRLO:
 684    case GT_CPUERR_ADDRHI:
 685    case GT_CPUERR_DATALO:
 686    case GT_CPUERR_DATAHI:
 687    case GT_CPUERR_PARITY:
 688        /* Emulated memory has no error, always return the initial
 689           values */
 690        val = s->regs[saddr];
 691        break;
 692
 693    /* CPU Sync Barrier */
 694    case GT_PCI0SYNC:
 695    case GT_PCI1SYNC:
 696        /* Reading those register should empty all FIFO on the PCI
 697           bus, which are not emulated. The return value should be
 698           a random value that should be ignored. */
 699        val = 0xc000ffee;
 700        break;
 701
 702    /* ECC */
 703    case GT_ECC_ERRDATALO:
 704    case GT_ECC_ERRDATAHI:
 705    case GT_ECC_MEM:
 706    case GT_ECC_CALC:
 707    case GT_ECC_ERRADDR:
 708        /* Emulated memory has no error, always return the initial
 709           values */
 710        val = s->regs[saddr];
 711        break;
 712
 713    case GT_CPU:
 714    case GT_SCS10LD:
 715    case GT_SCS10HD:
 716    case GT_SCS32LD:
 717    case GT_SCS32HD:
 718    case GT_CS20LD:
 719    case GT_CS20HD:
 720    case GT_CS3BOOTLD:
 721    case GT_CS3BOOTHD:
 722    case GT_SCS10AR:
 723    case GT_SCS32AR:
 724    case GT_CS20R:
 725    case GT_CS3BOOTR:
 726    case GT_PCI0IOLD:
 727    case GT_PCI0M0LD:
 728    case GT_PCI0M1LD:
 729    case GT_PCI1IOLD:
 730    case GT_PCI1M0LD:
 731    case GT_PCI1M1LD:
 732    case GT_PCI0IOHD:
 733    case GT_PCI0M0HD:
 734    case GT_PCI0M1HD:
 735    case GT_PCI1IOHD:
 736    case GT_PCI1M0HD:
 737    case GT_PCI1M1HD:
 738    case GT_PCI0IOREMAP:
 739    case GT_PCI0M0REMAP:
 740    case GT_PCI0M1REMAP:
 741    case GT_PCI1IOREMAP:
 742    case GT_PCI1M0REMAP:
 743    case GT_PCI1M1REMAP:
 744    case GT_ISD:
 745        val = s->regs[saddr];
 746        break;
 747    case GT_PCI0_IACK:
 748        /* Read the IRQ number */
 749        val = pic_read_irq(isa_pic);
 750        break;
 751
 752    /* SDRAM and Device Address Decode */
 753    case GT_SCS0LD:
 754    case GT_SCS0HD:
 755    case GT_SCS1LD:
 756    case GT_SCS1HD:
 757    case GT_SCS2LD:
 758    case GT_SCS2HD:
 759    case GT_SCS3LD:
 760    case GT_SCS3HD:
 761    case GT_CS0LD:
 762    case GT_CS0HD:
 763    case GT_CS1LD:
 764    case GT_CS1HD:
 765    case GT_CS2LD:
 766    case GT_CS2HD:
 767    case GT_CS3LD:
 768    case GT_CS3HD:
 769    case GT_BOOTLD:
 770    case GT_BOOTHD:
 771    case GT_ADERR:
 772        val = s->regs[saddr];
 773        break;
 774
 775    /* SDRAM Configuration */
 776    case GT_SDRAM_CFG:
 777    case GT_SDRAM_OPMODE:
 778    case GT_SDRAM_BM:
 779    case GT_SDRAM_ADDRDECODE:
 780        val = s->regs[saddr];
 781        break;
 782
 783    /* SDRAM Parameters */
 784    case GT_SDRAM_B0:
 785    case GT_SDRAM_B1:
 786    case GT_SDRAM_B2:
 787    case GT_SDRAM_B3:
 788        /* We don't simulate electrical parameters of the SDRAM.
 789           Just return the last written value. */
 790        val = s->regs[saddr];
 791        break;
 792
 793    /* Device Parameters */
 794    case GT_DEV_B0:
 795    case GT_DEV_B1:
 796    case GT_DEV_B2:
 797    case GT_DEV_B3:
 798    case GT_DEV_BOOT:
 799        val = s->regs[saddr];
 800        break;
 801
 802    /* DMA Record */
 803    case GT_DMA0_CNT:
 804    case GT_DMA1_CNT:
 805    case GT_DMA2_CNT:
 806    case GT_DMA3_CNT:
 807    case GT_DMA0_SA:
 808    case GT_DMA1_SA:
 809    case GT_DMA2_SA:
 810    case GT_DMA3_SA:
 811    case GT_DMA0_DA:
 812    case GT_DMA1_DA:
 813    case GT_DMA2_DA:
 814    case GT_DMA3_DA:
 815    case GT_DMA0_NEXT:
 816    case GT_DMA1_NEXT:
 817    case GT_DMA2_NEXT:
 818    case GT_DMA3_NEXT:
 819    case GT_DMA0_CUR:
 820    case GT_DMA1_CUR:
 821    case GT_DMA2_CUR:
 822    case GT_DMA3_CUR:
 823        val = s->regs[saddr];
 824        break;
 825
 826    /* DMA Channel Control */
 827    case GT_DMA0_CTRL:
 828    case GT_DMA1_CTRL:
 829    case GT_DMA2_CTRL:
 830    case GT_DMA3_CTRL:
 831        val = s->regs[saddr];
 832        break;
 833
 834    /* DMA Arbiter */
 835    case GT_DMA_ARB:
 836        val = s->regs[saddr];
 837        break;
 838
 839    /* Timer/Counter */
 840    case GT_TC0:
 841    case GT_TC1:
 842    case GT_TC2:
 843    case GT_TC3:
 844    case GT_TC_CONTROL:
 845        val = s->regs[saddr];
 846        break;
 847
 848    /* PCI Internal */
 849    case GT_PCI0_CFGADDR:
 850        val = phb->config_reg;
 851        break;
 852    case GT_PCI0_CFGDATA:
 853        if (!(phb->config_reg & (1 << 31))) {
 854            val = 0xffffffff;
 855        } else {
 856            val = pci_data_read(phb->bus, phb->config_reg, 4);
 857        }
 858        if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
 859            val = bswap32(val);
 860        }
 861        break;
 862
 863    case GT_PCI0_CMD:
 864    case GT_PCI0_TOR:
 865    case GT_PCI0_BS_SCS10:
 866    case GT_PCI0_BS_SCS32:
 867    case GT_PCI0_BS_CS20:
 868    case GT_PCI0_BS_CS3BT:
 869    case GT_PCI1_IACK:
 870    case GT_PCI0_BARE:
 871    case GT_PCI0_PREFMBR:
 872    case GT_PCI0_SCS10_BAR:
 873    case GT_PCI0_SCS32_BAR:
 874    case GT_PCI0_CS20_BAR:
 875    case GT_PCI0_CS3BT_BAR:
 876    case GT_PCI0_SSCS10_BAR:
 877    case GT_PCI0_SSCS32_BAR:
 878    case GT_PCI0_SCS3BT_BAR:
 879    case GT_PCI1_CMD:
 880    case GT_PCI1_TOR:
 881    case GT_PCI1_BS_SCS10:
 882    case GT_PCI1_BS_SCS32:
 883    case GT_PCI1_BS_CS20:
 884    case GT_PCI1_BS_CS3BT:
 885    case GT_PCI1_BARE:
 886    case GT_PCI1_PREFMBR:
 887    case GT_PCI1_SCS10_BAR:
 888    case GT_PCI1_SCS32_BAR:
 889    case GT_PCI1_CS20_BAR:
 890    case GT_PCI1_CS3BT_BAR:
 891    case GT_PCI1_SSCS10_BAR:
 892    case GT_PCI1_SSCS32_BAR:
 893    case GT_PCI1_SCS3BT_BAR:
 894    case GT_PCI1_CFGADDR:
 895    case GT_PCI1_CFGDATA:
 896        val = s->regs[saddr];
 897        break;
 898
 899    /* Interrupts */
 900    case GT_INTRCAUSE:
 901        val = s->regs[saddr];
 902        DPRINTF("INTRCAUSE %x\n", val);
 903        break;
 904    case GT_INTRMASK:
 905        val = s->regs[saddr];
 906        DPRINTF("INTRMASK %x\n", val);
 907        break;
 908    case GT_PCI0_ICMASK:
 909        val = s->regs[saddr];
 910        DPRINTF("ICMASK %x\n", val);
 911        break;
 912    case GT_PCI0_SERR0MASK:
 913        val = s->regs[saddr];
 914        DPRINTF("SERR0MASK %x\n", val);
 915        break;
 916
 917    /* Reserved when only PCI_0 is configured. */
 918    case GT_HINTRCAUSE:
 919    case GT_CPU_INTSEL:
 920    case GT_PCI0_INTSEL:
 921    case GT_HINTRMASK:
 922    case GT_PCI0_HICMASK:
 923    case GT_PCI1_SERR1MASK:
 924        val = s->regs[saddr];
 925        break;
 926
 927    default:
 928        val = s->regs[saddr];
 929        DPRINTF ("Bad register offset 0x%x\n", (int)addr);
 930        break;
 931    }
 932
 933    if (!(s->regs[GT_CPU] & 0x00001000))
 934        val = bswap32(val);
 935
 936    return val;
 937}
 938
 939static const MemoryRegionOps isd_mem_ops = {
 940    .read = gt64120_readl,
 941    .write = gt64120_writel,
 942    .endianness = DEVICE_NATIVE_ENDIAN,
 943};
 944
 945static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 946{
 947    int slot;
 948
 949    slot = (pci_dev->devfn >> 3);
 950
 951    switch (slot) {
 952      /* PIIX4 USB */
 953      case 10:
 954        return 3;
 955      /* AMD 79C973 Ethernet */
 956      case 11:
 957        return 1;
 958      /* Crystal 4281 Sound */
 959      case 12:
 960        return 2;
 961      /* PCI slot 1 to 4 */
 962      case 18 ... 21:
 963        return ((slot - 18) + irq_num) & 0x03;
 964      /* Unknown device, don't do any translation */
 965      default:
 966        return irq_num;
 967    }
 968}
 969
 970static int pci_irq_levels[4];
 971
 972static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
 973{
 974    int i, pic_irq, pic_level;
 975    qemu_irq *pic = opaque;
 976
 977    pci_irq_levels[irq_num] = level;
 978
 979    /* now we change the pic irq level according to the piix irq mappings */
 980    /* XXX: optimize */
 981    pic_irq = piix4_dev->config[0x60 + irq_num];
 982    if (pic_irq < 16) {
 983        /* The pic level is the logical OR of all the PCI irqs mapped
 984           to it */
 985        pic_level = 0;
 986        for (i = 0; i < 4; i++) {
 987            if (pic_irq == piix4_dev->config[0x60 + i])
 988                pic_level |= pci_irq_levels[i];
 989        }
 990        qemu_set_irq(pic[pic_irq], pic_level);
 991    }
 992}
 993
 994
 995static void gt64120_reset(void *opaque)
 996{
 997    GT64120State *s = opaque;
 998
 999    /* FIXME: Malta specific hw assumptions ahead */
1000
1001    /* CPU Configuration */
1002#ifdef TARGET_WORDS_BIGENDIAN
1003    s->regs[GT_CPU]           = 0x00000000;
1004#else
1005    s->regs[GT_CPU]           = 0x00001000;
1006#endif
1007    s->regs[GT_MULTI]         = 0x00000003;
1008
1009    /* CPU Address decode */
1010    s->regs[GT_SCS10LD]       = 0x00000000;
1011    s->regs[GT_SCS10HD]       = 0x00000007;
1012    s->regs[GT_SCS32LD]       = 0x00000008;
1013    s->regs[GT_SCS32HD]       = 0x0000000f;
1014    s->regs[GT_CS20LD]        = 0x000000e0;
1015    s->regs[GT_CS20HD]        = 0x00000070;
1016    s->regs[GT_CS3BOOTLD]     = 0x000000f8;
1017    s->regs[GT_CS3BOOTHD]     = 0x0000007f;
1018
1019    s->regs[GT_PCI0IOLD]      = 0x00000080;
1020    s->regs[GT_PCI0IOHD]      = 0x0000000f;
1021    s->regs[GT_PCI0M0LD]      = 0x00000090;
1022    s->regs[GT_PCI0M0HD]      = 0x0000001f;
1023    s->regs[GT_ISD]           = 0x000000a0;
1024    s->regs[GT_PCI0M1LD]      = 0x00000790;
1025    s->regs[GT_PCI0M1HD]      = 0x0000001f;
1026    s->regs[GT_PCI1IOLD]      = 0x00000100;
1027    s->regs[GT_PCI1IOHD]      = 0x0000000f;
1028    s->regs[GT_PCI1M0LD]      = 0x00000110;
1029    s->regs[GT_PCI1M0HD]      = 0x0000001f;
1030    s->regs[GT_PCI1M1LD]      = 0x00000120;
1031    s->regs[GT_PCI1M1HD]      = 0x0000002f;
1032
1033    s->regs[GT_SCS10AR]       = 0x00000000;
1034    s->regs[GT_SCS32AR]       = 0x00000008;
1035    s->regs[GT_CS20R]         = 0x000000e0;
1036    s->regs[GT_CS3BOOTR]      = 0x000000f8;
1037
1038    s->regs[GT_PCI0IOREMAP]   = 0x00000080;
1039    s->regs[GT_PCI0M0REMAP]   = 0x00000090;
1040    s->regs[GT_PCI0M1REMAP]   = 0x00000790;
1041    s->regs[GT_PCI1IOREMAP]   = 0x00000100;
1042    s->regs[GT_PCI1M0REMAP]   = 0x00000110;
1043    s->regs[GT_PCI1M1REMAP]   = 0x00000120;
1044
1045    /* CPU Error Report */
1046    s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1047    s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1048    s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1049    s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1050    s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1051
1052    /* CPU Sync Barrier */
1053    s->regs[GT_PCI0SYNC]      = 0x00000000;
1054    s->regs[GT_PCI1SYNC]      = 0x00000000;
1055
1056    /* SDRAM and Device Address Decode */
1057    s->regs[GT_SCS0LD]        = 0x00000000;
1058    s->regs[GT_SCS0HD]        = 0x00000007;
1059    s->regs[GT_SCS1LD]        = 0x00000008;
1060    s->regs[GT_SCS1HD]        = 0x0000000f;
1061    s->regs[GT_SCS2LD]        = 0x00000010;
1062    s->regs[GT_SCS2HD]        = 0x00000017;
1063    s->regs[GT_SCS3LD]        = 0x00000018;
1064    s->regs[GT_SCS3HD]        = 0x0000001f;
1065    s->regs[GT_CS0LD]         = 0x000000c0;
1066    s->regs[GT_CS0HD]         = 0x000000c7;
1067    s->regs[GT_CS1LD]         = 0x000000c8;
1068    s->regs[GT_CS1HD]         = 0x000000cf;
1069    s->regs[GT_CS2LD]         = 0x000000d0;
1070    s->regs[GT_CS2HD]         = 0x000000df;
1071    s->regs[GT_CS3LD]         = 0x000000f0;
1072    s->regs[GT_CS3HD]         = 0x000000fb;
1073    s->regs[GT_BOOTLD]        = 0x000000fc;
1074    s->regs[GT_BOOTHD]        = 0x000000ff;
1075    s->regs[GT_ADERR]         = 0xffffffff;
1076
1077    /* SDRAM Configuration */
1078    s->regs[GT_SDRAM_CFG]     = 0x00000200;
1079    s->regs[GT_SDRAM_OPMODE]  = 0x00000000;
1080    s->regs[GT_SDRAM_BM]      = 0x00000007;
1081    s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1082
1083    /* SDRAM Parameters */
1084    s->regs[GT_SDRAM_B0]      = 0x00000005;
1085    s->regs[GT_SDRAM_B1]      = 0x00000005;
1086    s->regs[GT_SDRAM_B2]      = 0x00000005;
1087    s->regs[GT_SDRAM_B3]      = 0x00000005;
1088
1089    /* ECC */
1090    s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1091    s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1092    s->regs[GT_ECC_MEM]       = 0x00000000;
1093    s->regs[GT_ECC_CALC]      = 0x00000000;
1094    s->regs[GT_ECC_ERRADDR]   = 0x00000000;
1095
1096    /* Device Parameters */
1097    s->regs[GT_DEV_B0]        = 0x386fffff;
1098    s->regs[GT_DEV_B1]        = 0x386fffff;
1099    s->regs[GT_DEV_B2]        = 0x386fffff;
1100    s->regs[GT_DEV_B3]        = 0x386fffff;
1101    s->regs[GT_DEV_BOOT]      = 0x146fffff;
1102
1103    /* DMA registers are all zeroed at reset */
1104
1105    /* Timer/Counter */
1106    s->regs[GT_TC0]           = 0xffffffff;
1107    s->regs[GT_TC1]           = 0x00ffffff;
1108    s->regs[GT_TC2]           = 0x00ffffff;
1109    s->regs[GT_TC3]           = 0x00ffffff;
1110    s->regs[GT_TC_CONTROL]    = 0x00000000;
1111
1112    /* PCI Internal */
1113#ifdef TARGET_WORDS_BIGENDIAN
1114    s->regs[GT_PCI0_CMD]      = 0x00000000;
1115#else
1116    s->regs[GT_PCI0_CMD]      = 0x00010001;
1117#endif
1118    s->regs[GT_PCI0_TOR]      = 0x0000070f;
1119    s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1120    s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1121    s->regs[GT_PCI0_BS_CS20]  = 0x01fff000;
1122    s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1123    s->regs[GT_PCI1_IACK]     = 0x00000000;
1124    s->regs[GT_PCI0_IACK]     = 0x00000000;
1125    s->regs[GT_PCI0_BARE]     = 0x0000000f;
1126    s->regs[GT_PCI0_PREFMBR]  = 0x00000040;
1127    s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1128    s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1129    s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1130    s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1131    s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1132    s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1133    s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1134#ifdef TARGET_WORDS_BIGENDIAN
1135    s->regs[GT_PCI1_CMD]      = 0x00000000;
1136#else
1137    s->regs[GT_PCI1_CMD]      = 0x00010001;
1138#endif
1139    s->regs[GT_PCI1_TOR]      = 0x0000070f;
1140    s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1141    s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1142    s->regs[GT_PCI1_BS_CS20]  = 0x01fff000;
1143    s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1144    s->regs[GT_PCI1_BARE]     = 0x0000000f;
1145    s->regs[GT_PCI1_PREFMBR]  = 0x00000040;
1146    s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1147    s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1148    s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1149    s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1150    s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1151    s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1152    s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1153    s->regs[GT_PCI1_CFGADDR]  = 0x00000000;
1154    s->regs[GT_PCI1_CFGDATA]  = 0x00000000;
1155    s->regs[GT_PCI0_CFGADDR]  = 0x00000000;
1156
1157    /* Interrupt registers are all zeroed at reset */
1158
1159    gt64120_isd_mapping(s);
1160    gt64120_pci_mapping(s);
1161}
1162
1163PCIBus *gt64120_register(qemu_irq *pic)
1164{
1165    GT64120State *d;
1166    PCIHostState *phb;
1167    DeviceState *dev;
1168
1169    dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
1170    d = GT64120_PCI_HOST_BRIDGE(dev);
1171    phb = PCI_HOST_BRIDGE(dev);
1172    memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX);
1173    address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
1174    phb->bus = pci_register_bus(dev, "pci",
1175                                gt64120_pci_set_irq, gt64120_pci_map_irq,
1176                                pic,
1177                                &d->pci0_mem,
1178                                get_system_io(),
1179                                PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
1180    qdev_init_nofail(dev);
1181    memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000);
1182
1183    pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1184    return phb->bus;
1185}
1186
1187static int gt64120_init(SysBusDevice *dev)
1188{
1189    GT64120State *s;
1190
1191    s = GT64120_PCI_HOST_BRIDGE(dev);
1192
1193    qemu_register_reset(gt64120_reset, s);
1194    return 0;
1195}
1196
1197static void gt64120_pci_realize(PCIDevice *d, Error **errp)
1198{
1199    /* FIXME: Malta specific hw assumptions ahead */
1200    pci_set_word(d->config + PCI_COMMAND, 0);
1201    pci_set_word(d->config + PCI_STATUS,
1202                 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1203    pci_config_set_prog_interface(d->config, 0);
1204    pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1205    pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1206    pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1207    pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1208    pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1209    pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1210    pci_set_byte(d->config + 0x3d, 0x01);
1211}
1212
1213static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1214{
1215    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1216    DeviceClass *dc = DEVICE_CLASS(klass);
1217
1218    k->realize = gt64120_pci_realize;
1219    k->vendor_id = PCI_VENDOR_ID_MARVELL;
1220    k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1221    k->revision = 0x10;
1222    k->class_id = PCI_CLASS_BRIDGE_HOST;
1223    /*
1224     * PCI-facing part of the host bridge, not usable without the
1225     * host-facing part, which can't be device_add'ed, yet.
1226     */
1227    dc->cannot_instantiate_with_device_add_yet = true;
1228}
1229
1230static const TypeInfo gt64120_pci_info = {
1231    .name          = "gt64120_pci",
1232    .parent        = TYPE_PCI_DEVICE,
1233    .instance_size = sizeof(PCIDevice),
1234    .class_init    = gt64120_pci_class_init,
1235};
1236
1237static void gt64120_class_init(ObjectClass *klass, void *data)
1238{
1239    DeviceClass *dc = DEVICE_CLASS(klass);
1240    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1241
1242    sdc->init = gt64120_init;
1243    dc->vmsd = &vmstate_gt64120;
1244}
1245
1246static const TypeInfo gt64120_info = {
1247    .name          = TYPE_GT64120_PCI_HOST_BRIDGE,
1248    .parent        = TYPE_PCI_HOST_BRIDGE,
1249    .instance_size = sizeof(GT64120State),
1250    .class_init    = gt64120_class_init,
1251};
1252
1253static void gt64120_pci_register_types(void)
1254{
1255    type_register_static(&gt64120_info);
1256    type_register_static(&gt64120_pci_info);
1257}
1258
1259type_init(gt64120_pci_register_types)
1260