LXR qemu/hw/net/dp8393x.c

   1/*
   2 * QEMU NS SONIC DP8393x netcard
   3 *
   4 * Copyright (c) 2008-2009 Herve Poussineau
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License as
   8 * published by the Free Software Foundation; either version 2 of
   9 * the License, or (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License along
  17 * with this program; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include "qemu/osdep.h"
  21#include "hw/sysbus.h"
  22#include "hw/devices.h"
  23#include "net/net.h"
  24#include "qapi/error.h"
  25#include "qemu/timer.h"
  26#include <zlib.h>
  27
  28//#define DEBUG_SONIC
  29
  30#define SONIC_PROM_SIZE 0x1000
  31
  32#ifdef DEBUG_SONIC
  33#define DPRINTF(fmt, ...) \
  34do { printf("sonic: " fmt , ##  __VA_ARGS__); } while (0)
  35static const char* reg_names[] = {
  36    "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
  37    "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
  38    "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
  39    "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
  40    "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
  41    "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
  42    "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
  43    "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
  44#else
  45#define DPRINTF(fmt, ...) do {} while (0)
  46#endif
  47
  48#define SONIC_ERROR(fmt, ...) \
  49do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  50
  51#define SONIC_CR     0x00
  52#define SONIC_DCR    0x01
  53#define SONIC_RCR    0x02
  54#define SONIC_TCR    0x03
  55#define SONIC_IMR    0x04
  56#define SONIC_ISR    0x05
  57#define SONIC_UTDA   0x06
  58#define SONIC_CTDA   0x07
  59#define SONIC_TPS    0x08
  60#define SONIC_TFC    0x09
  61#define SONIC_TSA0   0x0a
  62#define SONIC_TSA1   0x0b
  63#define SONIC_TFS    0x0c
  64#define SONIC_URDA   0x0d
  65#define SONIC_CRDA   0x0e
  66#define SONIC_CRBA0  0x0f
  67#define SONIC_CRBA1  0x10
  68#define SONIC_RBWC0  0x11
  69#define SONIC_RBWC1  0x12
  70#define SONIC_EOBC   0x13
  71#define SONIC_URRA   0x14
  72#define SONIC_RSA    0x15
  73#define SONIC_REA    0x16
  74#define SONIC_RRP    0x17
  75#define SONIC_RWP    0x18
  76#define SONIC_TRBA0  0x19
  77#define SONIC_TRBA1  0x1a
  78#define SONIC_LLFA   0x1f
  79#define SONIC_TTDA   0x20
  80#define SONIC_CEP    0x21
  81#define SONIC_CAP2   0x22
  82#define SONIC_CAP1   0x23
  83#define SONIC_CAP0   0x24
  84#define SONIC_CE     0x25
  85#define SONIC_CDP    0x26
  86#define SONIC_CDC    0x27
  87#define SONIC_SR     0x28
  88#define SONIC_WT0    0x29
  89#define SONIC_WT1    0x2a
  90#define SONIC_RSC    0x2b
  91#define SONIC_CRCT   0x2c
  92#define SONIC_FAET   0x2d
  93#define SONIC_MPT    0x2e
  94#define SONIC_MDT    0x2f
  95#define SONIC_DCR2   0x3f
  96
  97#define SONIC_CR_HTX     0x0001
  98#define SONIC_CR_TXP     0x0002
  99#define SONIC_CR_RXDIS   0x0004
 100#define SONIC_CR_RXEN    0x0008
 101#define SONIC_CR_STP     0x0010
 102#define SONIC_CR_ST      0x0020
 103#define SONIC_CR_RST     0x0080
 104#define SONIC_CR_RRRA    0x0100
 105#define SONIC_CR_LCAM    0x0200
 106#define SONIC_CR_MASK    0x03bf
 107
 108#define SONIC_DCR_DW     0x0020
 109#define SONIC_DCR_LBR    0x2000
 110#define SONIC_DCR_EXBUS  0x8000
 111
 112#define SONIC_RCR_PRX    0x0001
 113#define SONIC_RCR_LBK    0x0002
 114#define SONIC_RCR_FAER   0x0004
 115#define SONIC_RCR_CRCR   0x0008
 116#define SONIC_RCR_CRS    0x0020
 117#define SONIC_RCR_LPKT   0x0040
 118#define SONIC_RCR_BC     0x0080
 119#define SONIC_RCR_MC     0x0100
 120#define SONIC_RCR_LB0    0x0200
 121#define SONIC_RCR_LB1    0x0400
 122#define SONIC_RCR_AMC    0x0800
 123#define SONIC_RCR_PRO    0x1000
 124#define SONIC_RCR_BRD    0x2000
 125#define SONIC_RCR_RNT    0x4000
 126
 127#define SONIC_TCR_PTX    0x0001
 128#define SONIC_TCR_BCM    0x0002
 129#define SONIC_TCR_FU     0x0004
 130#define SONIC_TCR_EXC    0x0040
 131#define SONIC_TCR_CRSL   0x0080
 132#define SONIC_TCR_NCRS   0x0100
 133#define SONIC_TCR_EXD    0x0400
 134#define SONIC_TCR_CRCI   0x2000
 135#define SONIC_TCR_PINT   0x8000
 136
 137#define SONIC_ISR_RBE    0x0020
 138#define SONIC_ISR_RDE    0x0040
 139#define SONIC_ISR_TC     0x0080
 140#define SONIC_ISR_TXDN   0x0200
 141#define SONIC_ISR_PKTRX  0x0400
 142#define SONIC_ISR_PINT   0x0800
 143#define SONIC_ISR_LCD    0x1000
 144
 145#define TYPE_DP8393X "dp8393x"
 146#define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X)
 147
 148typedef struct dp8393xState {
 149    SysBusDevice parent_obj;
 150
 151    /* Hardware */
 152    uint8_t it_shift;
 153    qemu_irq irq;
 154#ifdef DEBUG_SONIC
 155    int irq_level;
 156#endif
 157    QEMUTimer *watchdog;
 158    int64_t wt_last_update;
 159    NICConf conf;
 160    NICState *nic;
 161    MemoryRegion mmio;
 162    MemoryRegion prom;
 163
 164    /* Registers */
 165    uint8_t cam[16][6];
 166    uint16_t regs[0x40];
 167
 168    /* Temporaries */
 169    uint8_t tx_buffer[0x10000];
 170    int loopback_packet;
 171
 172    /* Memory access */
 173    void *dma_mr;
 174    AddressSpace as;
 175} dp8393xState;
 176
 177static void dp8393x_update_irq(dp8393xState *s)
 178{
 179    int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
 180
 181#ifdef DEBUG_SONIC
 182    if (level != s->irq_level) {
 183        s->irq_level = level;
 184        if (level) {
 185            DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]);
 186        } else {
 187            DPRINTF("lower irq\n");
 188        }
 189    }
 190#endif
 191
 192    qemu_set_irq(s->irq, level);
 193}
 194
 195static void dp8393x_do_load_cam(dp8393xState *s)
 196{
 197    uint16_t data[8];
 198    int width, size;
 199    uint16_t index = 0;
 200
 201    width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 202    size = sizeof(uint16_t) * 4 * width;
 203
 204    while (s->regs[SONIC_CDC] & 0x1f) {
 205        /* Fill current entry */
 206        address_space_rw(&s->as,
 207            (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP],
 208            MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 209        s->cam[index][0] = data[1 * width] & 0xff;
 210        s->cam[index][1] = data[1 * width] >> 8;
 211        s->cam[index][2] = data[2 * width] & 0xff;
 212        s->cam[index][3] = data[2 * width] >> 8;
 213        s->cam[index][4] = data[3 * width] & 0xff;
 214        s->cam[index][5] = data[3 * width] >> 8;
 215        DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index,
 216            s->cam[index][0], s->cam[index][1], s->cam[index][2],
 217            s->cam[index][3], s->cam[index][4], s->cam[index][5]);
 218        /* Move to next entry */
 219        s->regs[SONIC_CDC]--;
 220        s->regs[SONIC_CDP] += size;
 221        index++;
 222    }
 223
 224    /* Read CAM enable */
 225    address_space_rw(&s->as,
 226        (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP],
 227        MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 228    s->regs[SONIC_CE] = data[0 * width];
 229    DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
 230
 231    /* Done */
 232    s->regs[SONIC_CR] &= ~SONIC_CR_LCAM;
 233    s->regs[SONIC_ISR] |= SONIC_ISR_LCD;
 234    dp8393x_update_irq(s);
 235}
 236
 237static void dp8393x_do_read_rra(dp8393xState *s)
 238{
 239    uint16_t data[8];
 240    int width, size;
 241
 242    /* Read memory */
 243    width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 244    size = sizeof(uint16_t) * 4 * width;
 245    address_space_rw(&s->as,
 246        (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP],
 247        MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 248
 249    /* Update SONIC registers */
 250    s->regs[SONIC_CRBA0] = data[0 * width];
 251    s->regs[SONIC_CRBA1] = data[1 * width];
 252    s->regs[SONIC_RBWC0] = data[2 * width];
 253    s->regs[SONIC_RBWC1] = data[3 * width];
 254    DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
 255        s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
 256        s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
 257
 258    /* Go to next entry */
 259    s->regs[SONIC_RRP] += size;
 260
 261    /* Handle wrap */
 262    if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) {
 263        s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
 264    }
 265
 266    /* Check resource exhaustion */
 267    if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])
 268    {
 269        s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
 270        dp8393x_update_irq(s);
 271    }
 272
 273    /* Done */
 274    s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
 275}
 276
 277static void dp8393x_do_software_reset(dp8393xState *s)
 278{
 279    timer_del(s->watchdog);
 280
 281    s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX);
 282    s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
 283}
 284
 285static void dp8393x_set_next_tick(dp8393xState *s)
 286{
 287    uint32_t ticks;
 288    int64_t delay;
 289
 290    if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 291        timer_del(s->watchdog);
 292        return;
 293    }
 294
 295    ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
 296    s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 297    delay = NANOSECONDS_PER_SECOND * ticks / 5000000;
 298    timer_mod(s->watchdog, s->wt_last_update + delay);
 299}
 300
 301static void dp8393x_update_wt_regs(dp8393xState *s)
 302{
 303    int64_t elapsed;
 304    uint32_t val;
 305
 306    if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 307        timer_del(s->watchdog);
 308        return;
 309    }
 310
 311    elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 312    val = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
 313    val -= elapsed / 5000000;
 314    s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
 315    s->regs[SONIC_WT0] = (val >> 0)  & 0xffff;
 316    dp8393x_set_next_tick(s);
 317
 318}
 319
 320static void dp8393x_do_start_timer(dp8393xState *s)
 321{
 322    s->regs[SONIC_CR] &= ~SONIC_CR_STP;
 323    dp8393x_set_next_tick(s);
 324}
 325
 326static void dp8393x_do_stop_timer(dp8393xState *s)
 327{
 328    s->regs[SONIC_CR] &= ~SONIC_CR_ST;
 329    dp8393x_update_wt_regs(s);
 330}
 331
 332static int dp8393x_can_receive(NetClientState *nc);
 333
 334static void dp8393x_do_receiver_enable(dp8393xState *s)
 335{
 336    s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS;
 337    if (dp8393x_can_receive(s->nic->ncs)) {
 338        qemu_flush_queued_packets(qemu_get_queue(s->nic));
 339    }
 340}
 341
 342static void dp8393x_do_receiver_disable(dp8393xState *s)
 343{
 344    s->regs[SONIC_CR] &= ~SONIC_CR_RXEN;
 345}
 346
 347static void dp8393x_do_transmit_packets(dp8393xState *s)
 348{
 349    NetClientState *nc = qemu_get_queue(s->nic);
 350    uint16_t data[12];
 351    int width, size;
 352    int tx_len, len;
 353    uint16_t i;
 354
 355    width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 356
 357    while (1) {
 358        /* Read memory */
 359        DPRINTF("Transmit packet at %08x\n",
 360                (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_CTDA]);
 361        size = sizeof(uint16_t) * 6 * width;
 362        s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
 363        address_space_rw(&s->as,
 364            ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * width,
 365            MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 366        tx_len = 0;
 367
 368        /* Update registers */
 369        s->regs[SONIC_TCR] = data[0 * width] & 0xf000;
 370        s->regs[SONIC_TPS] = data[1 * width];
 371        s->regs[SONIC_TFC] = data[2 * width];
 372        s->regs[SONIC_TSA0] = data[3 * width];
 373        s->regs[SONIC_TSA1] = data[4 * width];
 374        s->regs[SONIC_TFS] = data[5 * width];
 375
 376        /* Handle programmable interrupt */
 377        if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
 378            s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
 379        } else {
 380            s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
 381        }
 382
 383        for (i = 0; i < s->regs[SONIC_TFC]; ) {
 384            /* Append fragment */
 385            len = s->regs[SONIC_TFS];
 386            if (tx_len + len > sizeof(s->tx_buffer)) {
 387                len = sizeof(s->tx_buffer) - tx_len;
 388            }
 389            address_space_rw(&s->as,
 390                (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0],
 391                MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0);
 392            tx_len += len;
 393
 394            i++;
 395            if (i != s->regs[SONIC_TFC]) {
 396                /* Read next fragment details */
 397                size = sizeof(uint16_t) * 3 * width;
 398                address_space_rw(&s->as,
 399                    ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * i) * width,
 400                    MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 401                s->regs[SONIC_TSA0] = data[0 * width];
 402                s->regs[SONIC_TSA1] = data[1 * width];
 403                s->regs[SONIC_TFS] = data[2 * width];
 404            }
 405        }
 406
 407        /* Handle Ethernet checksum */
 408        if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
 409            /* Don't append FCS there, to look like slirp packets
 410             * which don't have one */
 411        } else {
 412            /* Remove existing FCS */
 413            tx_len -= 4;
 414        }
 415
 416        if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
 417            /* Loopback */
 418            s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
 419            if (nc->info->can_receive(nc)) {
 420                s->loopback_packet = 1;
 421                nc->info->receive(nc, s->tx_buffer, tx_len);
 422            }
 423        } else {
 424            /* Transmit packet */
 425            qemu_send_packet(nc, s->tx_buffer, tx_len);
 426        }
 427        s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
 428
 429        /* Write status */
 430        data[0 * width] = s->regs[SONIC_TCR] & 0x0fff; /* status */
 431        size = sizeof(uint16_t) * width;
 432        address_space_rw(&s->as,
 433            (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA],
 434            MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
 435
 436        if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
 437            /* Read footer of packet */
 438            size = sizeof(uint16_t) * width;
 439            address_space_rw(&s->as,
 440                ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width,
 441                MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 442            s->regs[SONIC_CTDA] = data[0 * width] & ~0x1;
 443            if (data[0 * width] & 0x1) {
 444                /* EOL detected */
 445                break;
 446            }
 447        }
 448    }
 449
 450    /* Done */
 451    s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
 452    s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
 453    dp8393x_update_irq(s);
 454}
 455
 456static void dp8393x_do_halt_transmission(dp8393xState *s)
 457{
 458    /* Nothing to do */
 459}
 460
 461static void dp8393x_do_command(dp8393xState *s, uint16_t command)
 462{
 463    if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) {
 464        s->regs[SONIC_CR] &= ~SONIC_CR_RST;
 465        return;
 466    }
 467
 468    s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
 469
 470    if (command & SONIC_CR_HTX)
 471        dp8393x_do_halt_transmission(s);
 472    if (command & SONIC_CR_TXP)
 473        dp8393x_do_transmit_packets(s);
 474    if (command & SONIC_CR_RXDIS)
 475        dp8393x_do_receiver_disable(s);
 476    if (command & SONIC_CR_RXEN)
 477        dp8393x_do_receiver_enable(s);
 478    if (command & SONIC_CR_STP)
 479        dp8393x_do_stop_timer(s);
 480    if (command & SONIC_CR_ST)
 481        dp8393x_do_start_timer(s);
 482    if (command & SONIC_CR_RST)
 483        dp8393x_do_software_reset(s);
 484    if (command & SONIC_CR_RRRA)
 485        dp8393x_do_read_rra(s);
 486    if (command & SONIC_CR_LCAM)
 487        dp8393x_do_load_cam(s);
 488}
 489
 490static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
 491{
 492    dp8393xState *s = opaque;
 493    int reg = addr >> s->it_shift;
 494    uint16_t val = 0;
 495
 496    switch (reg) {
 497        /* Update data before reading it */
 498        case SONIC_WT0:
 499        case SONIC_WT1:
 500            dp8393x_update_wt_regs(s);
 501            val = s->regs[reg];
 502            break;
 503        /* Accept read to some registers only when in reset mode */
 504        case SONIC_CAP2:
 505        case SONIC_CAP1:
 506        case SONIC_CAP0:
 507            if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 508                val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8;
 509                val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)];
 510            }
 511            break;
 512        /* All other registers have no special contrainst */
 513        default:
 514            val = s->regs[reg];
 515    }
 516
 517    DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]);
 518
 519    return val;
 520}
 521
 522static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
 523                          unsigned int size)
 524{
 525    dp8393xState *s = opaque;
 526    int reg = addr >> s->it_shift;
 527
 528    DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]);
 529
 530    switch (reg) {
 531        /* Command register */
 532        case SONIC_CR:
 533            dp8393x_do_command(s, data);
 534            break;
 535        /* Prevent write to read-only registers */
 536        case SONIC_CAP2:
 537        case SONIC_CAP1:
 538        case SONIC_CAP0:
 539        case SONIC_SR:
 540        case SONIC_MDT:
 541            DPRINTF("writing to reg %d invalid\n", reg);
 542            break;
 543        /* Accept write to some registers only when in reset mode */
 544        case SONIC_DCR:
 545            if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 546                s->regs[reg] = data & 0xbfff;
 547            } else {
 548                DPRINTF("writing to DCR invalid\n");
 549            }
 550            break;
 551        case SONIC_DCR2:
 552            if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 553                s->regs[reg] = data & 0xf017;
 554            } else {
 555                DPRINTF("writing to DCR2 invalid\n");
 556            }
 557            break;
 558        /* 12 lower bytes are Read Only */
 559        case SONIC_TCR:
 560            s->regs[reg] = data & 0xf000;
 561            break;
 562        /* 9 lower bytes are Read Only */
 563        case SONIC_RCR:
 564            s->regs[reg] = data & 0xffe0;
 565            break;
 566        /* Ignore most significant bit */
 567        case SONIC_IMR:
 568            s->regs[reg] = data & 0x7fff;
 569            dp8393x_update_irq(s);
 570            break;
 571        /* Clear bits by writing 1 to them */
 572        case SONIC_ISR:
 573            data &= s->regs[reg];
 574            s->regs[reg] &= ~data;
 575            if (data & SONIC_ISR_RBE) {
 576                dp8393x_do_read_rra(s);
 577            }
 578            dp8393x_update_irq(s);
 579            if (dp8393x_can_receive(s->nic->ncs)) {
 580                qemu_flush_queued_packets(qemu_get_queue(s->nic));
 581            }
 582            break;
 583        /* Ignore least significant bit */
 584        case SONIC_RSA:
 585        case SONIC_REA:
 586        case SONIC_RRP:
 587        case SONIC_RWP:
 588            s->regs[reg] = data & 0xfffe;
 589            break;
 590        /* Invert written value for some registers */
 591        case SONIC_CRCT:
 592        case SONIC_FAET:
 593        case SONIC_MPT:
 594            s->regs[reg] = data ^ 0xffff;
 595            break;
 596        /* All other registers have no special contrainst */
 597        default:
 598            s->regs[reg] = data;
 599    }
 600
 601    if (reg == SONIC_WT0 || reg == SONIC_WT1) {
 602        dp8393x_set_next_tick(s);
 603    }
 604}
 605
 606static const MemoryRegionOps dp8393x_ops = {
 607    .read = dp8393x_read,
 608    .write = dp8393x_write,
 609    .impl.min_access_size = 2,
 610    .impl.max_access_size = 2,
 611    .endianness = DEVICE_NATIVE_ENDIAN,
 612};
 613
 614static void dp8393x_watchdog(void *opaque)
 615{
 616    dp8393xState *s = opaque;
 617
 618    if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 619        return;
 620    }
 621
 622    s->regs[SONIC_WT1] = 0xffff;
 623    s->regs[SONIC_WT0] = 0xffff;
 624    dp8393x_set_next_tick(s);
 625
 626    /* Signal underflow */
 627    s->regs[SONIC_ISR] |= SONIC_ISR_TC;
 628    dp8393x_update_irq(s);
 629}
 630
 631static int dp8393x_can_receive(NetClientState *nc)
 632{
 633    dp8393xState *s = qemu_get_nic_opaque(nc);
 634
 635    if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN))
 636        return 0;
 637    if (s->regs[SONIC_ISR] & SONIC_ISR_RBE)
 638        return 0;
 639    return 1;
 640}
 641
 642static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
 643                                  int size)
 644{
 645    static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 646    int i;
 647
 648    /* Check promiscuous mode */
 649    if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) {
 650        return 0;
 651    }
 652
 653    /* Check multicast packets */
 654    if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) {
 655        return SONIC_RCR_MC;
 656    }
 657
 658    /* Check broadcast */
 659    if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) {
 660        return SONIC_RCR_BC;
 661    }
 662
 663    /* Check CAM */
 664    for (i = 0; i < 16; i++) {
 665        if (s->regs[SONIC_CE] & (1 << i)) {
 666             /* Entry enabled */
 667             if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
 668                 return 0;
 669             }
 670        }
 671    }
 672
 673    return -1;
 674}
 675
 676static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
 677                               size_t size)
 678{
 679    dp8393xState *s = qemu_get_nic_opaque(nc);
 680    uint16_t data[10];
 681    int packet_type;
 682    uint32_t available, address;
 683    int width, rx_len = size;
 684    uint32_t checksum;
 685
 686    width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 687
 688    s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
 689        SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
 690
 691    packet_type = dp8393x_receive_filter(s, buf, size);
 692    if (packet_type < 0) {
 693        DPRINTF("packet not for netcard\n");
 694        return -1;
 695    }
 696
 697    /* XXX: Check byte ordering */
 698
 699    /* Check for EOL */
 700    if (s->regs[SONIC_LLFA] & 0x1) {
 701        /* Are we still in resource exhaustion? */
 702        size = sizeof(uint16_t) * 1 * width;
 703        address = ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width;
 704        address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
 705                         (uint8_t *)data, size, 0);
 706        if (data[0 * width] & 0x1) {
 707            /* Still EOL ; stop reception */
 708            return -1;
 709        } else {
 710            s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
 711        }
 712    }
 713
 714    /* Save current position */
 715    s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
 716    s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
 717
 718    /* Calculate the ethernet checksum */
 719    checksum = cpu_to_le32(crc32(0, buf, rx_len));
 720
 721    /* Put packet into RBA */
 722    DPRINTF("Receive packet at %08x\n", (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]);
 723    address = (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
 724    address_space_rw(&s->as, address,
 725        MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1);
 726    address += rx_len;
 727    address_space_rw(&s->as, address,
 728        MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1);
 729    rx_len += 4;
 730    s->regs[SONIC_CRBA1] = address >> 16;
 731    s->regs[SONIC_CRBA0] = address & 0xffff;
 732    available = (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0];
 733    available -= rx_len / 2;
 734    s->regs[SONIC_RBWC1] = available >> 16;
 735    s->regs[SONIC_RBWC0] = available & 0xffff;
 736
 737    /* Update status */
 738    if (((s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]) < s->regs[SONIC_EOBC]) {
 739        s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
 740    }
 741    s->regs[SONIC_RCR] |= packet_type;
 742    s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
 743    if (s->loopback_packet) {
 744        s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
 745        s->loopback_packet = 0;
 746    }
 747
 748    /* Write status to memory */
 749    DPRINTF("Write status at %08x\n", (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]);
 750    data[0 * width] = s->regs[SONIC_RCR]; /* status */
 751    data[1 * width] = rx_len; /* byte count */
 752    data[2 * width] = s->regs[SONIC_TRBA0]; /* pkt_ptr0 */
 753    data[3 * width] = s->regs[SONIC_TRBA1]; /* pkt_ptr1 */
 754    data[4 * width] = s->regs[SONIC_RSC]; /* seq_no */
 755    size = sizeof(uint16_t) * 5 * width;
 756    address_space_rw(&s->as, (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA],
 757        MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
 758
 759    /* Move to next descriptor */
 760    size = sizeof(uint16_t) * width;
 761    address_space_rw(&s->as,
 762        ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width,
 763        MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 764    s->regs[SONIC_LLFA] = data[0 * width];
 765    if (s->regs[SONIC_LLFA] & 0x1) {
 766        /* EOL detected */
 767        s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
 768    } else {
 769        data[0 * width] = 0; /* in_use */
 770        address_space_rw(&s->as,
 771            ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 6 * width,
 772            MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1);
 773        s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
 774        s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
 775        s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);
 776
 777        if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
 778            /* Read next RRA */
 779            dp8393x_do_read_rra(s);
 780        }
 781    }
 782
 783    /* Done */
 784    dp8393x_update_irq(s);
 785
 786    return size;
 787}
 788
 789static void dp8393x_reset(DeviceState *dev)
 790{
 791    dp8393xState *s = DP8393X(dev);
 792    timer_del(s->watchdog);
 793
 794    memset(s->regs, 0, sizeof(s->regs));
 795    s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
 796    s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
 797    s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT);
 798    s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
 799    s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
 800    s->regs[SONIC_IMR] = 0;
 801    s->regs[SONIC_ISR] = 0;
 802    s->regs[SONIC_DCR2] = 0;
 803    s->regs[SONIC_EOBC] = 0x02F8;
 804    s->regs[SONIC_RSC] = 0;
 805    s->regs[SONIC_CE] = 0;
 806    s->regs[SONIC_RSC] = 0;
 807
 808    /* Network cable is connected */
 809    s->regs[SONIC_RCR] |= SONIC_RCR_CRS;
 810
 811    dp8393x_update_irq(s);
 812}
 813
 814static NetClientInfo net_dp83932_info = {
 815    .type = NET_CLIENT_DRIVER_NIC,
 816    .size = sizeof(NICState),
 817    .can_receive = dp8393x_can_receive,
 818    .receive = dp8393x_receive,
 819};
 820
 821static void dp8393x_instance_init(Object *obj)
 822{
 823    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 824    dp8393xState *s = DP8393X(obj);
 825
 826    sysbus_init_mmio(sbd, &s->mmio);
 827    sysbus_init_mmio(sbd, &s->prom);
 828    sysbus_init_irq(sbd, &s->irq);
 829}
 830
 831static void dp8393x_realize(DeviceState *dev, Error **errp)
 832{
 833    dp8393xState *s = DP8393X(dev);
 834    int i, checksum;
 835    uint8_t *prom;
 836    Error *local_err = NULL;
 837
 838    address_space_init(&s->as, s->dma_mr, "dp8393x");
 839    memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
 840                          "dp8393x-regs", 0x40 << s->it_shift);
 841
 842    s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
 843                          object_get_typename(OBJECT(dev)), dev->id, s);
 844    qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 845
 846    s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
 847    s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
 848
 849    memory_region_init_ram(&s->prom, OBJECT(dev),
 850                           "dp8393x-prom", SONIC_PROM_SIZE, &local_err);
 851    if (local_err) {
 852        error_propagate(errp, local_err);
 853        return;
 854    }
 855    memory_region_set_readonly(&s->prom, true);
 856    prom = memory_region_get_ram_ptr(&s->prom);
 857    checksum = 0;
 858    for (i = 0; i < 6; i++) {
 859        prom[i] = s->conf.macaddr.a[i];
 860        checksum += prom[i];
 861        if (checksum > 0xff) {
 862            checksum = (checksum + 1) & 0xff;
 863        }
 864    }
 865    prom[7] = 0xff - checksum;
 866}
 867
 868static const VMStateDescription vmstate_dp8393x = {
 869    .name = "dp8393x",
 870    .version_id = 0,
 871    .minimum_version_id = 0,
 872    .fields = (VMStateField []) {
 873        VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
 874        VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
 875        VMSTATE_END_OF_LIST()
 876    }
 877};
 878
 879static Property dp8393x_properties[] = {
 880    DEFINE_NIC_PROPERTIES(dp8393xState, conf),
 881    DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr),
 882    DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
 883    DEFINE_PROP_END_OF_LIST(),
 884};
 885
 886static void dp8393x_class_init(ObjectClass *klass, void *data)
 887{
 888    DeviceClass *dc = DEVICE_CLASS(klass);
 889
 890    set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 891    dc->realize = dp8393x_realize;
 892    dc->reset = dp8393x_reset;
 893    dc->vmsd = &vmstate_dp8393x;
 894    dc->props = dp8393x_properties;
 895    /* Reason: dma_mr property can't be set */
 896    dc->cannot_instantiate_with_device_add_yet = true;
 897}
 898
 899static const TypeInfo dp8393x_info = {
 900    .name          = TYPE_DP8393X,
 901    .parent        = TYPE_SYS_BUS_DEVICE,
 902    .instance_size = sizeof(dp8393xState),
 903    .instance_init = dp8393x_instance_init,
 904    .class_init    = dp8393x_class_init,
 905};
 906
 907static void dp8393x_register_types(void)
 908{
 909    type_register_static(&dp8393x_info);
 910}
 911
 912type_init(dp8393x_register_types)
 913