qemu/hw/net/milkymist-minimac2.c
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   1/*
   2 *  QEMU model of the Milkymist minimac2 block.
   3 *
   4 *  Copyright (c) 2011 Michael Walle <michael@walle.cc>
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 *
  19 *
  20 * Specification available at:
  21 *   not available yet
  22 *
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "qapi/error.h"
  27#include "qemu-common.h"
  28#include "cpu.h" /* FIXME: why does this use TARGET_PAGE_ALIGN? */
  29#include "hw/hw.h"
  30#include "hw/sysbus.h"
  31#include "trace.h"
  32#include "net/net.h"
  33#include "qemu/error-report.h"
  34
  35#include <zlib.h>
  36
  37enum {
  38    R_SETUP = 0,
  39    R_MDIO,
  40    R_STATE0,
  41    R_COUNT0,
  42    R_STATE1,
  43    R_COUNT1,
  44    R_TXCOUNT,
  45    R_MAX
  46};
  47
  48enum {
  49    SETUP_PHY_RST = (1<<0),
  50};
  51
  52enum {
  53    MDIO_DO  = (1<<0),
  54    MDIO_DI  = (1<<1),
  55    MDIO_OE  = (1<<2),
  56    MDIO_CLK = (1<<3),
  57};
  58
  59enum {
  60    STATE_EMPTY   = 0,
  61    STATE_LOADED  = 1,
  62    STATE_PENDING = 2,
  63};
  64
  65enum {
  66    MDIO_OP_WRITE = 1,
  67    MDIO_OP_READ  = 2,
  68};
  69
  70enum mdio_state {
  71    MDIO_STATE_IDLE,
  72    MDIO_STATE_READING,
  73    MDIO_STATE_WRITING,
  74};
  75
  76enum {
  77    R_PHY_ID1  = 2,
  78    R_PHY_ID2  = 3,
  79    R_PHY_MAX  = 32
  80};
  81
  82#define MINIMAC2_MTU 1530
  83#define MINIMAC2_BUFFER_SIZE 2048
  84
  85struct MilkymistMinimac2MdioState {
  86    int last_clk;
  87    int count;
  88    uint32_t data;
  89    uint16_t data_out;
  90    int state;
  91
  92    uint8_t phy_addr;
  93    uint8_t reg_addr;
  94};
  95typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
  96
  97#define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2"
  98#define MILKYMIST_MINIMAC2(obj) \
  99    OBJECT_CHECK(MilkymistMinimac2State, (obj), TYPE_MILKYMIST_MINIMAC2)
 100
 101struct MilkymistMinimac2State {
 102    SysBusDevice parent_obj;
 103
 104    NICState *nic;
 105    NICConf conf;
 106    char *phy_model;
 107    MemoryRegion buffers;
 108    MemoryRegion regs_region;
 109
 110    qemu_irq rx_irq;
 111    qemu_irq tx_irq;
 112
 113    uint32_t regs[R_MAX];
 114
 115    MilkymistMinimac2MdioState mdio;
 116
 117    uint16_t phy_regs[R_PHY_MAX];
 118
 119    uint8_t *rx0_buf;
 120    uint8_t *rx1_buf;
 121    uint8_t *tx_buf;
 122};
 123typedef struct MilkymistMinimac2State MilkymistMinimac2State;
 124
 125static const uint8_t preamble_sfd[] = {
 126        0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
 127};
 128
 129static void minimac2_mdio_write_reg(MilkymistMinimac2State *s,
 130        uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
 131{
 132    trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value);
 133
 134    /* nop */
 135}
 136
 137static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s,
 138        uint8_t phy_addr, uint8_t reg_addr)
 139{
 140    uint16_t r = s->phy_regs[reg_addr];
 141
 142    trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r);
 143
 144    return r;
 145}
 146
 147static void minimac2_update_mdio(MilkymistMinimac2State *s)
 148{
 149    MilkymistMinimac2MdioState *m = &s->mdio;
 150
 151    /* detect rising clk edge */
 152    if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
 153        /* shift data in */
 154        int bit = ((s->regs[R_MDIO] & MDIO_DO)
 155                   && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0;
 156        m->data = (m->data << 1) | bit;
 157
 158        /* check for sync */
 159        if (m->data == 0xffffffff) {
 160            m->count = 32;
 161        }
 162
 163        if (m->count == 16) {
 164            uint8_t start = (m->data >> 14) & 0x3;
 165            uint8_t op = (m->data >> 12) & 0x3;
 166            uint8_t ta = (m->data) & 0x3;
 167
 168            if (start == 1 && op == MDIO_OP_WRITE && ta == 2) {
 169                m->state = MDIO_STATE_WRITING;
 170            } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) {
 171                m->state = MDIO_STATE_READING;
 172            } else {
 173                m->state = MDIO_STATE_IDLE;
 174            }
 175
 176            if (m->state != MDIO_STATE_IDLE) {
 177                m->phy_addr = (m->data >> 7) & 0x1f;
 178                m->reg_addr = (m->data >> 2) & 0x1f;
 179            }
 180
 181            if (m->state == MDIO_STATE_READING) {
 182                m->data_out = minimac2_mdio_read_reg(s, m->phy_addr,
 183                        m->reg_addr);
 184            }
 185        }
 186
 187        if (m->count < 16 && m->state == MDIO_STATE_READING) {
 188            int bit = (m->data_out & 0x8000) ? 1 : 0;
 189            m->data_out <<= 1;
 190
 191            if (bit) {
 192                s->regs[R_MDIO] |= MDIO_DI;
 193            } else {
 194                s->regs[R_MDIO] &= ~MDIO_DI;
 195            }
 196        }
 197
 198        if (m->count == 0 && m->state) {
 199            if (m->state == MDIO_STATE_WRITING) {
 200                uint16_t data = m->data & 0xffff;
 201                minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
 202            }
 203            m->state = MDIO_STATE_IDLE;
 204        }
 205        m->count--;
 206    }
 207
 208    m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0;
 209}
 210
 211static size_t assemble_frame(uint8_t *buf, size_t size,
 212        const uint8_t *payload, size_t payload_size)
 213{
 214    uint32_t crc;
 215
 216    if (size < payload_size + 12) {
 217        error_report("milkymist_minimac2: received too big ethernet frame");
 218        return 0;
 219    }
 220
 221    /* prepend preamble and sfd */
 222    memcpy(buf, preamble_sfd, 8);
 223
 224    /* now copy the payload */
 225    memcpy(buf + 8, payload, payload_size);
 226
 227    /* pad frame if needed */
 228    if (payload_size < 60) {
 229        memset(buf + payload_size + 8, 0, 60 - payload_size);
 230        payload_size = 60;
 231    }
 232
 233    /* append fcs */
 234    crc = cpu_to_le32(crc32(0, buf + 8, payload_size));
 235    memcpy(buf + payload_size + 8, &crc, 4);
 236
 237    return payload_size + 12;
 238}
 239
 240static void minimac2_tx(MilkymistMinimac2State *s)
 241{
 242    uint32_t txcount = s->regs[R_TXCOUNT];
 243    uint8_t *buf = s->tx_buf;
 244
 245    if (txcount < 64) {
 246        error_report("milkymist_minimac2: ethernet frame too small (%u < %u)",
 247                txcount, 64);
 248        goto err;
 249    }
 250
 251    if (txcount > MINIMAC2_MTU) {
 252        error_report("milkymist_minimac2: MTU exceeded (%u > %u)",
 253                txcount, MINIMAC2_MTU);
 254        goto err;
 255    }
 256
 257    if (memcmp(buf, preamble_sfd, 8) != 0) {
 258        error_report("milkymist_minimac2: frame doesn't contain the preamble "
 259                "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)",
 260                buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
 261        goto err;
 262    }
 263
 264    trace_milkymist_minimac2_tx_frame(txcount - 12);
 265
 266    /* send packet, skipping preamble and sfd */
 267    qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12);
 268
 269    s->regs[R_TXCOUNT] = 0;
 270
 271err:
 272    trace_milkymist_minimac2_pulse_irq_tx();
 273    qemu_irq_pulse(s->tx_irq);
 274}
 275
 276static void update_rx_interrupt(MilkymistMinimac2State *s)
 277{
 278    if (s->regs[R_STATE0] == STATE_PENDING
 279            || s->regs[R_STATE1] == STATE_PENDING) {
 280        trace_milkymist_minimac2_raise_irq_rx();
 281        qemu_irq_raise(s->rx_irq);
 282    } else {
 283        trace_milkymist_minimac2_lower_irq_rx();
 284        qemu_irq_lower(s->rx_irq);
 285    }
 286}
 287
 288static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 289{
 290    MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
 291
 292    uint32_t r_count;
 293    uint32_t r_state;
 294    uint8_t *rx_buf;
 295
 296    size_t frame_size;
 297
 298    trace_milkymist_minimac2_rx_frame(buf, size);
 299
 300    /* choose appropriate slot */
 301    if (s->regs[R_STATE0] == STATE_LOADED) {
 302        r_count = R_COUNT0;
 303        r_state = R_STATE0;
 304        rx_buf = s->rx0_buf;
 305    } else if (s->regs[R_STATE1] == STATE_LOADED) {
 306        r_count = R_COUNT1;
 307        r_state = R_STATE1;
 308        rx_buf = s->rx1_buf;
 309    } else {
 310        return 0;
 311    }
 312
 313    /* assemble frame */
 314    frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size);
 315
 316    if (frame_size == 0) {
 317        return size;
 318    }
 319
 320    trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size);
 321
 322    /* update slot */
 323    s->regs[r_count] = frame_size;
 324    s->regs[r_state] = STATE_PENDING;
 325
 326    update_rx_interrupt(s);
 327
 328    return size;
 329}
 330
 331static uint64_t
 332minimac2_read(void *opaque, hwaddr addr, unsigned size)
 333{
 334    MilkymistMinimac2State *s = opaque;
 335    uint32_t r = 0;
 336
 337    addr >>= 2;
 338    switch (addr) {
 339    case R_SETUP:
 340    case R_MDIO:
 341    case R_STATE0:
 342    case R_COUNT0:
 343    case R_STATE1:
 344    case R_COUNT1:
 345    case R_TXCOUNT:
 346        r = s->regs[addr];
 347        break;
 348
 349    default:
 350        error_report("milkymist_minimac2: read access to unknown register 0x"
 351                TARGET_FMT_plx, addr << 2);
 352        break;
 353    }
 354
 355    trace_milkymist_minimac2_memory_read(addr << 2, r);
 356
 357    return r;
 358}
 359
 360static int minimac2_can_rx(MilkymistMinimac2State *s)
 361{
 362    if (s->regs[R_STATE0] == STATE_LOADED) {
 363        return 1;
 364    }
 365    if (s->regs[R_STATE1] == STATE_LOADED) {
 366        return 1;
 367    }
 368
 369    return 0;
 370}
 371
 372static void
 373minimac2_write(void *opaque, hwaddr addr, uint64_t value,
 374               unsigned size)
 375{
 376    MilkymistMinimac2State *s = opaque;
 377
 378    trace_milkymist_minimac2_memory_write(addr, value);
 379
 380    addr >>= 2;
 381    switch (addr) {
 382    case R_MDIO:
 383    {
 384        /* MDIO_DI is read only */
 385        int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
 386        s->regs[R_MDIO] = value;
 387        if (mdio_di) {
 388            s->regs[R_MDIO] |= mdio_di;
 389        } else {
 390            s->regs[R_MDIO] &= ~mdio_di;
 391        }
 392
 393        minimac2_update_mdio(s);
 394    } break;
 395    case R_TXCOUNT:
 396        s->regs[addr] = value;
 397        if (value > 0) {
 398            minimac2_tx(s);
 399        }
 400        break;
 401    case R_STATE0:
 402    case R_STATE1:
 403        s->regs[addr] = value;
 404        update_rx_interrupt(s);
 405        if (minimac2_can_rx(s)) {
 406            qemu_flush_queued_packets(qemu_get_queue(s->nic));
 407        }
 408        break;
 409    case R_SETUP:
 410    case R_COUNT0:
 411    case R_COUNT1:
 412        s->regs[addr] = value;
 413        break;
 414
 415    default:
 416        error_report("milkymist_minimac2: write access to unknown register 0x"
 417                TARGET_FMT_plx, addr << 2);
 418        break;
 419    }
 420}
 421
 422static const MemoryRegionOps minimac2_ops = {
 423    .read = minimac2_read,
 424    .write = minimac2_write,
 425    .valid = {
 426        .min_access_size = 4,
 427        .max_access_size = 4,
 428    },
 429    .endianness = DEVICE_NATIVE_ENDIAN,
 430};
 431
 432static void milkymist_minimac2_reset(DeviceState *d)
 433{
 434    MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(d);
 435    int i;
 436
 437    for (i = 0; i < R_MAX; i++) {
 438        s->regs[i] = 0;
 439    }
 440    for (i = 0; i < R_PHY_MAX; i++) {
 441        s->phy_regs[i] = 0;
 442    }
 443
 444    /* defaults */
 445    s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */
 446    s->phy_regs[R_PHY_ID2] = 0x161a;
 447}
 448
 449static NetClientInfo net_milkymist_minimac2_info = {
 450    .type = NET_CLIENT_DRIVER_NIC,
 451    .size = sizeof(NICState),
 452    .receive = minimac2_rx,
 453};
 454
 455static int milkymist_minimac2_init(SysBusDevice *sbd)
 456{
 457    DeviceState *dev = DEVICE(sbd);
 458    MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(dev);
 459    size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
 460
 461    sysbus_init_irq(sbd, &s->rx_irq);
 462    sysbus_init_irq(sbd, &s->tx_irq);
 463
 464    memory_region_init_io(&s->regs_region, OBJECT(dev), &minimac2_ops, s,
 465                          "milkymist-minimac2", R_MAX * 4);
 466    sysbus_init_mmio(sbd, &s->regs_region);
 467
 468    /* register buffers memory */
 469    memory_region_init_ram(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers",
 470                           buffers_size, &error_fatal);
 471    vmstate_register_ram_global(&s->buffers);
 472    s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
 473    s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
 474    s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
 475
 476    sysbus_init_mmio(sbd, &s->buffers);
 477
 478    qemu_macaddr_default_if_unset(&s->conf.macaddr);
 479    s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
 480                          object_get_typename(OBJECT(dev)), dev->id, s);
 481    qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 482
 483    return 0;
 484}
 485
 486static const VMStateDescription vmstate_milkymist_minimac2_mdio = {
 487    .name = "milkymist-minimac2-mdio",
 488    .version_id = 1,
 489    .minimum_version_id = 1,
 490    .fields = (VMStateField[]) {
 491        VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState),
 492        VMSTATE_INT32(count, MilkymistMinimac2MdioState),
 493        VMSTATE_UINT32(data, MilkymistMinimac2MdioState),
 494        VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState),
 495        VMSTATE_INT32(state, MilkymistMinimac2MdioState),
 496        VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState),
 497        VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState),
 498        VMSTATE_END_OF_LIST()
 499    }
 500};
 501
 502static const VMStateDescription vmstate_milkymist_minimac2 = {
 503    .name = "milkymist-minimac2",
 504    .version_id = 1,
 505    .minimum_version_id = 1,
 506    .fields = (VMStateField[]) {
 507        VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX),
 508        VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX),
 509        VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0,
 510                vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState),
 511        VMSTATE_END_OF_LIST()
 512    }
 513};
 514
 515static Property milkymist_minimac2_properties[] = {
 516    DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf),
 517    DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model),
 518    DEFINE_PROP_END_OF_LIST(),
 519};
 520
 521static void milkymist_minimac2_class_init(ObjectClass *klass, void *data)
 522{
 523    DeviceClass *dc = DEVICE_CLASS(klass);
 524    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 525
 526    k->init = milkymist_minimac2_init;
 527    dc->reset = milkymist_minimac2_reset;
 528    dc->vmsd = &vmstate_milkymist_minimac2;
 529    dc->props = milkymist_minimac2_properties;
 530}
 531
 532static const TypeInfo milkymist_minimac2_info = {
 533    .name          = TYPE_MILKYMIST_MINIMAC2,
 534    .parent        = TYPE_SYS_BUS_DEVICE,
 535    .instance_size = sizeof(MilkymistMinimac2State),
 536    .class_init    = milkymist_minimac2_class_init,
 537};
 538
 539static void milkymist_minimac2_register_types(void)
 540{
 541    type_register_static(&milkymist_minimac2_info);
 542}
 543
 544type_init(milkymist_minimac2_register_types)
 545