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23#include "qemu/osdep.h"
24#include "hw/pci/pci_ids.h"
25#include "hw/pci/msi.h"
26#include "hw/pci/pcie.h"
27#include "ioh3420.h"
28#include "qapi/error.h"
29
30#define PCI_DEVICE_ID_IOH_EPORT 0x3420
31#define PCI_DEVICE_ID_IOH_REV 0x2
32#define IOH_EP_SSVID_OFFSET 0x40
33#define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL
34#define IOH_EP_SSVID_SSID 0
35#define IOH_EP_MSI_OFFSET 0x60
36#define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT
37#define IOH_EP_MSI_NR_VECTOR 2
38#define IOH_EP_EXP_OFFSET 0x90
39#define IOH_EP_AER_OFFSET 0x100
40
41
42
43
44
45
46static uint8_t ioh3420_aer_vector(const PCIDevice *d)
47{
48 switch (msi_nr_vectors_allocated(d)) {
49 case 1:
50 return 0;
51 case 2:
52 return 1;
53 case 4:
54 case 8:
55 case 16:
56 case 32:
57 default:
58 break;
59 }
60 abort();
61 return 0;
62}
63
64static void ioh3420_aer_vector_update(PCIDevice *d)
65{
66 pcie_aer_root_set_vector(d, ioh3420_aer_vector(d));
67}
68
69static void ioh3420_write_config(PCIDevice *d,
70 uint32_t address, uint32_t val, int len)
71{
72 uint32_t root_cmd =
73 pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
74
75 pci_bridge_write_config(d, address, val, len);
76 ioh3420_aer_vector_update(d);
77 pcie_cap_slot_write_config(d, address, val, len);
78 pcie_aer_write_config(d, address, val, len);
79 pcie_aer_root_write_config(d, address, val, len, root_cmd);
80}
81
82static void ioh3420_reset(DeviceState *qdev)
83{
84 PCIDevice *d = PCI_DEVICE(qdev);
85
86 ioh3420_aer_vector_update(d);
87 pcie_cap_root_reset(d);
88 pcie_cap_deverr_reset(d);
89 pcie_cap_slot_reset(d);
90 pcie_cap_arifwd_reset(d);
91 pcie_aer_root_reset(d);
92 pci_bridge_reset(qdev);
93 pci_bridge_disable_base_limit(d);
94}
95
96static int ioh3420_initfn(PCIDevice *d)
97{
98 PCIEPort *p = PCIE_PORT(d);
99 PCIESlot *s = PCIE_SLOT(d);
100 int rc;
101 Error *err = NULL;
102
103 pci_config_set_interrupt_pin(d->config, 1);
104 pci_bridge_initfn(d, TYPE_PCIE_BUS);
105 pcie_port_init_reg(d);
106
107 rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
108 IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
109 if (rc < 0) {
110 goto err_bridge;
111 }
112
113 rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
114 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
115 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err);
116 if (rc < 0) {
117 assert(rc == -ENOTSUP);
118 error_report_err(err);
119 goto err_bridge;
120 }
121
122 rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
123 if (rc < 0) {
124 goto err_msi;
125 }
126
127 pcie_cap_arifwd_init(d);
128 pcie_cap_deverr_init(d);
129 pcie_cap_slot_init(d, s->slot);
130 pcie_cap_root_init(d);
131
132 pcie_chassis_create(s->chassis);
133 rc = pcie_chassis_add_slot(s);
134 if (rc < 0) {
135 goto err_pcie_cap;
136 }
137
138 rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF);
139 if (rc < 0) {
140 goto err;
141 }
142 pcie_aer_root_init(d);
143 ioh3420_aer_vector_update(d);
144
145 return 0;
146
147err:
148 pcie_chassis_del_slot(s);
149err_pcie_cap:
150 pcie_cap_exit(d);
151err_msi:
152 msi_uninit(d);
153err_bridge:
154 pci_bridge_exitfn(d);
155 return rc;
156}
157
158static void ioh3420_exitfn(PCIDevice *d)
159{
160 PCIESlot *s = PCIE_SLOT(d);
161
162 pcie_aer_exit(d);
163 pcie_chassis_del_slot(s);
164 pcie_cap_exit(d);
165 msi_uninit(d);
166 pci_bridge_exitfn(d);
167}
168
169static Property ioh3420_props[] = {
170 DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
171 QEMU_PCIE_SLTCAP_PCP_BITNR, true),
172 DEFINE_PROP_END_OF_LIST()
173};
174
175static const VMStateDescription vmstate_ioh3420 = {
176 .name = "ioh-3240-express-root-port",
177 .version_id = 1,
178 .minimum_version_id = 1,
179 .post_load = pcie_cap_slot_post_load,
180 .fields = (VMStateField[]) {
181 VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
182 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
183 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
184 VMSTATE_END_OF_LIST()
185 }
186};
187
188static void ioh3420_class_init(ObjectClass *klass, void *data)
189{
190 DeviceClass *dc = DEVICE_CLASS(klass);
191 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
192
193 k->is_express = 1;
194 k->is_bridge = 1;
195 k->config_write = ioh3420_write_config;
196 k->init = ioh3420_initfn;
197 k->exit = ioh3420_exitfn;
198 k->vendor_id = PCI_VENDOR_ID_INTEL;
199 k->device_id = PCI_DEVICE_ID_IOH_EPORT;
200 k->revision = PCI_DEVICE_ID_IOH_REV;
201 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
202 dc->desc = "Intel IOH device id 3420 PCIE Root Port";
203 dc->reset = ioh3420_reset;
204 dc->vmsd = &vmstate_ioh3420;
205 dc->props = ioh3420_props;
206}
207
208static const TypeInfo ioh3420_info = {
209 .name = "ioh3420",
210 .parent = TYPE_PCIE_SLOT,
211 .class_init = ioh3420_class_init,
212};
213
214static void ioh3420_register_types(void)
215{
216 type_register_static(&ioh3420_info);
217}
218
219type_init(ioh3420_register_types)
220