LXR qemu/hw/pci-bridge/xio3130

   1/*
   2 * xio3130_upstream.c
   3 * TI X3130 pci express upstream port switch
   4 *
   5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6 *                    VA Linux Systems Japan K.K.
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License along
  19 * with this program; if not, see <http://www.gnu.org/licenses/>.
  20 */
  21
  22#include "qemu/osdep.h"
  23#include "hw/pci/pci_ids.h"
  24#include "hw/pci/msi.h"
  25#include "hw/pci/pcie.h"
  26#include "xio3130_upstream.h"
  27#include "qapi/error.h"
  28
  29#define PCI_DEVICE_ID_TI_XIO3130U       0x8232  /* upstream port */
  30#define XIO3130_REVISION                0x2
  31#define XIO3130_MSI_OFFSET              0x70
  32#define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  33#define XIO3130_MSI_NR_VECTOR           1
  34#define XIO3130_SSVID_OFFSET            0x80
  35#define XIO3130_SSVID_SVID              0
  36#define XIO3130_SSVID_SSID              0
  37#define XIO3130_EXP_OFFSET              0x90
  38#define XIO3130_AER_OFFSET              0x100
  39
  40static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
  41                                          uint32_t val, int len)
  42{
  43    pci_bridge_write_config(d, address, val, len);
  44    pcie_cap_flr_write_config(d, address, val, len);
  45    pcie_aer_write_config(d, address, val, len);
  46}
  47
  48static void xio3130_upstream_reset(DeviceState *qdev)
  49{
  50    PCIDevice *d = PCI_DEVICE(qdev);
  51
  52    pci_bridge_reset(qdev);
  53    pcie_cap_deverr_reset(d);
  54}
  55
  56static int xio3130_upstream_initfn(PCIDevice *d)
  57{
  58    PCIEPort *p = PCIE_PORT(d);
  59    int rc;
  60    Error *err = NULL;
  61
  62    pci_bridge_initfn(d, TYPE_PCIE_BUS);
  63    pcie_port_init_reg(d);
  64
  65    rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  66                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  67                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err);
  68    if (rc < 0) {
  69        assert(rc == -ENOTSUP);
  70        error_report_err(err);
  71        goto err_bridge;
  72    }
  73
  74    rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  75                               XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
  76    if (rc < 0) {
  77        goto err_bridge;
  78    }
  79
  80    rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
  81                       p->port);
  82    if (rc < 0) {
  83        goto err_msi;
  84    }
  85    pcie_cap_flr_init(d);
  86    pcie_cap_deverr_init(d);
  87
  88    rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF);
  89    if (rc < 0) {
  90        goto err;
  91    }
  92
  93    return 0;
  94
  95err:
  96    pcie_cap_exit(d);
  97err_msi:
  98    msi_uninit(d);
  99err_bridge:
 100    pci_bridge_exitfn(d);
 101    return rc;
 102}
 103
 104static void xio3130_upstream_exitfn(PCIDevice *d)
 105{
 106    pcie_aer_exit(d);
 107    pcie_cap_exit(d);
 108    msi_uninit(d);
 109    pci_bridge_exitfn(d);
 110}
 111
 112PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
 113                             const char *bus_name, pci_map_irq_fn map_irq,
 114                             uint8_t port)
 115{
 116    PCIDevice *d;
 117    PCIBridge *br;
 118    DeviceState *qdev;
 119
 120    d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream");
 121    if (!d) {
 122        return NULL;
 123    }
 124    br = PCI_BRIDGE(d);
 125
 126    qdev = DEVICE(d);
 127    pci_bridge_map_irq(br, bus_name, map_irq);
 128    qdev_prop_set_uint8(qdev, "port", port);
 129    qdev_init_nofail(qdev);
 130
 131    return PCIE_PORT(d);
 132}
 133
 134static const VMStateDescription vmstate_xio3130_upstream = {
 135    .name = "xio3130-express-upstream-port",
 136    .version_id = 1,
 137    .minimum_version_id = 1,
 138    .fields = (VMStateField[]) {
 139        VMSTATE_PCIE_DEVICE(parent_obj.parent_obj, PCIEPort),
 140        VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0,
 141                       vmstate_pcie_aer_log, PCIEAERLog),
 142        VMSTATE_END_OF_LIST()
 143    }
 144};
 145
 146static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
 147{
 148    DeviceClass *dc = DEVICE_CLASS(klass);
 149    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 150
 151    k->is_express = 1;
 152    k->is_bridge = 1;
 153    k->config_write = xio3130_upstream_write_config;
 154    k->init = xio3130_upstream_initfn;
 155    k->exit = xio3130_upstream_exitfn;
 156    k->vendor_id = PCI_VENDOR_ID_TI;
 157    k->device_id = PCI_DEVICE_ID_TI_XIO3130U;
 158    k->revision = XIO3130_REVISION;
 159    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 160    dc->desc = "TI X3130 Upstream Port of PCI Express Switch";
 161    dc->reset = xio3130_upstream_reset;
 162    dc->vmsd = &vmstate_xio3130_upstream;
 163}
 164
 165static const TypeInfo xio3130_upstream_info = {
 166    .name          = "x3130-upstream",
 167    .parent        = TYPE_PCIE_PORT,
 168    .class_init    = xio3130_upstream_class_init,
 169};
 170
 171static void xio3130_upstream_register_types(void)
 172{
 173    type_register_static(&xio3130_upstream_info);
 174}
 175
 176type_init(xio3130_upstream_register_types)
 177