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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qemu-common.h"
27#include "cpu.h"
28#include "hw/sysbus.h"
29#include "qemu/error-report.h"
30#include "qemu/timer.h"
31#include "hw/sparc/sun4m.h"
32#include "hw/timer/m48t59.h"
33#include "hw/sparc/sparc32_dma.h"
34#include "hw/block/fdc.h"
35#include "sysemu/sysemu.h"
36#include "net/net.h"
37#include "hw/boards.h"
38#include "hw/scsi/esp.h"
39#include "hw/i386/pc.h"
40#include "hw/isa/isa.h"
41#include "hw/nvram/sun_nvram.h"
42#include "hw/nvram/chrp_nvram.h"
43#include "hw/nvram/fw_cfg.h"
44#include "hw/char/escc.h"
45#include "hw/empty_slot.h"
46#include "hw/loader.h"
47#include "elf.h"
48#include "sysemu/block-backend.h"
49#include "trace.h"
50#include "qemu/cutils.h"
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68#define KERNEL_LOAD_ADDR 0x00004000
69#define CMDLINE_ADDR 0x007ff000
70#define INITRD_LOAD_ADDR 0x00800000
71#define PROM_SIZE_MAX (1024 * 1024)
72#define PROM_VADDR 0xffd00000
73#define PROM_FILENAME "openbios-sparc32"
74#define CFG_ADDR 0xd00000510ULL
75#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
76#define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
77#define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
78
79#define MAX_CPUS 16
80#define MAX_PILS 16
81#define MAX_VSIMMS 4
82
83#define ESCC_CLOCK 4915200
84
85struct sun4m_hwdef {
86 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
87 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
88 hwaddr serial_base, fd_base;
89 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
90 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
91 hwaddr bpp_base, dbri_base, sx_base;
92 struct {
93 hwaddr reg_base, vram_base;
94 } vsimm[MAX_VSIMMS];
95 hwaddr ecc_base;
96 uint64_t max_mem;
97 const char * const default_cpu_model;
98 uint32_t ecc_version;
99 uint32_t iommu_version;
100 uint16_t machine_id;
101 uint8_t nvram_machine_id;
102};
103
104void DMA_init(ISABus *bus, int high_page_enable)
105{
106}
107
108static void fw_cfg_boot_set(void *opaque, const char *boot_device,
109 Error **errp)
110{
111 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
112}
113
114static void nvram_init(Nvram *nvram, uint8_t *macaddr,
115 const char *cmdline, const char *boot_devices,
116 ram_addr_t RAM_size, uint32_t kernel_size,
117 int width, int height, int depth,
118 int nvram_machine_id, const char *arch)
119{
120 unsigned int i;
121 int sysp_end;
122 uint8_t image[0x1ff0];
123 NvramClass *k = NVRAM_GET_CLASS(nvram);
124
125 memset(image, '\0', sizeof(image));
126
127
128 sysp_end = chrp_nvram_create_system_partition(image, 0);
129
130
131 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
132
133 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
134 nvram_machine_id);
135
136 for (i = 0; i < sizeof(image); i++) {
137 (k->write)(nvram, i, image[i]);
138 }
139}
140
141void cpu_check_irqs(CPUSPARCState *env)
142{
143 CPUState *cs;
144
145 if (env->pil_in && (env->interrupt_index == 0 ||
146 (env->interrupt_index & ~15) == TT_EXTINT)) {
147 unsigned int i;
148
149 for (i = 15; i > 0; i--) {
150 if (env->pil_in & (1 << i)) {
151 int old_interrupt = env->interrupt_index;
152
153 env->interrupt_index = TT_EXTINT | i;
154 if (old_interrupt != env->interrupt_index) {
155 cs = CPU(sparc_env_get_cpu(env));
156 trace_sun4m_cpu_interrupt(i);
157 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
158 }
159 break;
160 }
161 }
162 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
163 cs = CPU(sparc_env_get_cpu(env));
164 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
165 env->interrupt_index = 0;
166 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
167 }
168}
169
170static void cpu_kick_irq(SPARCCPU *cpu)
171{
172 CPUSPARCState *env = &cpu->env;
173 CPUState *cs = CPU(cpu);
174
175 cs->halted = 0;
176 cpu_check_irqs(env);
177 qemu_cpu_kick(cs);
178}
179
180static void cpu_set_irq(void *opaque, int irq, int level)
181{
182 SPARCCPU *cpu = opaque;
183 CPUSPARCState *env = &cpu->env;
184
185 if (level) {
186 trace_sun4m_cpu_set_irq_raise(irq);
187 env->pil_in |= 1 << irq;
188 cpu_kick_irq(cpu);
189 } else {
190 trace_sun4m_cpu_set_irq_lower(irq);
191 env->pil_in &= ~(1 << irq);
192 cpu_check_irqs(env);
193 }
194}
195
196static void dummy_cpu_set_irq(void *opaque, int irq, int level)
197{
198}
199
200static void main_cpu_reset(void *opaque)
201{
202 SPARCCPU *cpu = opaque;
203 CPUState *cs = CPU(cpu);
204
205 cpu_reset(cs);
206 cs->halted = 0;
207}
208
209static void secondary_cpu_reset(void *opaque)
210{
211 SPARCCPU *cpu = opaque;
212 CPUState *cs = CPU(cpu);
213
214 cpu_reset(cs);
215 cs->halted = 1;
216}
217
218static void cpu_halt_signal(void *opaque, int irq, int level)
219{
220 if (level && current_cpu) {
221 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
222 }
223}
224
225static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
226{
227 return addr - 0xf0000000ULL;
228}
229
230static unsigned long sun4m_load_kernel(const char *kernel_filename,
231 const char *initrd_filename,
232 ram_addr_t RAM_size)
233{
234 int linux_boot;
235 unsigned int i;
236 long initrd_size, kernel_size;
237 uint8_t *ptr;
238
239 linux_boot = (kernel_filename != NULL);
240
241 kernel_size = 0;
242 if (linux_boot) {
243 int bswap_needed;
244
245#ifdef BSWAP_NEEDED
246 bswap_needed = 1;
247#else
248 bswap_needed = 0;
249#endif
250 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
251 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
252 if (kernel_size < 0)
253 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
254 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
255 TARGET_PAGE_SIZE);
256 if (kernel_size < 0)
257 kernel_size = load_image_targphys(kernel_filename,
258 KERNEL_LOAD_ADDR,
259 RAM_size - KERNEL_LOAD_ADDR);
260 if (kernel_size < 0) {
261 fprintf(stderr, "qemu: could not load kernel '%s'\n",
262 kernel_filename);
263 exit(1);
264 }
265
266
267 initrd_size = 0;
268 if (initrd_filename) {
269 initrd_size = load_image_targphys(initrd_filename,
270 INITRD_LOAD_ADDR,
271 RAM_size - INITRD_LOAD_ADDR);
272 if (initrd_size < 0) {
273 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
274 initrd_filename);
275 exit(1);
276 }
277 }
278 if (initrd_size > 0) {
279 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
280 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
281 if (ldl_p(ptr) == 0x48647253) {
282 stl_p(ptr + 16, INITRD_LOAD_ADDR);
283 stl_p(ptr + 20, initrd_size);
284 break;
285 }
286 }
287 }
288 }
289 return kernel_size;
290}
291
292static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
293{
294 DeviceState *dev;
295 SysBusDevice *s;
296
297 dev = qdev_create(NULL, "iommu");
298 qdev_prop_set_uint32(dev, "version", version);
299 qdev_init_nofail(dev);
300 s = SYS_BUS_DEVICE(dev);
301 sysbus_connect_irq(s, 0, irq);
302 sysbus_mmio_map(s, 0, addr);
303
304 return s;
305}
306
307static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
308 void *iommu, qemu_irq *dev_irq, int is_ledma)
309{
310 DeviceState *dev;
311 SysBusDevice *s;
312
313 dev = qdev_create(NULL, "sparc32_dma");
314 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
315 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
316 qdev_init_nofail(dev);
317 s = SYS_BUS_DEVICE(dev);
318 sysbus_connect_irq(s, 0, parent_irq);
319 *dev_irq = qdev_get_gpio_in(dev, 0);
320 sysbus_mmio_map(s, 0, daddr);
321
322 return s;
323}
324
325static void lance_init(NICInfo *nd, hwaddr leaddr,
326 void *dma_opaque, qemu_irq irq)
327{
328 DeviceState *dev;
329 SysBusDevice *s;
330 qemu_irq reset;
331
332 qemu_check_nic_model(&nd_table[0], "lance");
333
334 dev = qdev_create(NULL, "lance");
335 qdev_set_nic_properties(dev, nd);
336 qdev_prop_set_ptr(dev, "dma", dma_opaque);
337 qdev_init_nofail(dev);
338 s = SYS_BUS_DEVICE(dev);
339 sysbus_mmio_map(s, 0, leaddr);
340 sysbus_connect_irq(s, 0, irq);
341 reset = qdev_get_gpio_in(dev, 0);
342 qdev_connect_gpio_out(dma_opaque, 0, reset);
343}
344
345static DeviceState *slavio_intctl_init(hwaddr addr,
346 hwaddr addrg,
347 qemu_irq **parent_irq)
348{
349 DeviceState *dev;
350 SysBusDevice *s;
351 unsigned int i, j;
352
353 dev = qdev_create(NULL, "slavio_intctl");
354 qdev_init_nofail(dev);
355
356 s = SYS_BUS_DEVICE(dev);
357
358 for (i = 0; i < MAX_CPUS; i++) {
359 for (j = 0; j < MAX_PILS; j++) {
360 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
361 }
362 }
363 sysbus_mmio_map(s, 0, addrg);
364 for (i = 0; i < MAX_CPUS; i++) {
365 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
366 }
367
368 return dev;
369}
370
371#define SYS_TIMER_OFFSET 0x10000ULL
372#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
373
374static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
375 qemu_irq *cpu_irqs, unsigned int num_cpus)
376{
377 DeviceState *dev;
378 SysBusDevice *s;
379 unsigned int i;
380
381 dev = qdev_create(NULL, "slavio_timer");
382 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
383 qdev_init_nofail(dev);
384 s = SYS_BUS_DEVICE(dev);
385 sysbus_connect_irq(s, 0, master_irq);
386 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
387
388 for (i = 0; i < MAX_CPUS; i++) {
389 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
390 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
391 }
392}
393
394static qemu_irq slavio_system_powerdown;
395
396static void slavio_powerdown_req(Notifier *n, void *opaque)
397{
398 qemu_irq_raise(slavio_system_powerdown);
399}
400
401static Notifier slavio_system_powerdown_notifier = {
402 .notify = slavio_powerdown_req
403};
404
405#define MISC_LEDS 0x01600000
406#define MISC_CFG 0x01800000
407#define MISC_DIAG 0x01a00000
408#define MISC_MDM 0x01b00000
409#define MISC_SYS 0x01f00000
410
411static void slavio_misc_init(hwaddr base,
412 hwaddr aux1_base,
413 hwaddr aux2_base, qemu_irq irq,
414 qemu_irq fdc_tc)
415{
416 DeviceState *dev;
417 SysBusDevice *s;
418
419 dev = qdev_create(NULL, "slavio_misc");
420 qdev_init_nofail(dev);
421 s = SYS_BUS_DEVICE(dev);
422 if (base) {
423
424
425 sysbus_mmio_map(s, 0, base + MISC_CFG);
426
427 sysbus_mmio_map(s, 1, base + MISC_DIAG);
428
429 sysbus_mmio_map(s, 2, base + MISC_MDM);
430
431
432 sysbus_mmio_map(s, 3, base + MISC_LEDS);
433
434
435 sysbus_mmio_map(s, 4, base + MISC_SYS);
436 }
437 if (aux1_base) {
438
439 sysbus_mmio_map(s, 5, aux1_base);
440 }
441 if (aux2_base) {
442
443 sysbus_mmio_map(s, 6, aux2_base);
444 }
445 sysbus_connect_irq(s, 0, irq);
446 sysbus_connect_irq(s, 1, fdc_tc);
447 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
448 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
449}
450
451static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
452{
453 DeviceState *dev;
454 SysBusDevice *s;
455
456 dev = qdev_create(NULL, "eccmemctl");
457 qdev_prop_set_uint32(dev, "version", version);
458 qdev_init_nofail(dev);
459 s = SYS_BUS_DEVICE(dev);
460 sysbus_connect_irq(s, 0, irq);
461 sysbus_mmio_map(s, 0, base);
462 if (version == 0) {
463 sysbus_mmio_map(s, 1, base + 0x1000);
464 }
465}
466
467static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
468{
469 DeviceState *dev;
470 SysBusDevice *s;
471
472 dev = qdev_create(NULL, "apc");
473 qdev_init_nofail(dev);
474 s = SYS_BUS_DEVICE(dev);
475
476 sysbus_mmio_map(s, 0, power_base);
477 sysbus_connect_irq(s, 0, cpu_halt);
478}
479
480static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
481 int height, int depth)
482{
483 DeviceState *dev;
484 SysBusDevice *s;
485
486 dev = qdev_create(NULL, "SUNW,tcx");
487 qdev_prop_set_uint32(dev, "vram_size", vram_size);
488 qdev_prop_set_uint16(dev, "width", width);
489 qdev_prop_set_uint16(dev, "height", height);
490 qdev_prop_set_uint16(dev, "depth", depth);
491 qdev_prop_set_uint64(dev, "prom_addr", addr);
492 qdev_init_nofail(dev);
493 s = SYS_BUS_DEVICE(dev);
494
495
496 sysbus_mmio_map(s, 0, addr);
497
498 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
499
500 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
501
502 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
503
504 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
505
506 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
507
508 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
509
510 if (depth == 8) {
511 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
512 } else {
513 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
514 }
515
516 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
517
518 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
519
520 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
521
522 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
523
524 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
525
526 if (depth == 8) {
527 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
528 }
529
530 sysbus_connect_irq(s, 0, irq);
531}
532
533static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
534 int height, int depth)
535{
536 DeviceState *dev;
537 SysBusDevice *s;
538
539 dev = qdev_create(NULL, "cgthree");
540 qdev_prop_set_uint32(dev, "vram-size", vram_size);
541 qdev_prop_set_uint16(dev, "width", width);
542 qdev_prop_set_uint16(dev, "height", height);
543 qdev_prop_set_uint16(dev, "depth", depth);
544 qdev_prop_set_uint64(dev, "prom-addr", addr);
545 qdev_init_nofail(dev);
546 s = SYS_BUS_DEVICE(dev);
547
548
549 sysbus_mmio_map(s, 0, addr);
550
551 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
552
553 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
554
555 sysbus_connect_irq(s, 0, irq);
556}
557
558
559
560#define TYPE_MACIO_ID_REGISTER "macio_idreg"
561
562static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
563
564static void idreg_init(hwaddr addr)
565{
566 DeviceState *dev;
567 SysBusDevice *s;
568
569 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
570 qdev_init_nofail(dev);
571 s = SYS_BUS_DEVICE(dev);
572
573 sysbus_mmio_map(s, 0, addr);
574 cpu_physical_memory_write_rom(&address_space_memory,
575 addr, idreg_data, sizeof(idreg_data));
576}
577
578#define MACIO_ID_REGISTER(obj) \
579 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
580
581typedef struct IDRegState {
582 SysBusDevice parent_obj;
583
584 MemoryRegion mem;
585} IDRegState;
586
587static int idreg_init1(SysBusDevice *dev)
588{
589 IDRegState *s = MACIO_ID_REGISTER(dev);
590
591 memory_region_init_ram(&s->mem, OBJECT(s),
592 "sun4m.idreg", sizeof(idreg_data), &error_fatal);
593 vmstate_register_ram_global(&s->mem);
594 memory_region_set_readonly(&s->mem, true);
595 sysbus_init_mmio(dev, &s->mem);
596 return 0;
597}
598
599static void idreg_class_init(ObjectClass *klass, void *data)
600{
601 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
602
603 k->init = idreg_init1;
604}
605
606static const TypeInfo idreg_info = {
607 .name = TYPE_MACIO_ID_REGISTER,
608 .parent = TYPE_SYS_BUS_DEVICE,
609 .instance_size = sizeof(IDRegState),
610 .class_init = idreg_class_init,
611};
612
613#define TYPE_TCX_AFX "tcx_afx"
614#define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
615
616typedef struct AFXState {
617 SysBusDevice parent_obj;
618
619 MemoryRegion mem;
620} AFXState;
621
622
623static void afx_init(hwaddr addr)
624{
625 DeviceState *dev;
626 SysBusDevice *s;
627
628 dev = qdev_create(NULL, TYPE_TCX_AFX);
629 qdev_init_nofail(dev);
630 s = SYS_BUS_DEVICE(dev);
631
632 sysbus_mmio_map(s, 0, addr);
633}
634
635static int afx_init1(SysBusDevice *dev)
636{
637 AFXState *s = TCX_AFX(dev);
638
639 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal);
640 vmstate_register_ram_global(&s->mem);
641 sysbus_init_mmio(dev, &s->mem);
642 return 0;
643}
644
645static void afx_class_init(ObjectClass *klass, void *data)
646{
647 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
648
649 k->init = afx_init1;
650}
651
652static const TypeInfo afx_info = {
653 .name = TYPE_TCX_AFX,
654 .parent = TYPE_SYS_BUS_DEVICE,
655 .instance_size = sizeof(AFXState),
656 .class_init = afx_class_init,
657};
658
659#define TYPE_OPENPROM "openprom"
660#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
661
662typedef struct PROMState {
663 SysBusDevice parent_obj;
664
665 MemoryRegion prom;
666} PROMState;
667
668
669static uint64_t translate_prom_address(void *opaque, uint64_t addr)
670{
671 hwaddr *base_addr = (hwaddr *)opaque;
672 return addr + *base_addr - PROM_VADDR;
673}
674
675static void prom_init(hwaddr addr, const char *bios_name)
676{
677 DeviceState *dev;
678 SysBusDevice *s;
679 char *filename;
680 int ret;
681
682 dev = qdev_create(NULL, TYPE_OPENPROM);
683 qdev_init_nofail(dev);
684 s = SYS_BUS_DEVICE(dev);
685
686 sysbus_mmio_map(s, 0, addr);
687
688
689 if (bios_name == NULL) {
690 bios_name = PROM_FILENAME;
691 }
692 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
693 if (filename) {
694 ret = load_elf(filename, translate_prom_address, &addr, NULL,
695 NULL, NULL, 1, EM_SPARC, 0, 0);
696 if (ret < 0 || ret > PROM_SIZE_MAX) {
697 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
698 }
699 g_free(filename);
700 } else {
701 ret = -1;
702 }
703 if (ret < 0 || ret > PROM_SIZE_MAX) {
704 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
705 exit(1);
706 }
707}
708
709static int prom_init1(SysBusDevice *dev)
710{
711 PROMState *s = OPENPROM(dev);
712
713 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
714 &error_fatal);
715 vmstate_register_ram_global(&s->prom);
716 memory_region_set_readonly(&s->prom, true);
717 sysbus_init_mmio(dev, &s->prom);
718 return 0;
719}
720
721static Property prom_properties[] = {
722 {},
723};
724
725static void prom_class_init(ObjectClass *klass, void *data)
726{
727 DeviceClass *dc = DEVICE_CLASS(klass);
728 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
729
730 k->init = prom_init1;
731 dc->props = prom_properties;
732}
733
734static const TypeInfo prom_info = {
735 .name = TYPE_OPENPROM,
736 .parent = TYPE_SYS_BUS_DEVICE,
737 .instance_size = sizeof(PROMState),
738 .class_init = prom_class_init,
739};
740
741#define TYPE_SUN4M_MEMORY "memory"
742#define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
743
744typedef struct RamDevice {
745 SysBusDevice parent_obj;
746
747 MemoryRegion ram;
748 uint64_t size;
749} RamDevice;
750
751
752static int ram_init1(SysBusDevice *dev)
753{
754 RamDevice *d = SUN4M_RAM(dev);
755
756 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
757 d->size);
758 sysbus_init_mmio(dev, &d->ram);
759 return 0;
760}
761
762static void ram_init(hwaddr addr, ram_addr_t RAM_size,
763 uint64_t max_mem)
764{
765 DeviceState *dev;
766 SysBusDevice *s;
767 RamDevice *d;
768
769
770 if ((uint64_t)RAM_size > max_mem) {
771 fprintf(stderr,
772 "qemu: Too much memory for this machine: %d, maximum %d\n",
773 (unsigned int)(RAM_size / (1024 * 1024)),
774 (unsigned int)(max_mem / (1024 * 1024)));
775 exit(1);
776 }
777 dev = qdev_create(NULL, "memory");
778 s = SYS_BUS_DEVICE(dev);
779
780 d = SUN4M_RAM(dev);
781 d->size = RAM_size;
782 qdev_init_nofail(dev);
783
784 sysbus_mmio_map(s, 0, addr);
785}
786
787static Property ram_properties[] = {
788 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
789 DEFINE_PROP_END_OF_LIST(),
790};
791
792static void ram_class_init(ObjectClass *klass, void *data)
793{
794 DeviceClass *dc = DEVICE_CLASS(klass);
795 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
796
797 k->init = ram_init1;
798 dc->props = ram_properties;
799}
800
801static const TypeInfo ram_info = {
802 .name = TYPE_SUN4M_MEMORY,
803 .parent = TYPE_SYS_BUS_DEVICE,
804 .instance_size = sizeof(RamDevice),
805 .class_init = ram_class_init,
806};
807
808static void cpu_devinit(const char *cpu_model, unsigned int id,
809 uint64_t prom_addr, qemu_irq **cpu_irqs)
810{
811 CPUState *cs;
812 SPARCCPU *cpu;
813 CPUSPARCState *env;
814
815 cpu = cpu_sparc_init(cpu_model);
816 if (cpu == NULL) {
817 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
818 exit(1);
819 }
820 env = &cpu->env;
821
822 cpu_sparc_set_id(env, id);
823 if (id == 0) {
824 qemu_register_reset(main_cpu_reset, cpu);
825 } else {
826 qemu_register_reset(secondary_cpu_reset, cpu);
827 cs = CPU(cpu);
828 cs->halted = 1;
829 }
830 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
831 env->prom_addr = prom_addr;
832}
833
834static void dummy_fdc_tc(void *opaque, int irq, int level)
835{
836}
837
838static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
839 MachineState *machine)
840{
841 DeviceState *slavio_intctl;
842 const char *cpu_model = machine->cpu_model;
843 unsigned int i;
844 void *iommu, *espdma, *ledma, *nvram;
845 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
846 espdma_irq, ledma_irq;
847 qemu_irq esp_reset, dma_enable;
848 qemu_irq fdc_tc;
849 unsigned long kernel_size;
850 DriveInfo *fd[MAX_FD];
851 FWCfgState *fw_cfg;
852 unsigned int num_vsimms;
853
854
855 if (!cpu_model)
856 cpu_model = hwdef->default_cpu_model;
857
858 for(i = 0; i < smp_cpus; i++) {
859 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
860 }
861
862 for (i = smp_cpus; i < MAX_CPUS; i++)
863 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
864
865
866
867 ram_init(0, machine->ram_size, hwdef->max_mem);
868
869 if (!hwdef->ecc_base) {
870 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
871 }
872
873 prom_init(hwdef->slavio_base, bios_name);
874
875 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
876 hwdef->intctl_base + 0x10000ULL,
877 cpu_irqs);
878
879 for (i = 0; i < 32; i++) {
880 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
881 }
882 for (i = 0; i < MAX_CPUS; i++) {
883 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
884 }
885
886 if (hwdef->idreg_base) {
887 idreg_init(hwdef->idreg_base);
888 }
889
890 if (hwdef->afx_base) {
891 afx_init(hwdef->afx_base);
892 }
893
894 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
895 slavio_irq[30]);
896
897 if (hwdef->iommu_pad_base) {
898
899
900
901
902 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
903 }
904
905 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
906 iommu, &espdma_irq, 0);
907
908 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
909 slavio_irq[16], iommu, &ledma_irq, 1);
910
911 if (graphic_depth != 8 && graphic_depth != 24) {
912 error_report("Unsupported depth: %d", graphic_depth);
913 exit (1);
914 }
915 num_vsimms = 0;
916 if (num_vsimms == 0) {
917 if (vga_interface_type == VGA_CG3) {
918 if (graphic_depth != 8) {
919 error_report("Unsupported depth: %d", graphic_depth);
920 exit(1);
921 }
922
923 if (!(graphic_width == 1024 && graphic_height == 768) &&
924 !(graphic_width == 1152 && graphic_height == 900)) {
925 error_report("Unsupported resolution: %d x %d", graphic_width,
926 graphic_height);
927 exit(1);
928 }
929
930
931 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
932 graphic_width, graphic_height, graphic_depth);
933 } else {
934
935 if (graphic_depth != 8 && graphic_depth != 24) {
936 error_report("Unsupported depth: %d", graphic_depth);
937 exit(1);
938 }
939
940 if (!(graphic_width == 1024 && graphic_height == 768)) {
941 error_report("Unsupported resolution: %d x %d",
942 graphic_width, graphic_height);
943 exit(1);
944 }
945
946 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
947 graphic_width, graphic_height, graphic_depth);
948 }
949 }
950
951 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
952
953 if (hwdef->vsimm[i].reg_base) {
954 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
955 }
956 }
957
958 if (hwdef->sx_base) {
959 empty_slot_init(hwdef->sx_base, 0x2000);
960 }
961
962 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
963
964 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
965
966 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
967
968 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
969 !machine->enable_graphics, ESCC_CLOCK, 1);
970
971
972 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
973 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
974
975 if (hwdef->apc_base) {
976 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
977 }
978
979 if (hwdef->fd_base) {
980
981 memset(fd, 0, sizeof(fd));
982 fd[0] = drive_get(IF_FLOPPY, 0, 0);
983 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
984 &fdc_tc);
985 } else {
986 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
987 }
988
989 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
990 slavio_irq[30], fdc_tc);
991
992 if (drive_get_max_bus(IF_SCSI) > 0) {
993 fprintf(stderr, "qemu: too many SCSI bus\n");
994 exit(1);
995 }
996
997 esp_init(hwdef->esp_base, 2,
998 espdma_memory_read, espdma_memory_write,
999 espdma, espdma_irq, &esp_reset, &dma_enable);
1000
1001 qdev_connect_gpio_out(espdma, 0, esp_reset);
1002 qdev_connect_gpio_out(espdma, 1, dma_enable);
1003
1004 if (hwdef->cs_base) {
1005 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1006 slavio_irq[5]);
1007 }
1008
1009 if (hwdef->dbri_base) {
1010
1011
1012 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1013
1014 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1015 }
1016
1017 if (hwdef->bpp_base) {
1018
1019 empty_slot_init(hwdef->bpp_base, 0x20);
1020 }
1021
1022 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1023 machine->initrd_filename,
1024 machine->ram_size);
1025
1026 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1027 machine->boot_order, machine->ram_size, kernel_size,
1028 graphic_width, graphic_height, graphic_depth,
1029 hwdef->nvram_machine_id, "Sun4m");
1030
1031 if (hwdef->ecc_base)
1032 ecc_init(hwdef->ecc_base, slavio_irq[28],
1033 hwdef->ecc_version);
1034
1035 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1036 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1037 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1038 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1039 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1040 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1041 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1042 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1043 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1044 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1045 if (machine->kernel_cmdline) {
1046 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1047 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1048 machine->kernel_cmdline);
1049 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1050 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1051 strlen(machine->kernel_cmdline) + 1);
1052 } else {
1053 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1054 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1055 }
1056 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1057 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0);
1058 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1059 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1060}
1061
1062enum {
1063 ss5_id = 32,
1064 vger_id,
1065 lx_id,
1066 ss4_id,
1067 scls_id,
1068 sbook_id,
1069 ss10_id = 64,
1070 ss20_id,
1071 ss600mp_id,
1072};
1073
1074static const struct sun4m_hwdef sun4m_hwdefs[] = {
1075
1076 {
1077 .iommu_base = 0x10000000,
1078 .iommu_pad_base = 0x10004000,
1079 .iommu_pad_len = 0x0fffb000,
1080 .tcx_base = 0x50000000,
1081 .cs_base = 0x6c000000,
1082 .slavio_base = 0x70000000,
1083 .ms_kb_base = 0x71000000,
1084 .serial_base = 0x71100000,
1085 .nvram_base = 0x71200000,
1086 .fd_base = 0x71400000,
1087 .counter_base = 0x71d00000,
1088 .intctl_base = 0x71e00000,
1089 .idreg_base = 0x78000000,
1090 .dma_base = 0x78400000,
1091 .esp_base = 0x78800000,
1092 .le_base = 0x78c00000,
1093 .apc_base = 0x6a000000,
1094 .afx_base = 0x6e000000,
1095 .aux1_base = 0x71900000,
1096 .aux2_base = 0x71910000,
1097 .nvram_machine_id = 0x80,
1098 .machine_id = ss5_id,
1099 .iommu_version = 0x05000000,
1100 .max_mem = 0x10000000,
1101 .default_cpu_model = "Fujitsu MB86904",
1102 },
1103
1104 {
1105 .iommu_base = 0xfe0000000ULL,
1106 .tcx_base = 0xe20000000ULL,
1107 .slavio_base = 0xff0000000ULL,
1108 .ms_kb_base = 0xff1000000ULL,
1109 .serial_base = 0xff1100000ULL,
1110 .nvram_base = 0xff1200000ULL,
1111 .fd_base = 0xff1700000ULL,
1112 .counter_base = 0xff1300000ULL,
1113 .intctl_base = 0xff1400000ULL,
1114 .idreg_base = 0xef0000000ULL,
1115 .dma_base = 0xef0400000ULL,
1116 .esp_base = 0xef0800000ULL,
1117 .le_base = 0xef0c00000ULL,
1118 .apc_base = 0xefa000000ULL,
1119 .aux1_base = 0xff1800000ULL,
1120 .aux2_base = 0xff1a01000ULL,
1121 .ecc_base = 0xf00000000ULL,
1122 .ecc_version = 0x10000000,
1123 .nvram_machine_id = 0x72,
1124 .machine_id = ss10_id,
1125 .iommu_version = 0x03000000,
1126 .max_mem = 0xf00000000ULL,
1127 .default_cpu_model = "TI SuperSparc II",
1128 },
1129
1130 {
1131 .iommu_base = 0xfe0000000ULL,
1132 .tcx_base = 0xe20000000ULL,
1133 .slavio_base = 0xff0000000ULL,
1134 .ms_kb_base = 0xff1000000ULL,
1135 .serial_base = 0xff1100000ULL,
1136 .nvram_base = 0xff1200000ULL,
1137 .counter_base = 0xff1300000ULL,
1138 .intctl_base = 0xff1400000ULL,
1139 .dma_base = 0xef0081000ULL,
1140 .esp_base = 0xef0080000ULL,
1141 .le_base = 0xef0060000ULL,
1142 .apc_base = 0xefa000000ULL,
1143 .aux1_base = 0xff1800000ULL,
1144 .aux2_base = 0xff1a01000ULL,
1145 .ecc_base = 0xf00000000ULL,
1146 .ecc_version = 0x00000000,
1147 .nvram_machine_id = 0x71,
1148 .machine_id = ss600mp_id,
1149 .iommu_version = 0x01000000,
1150 .max_mem = 0xf00000000ULL,
1151 .default_cpu_model = "TI SuperSparc II",
1152 },
1153
1154 {
1155 .iommu_base = 0xfe0000000ULL,
1156 .tcx_base = 0xe20000000ULL,
1157 .slavio_base = 0xff0000000ULL,
1158 .ms_kb_base = 0xff1000000ULL,
1159 .serial_base = 0xff1100000ULL,
1160 .nvram_base = 0xff1200000ULL,
1161 .fd_base = 0xff1700000ULL,
1162 .counter_base = 0xff1300000ULL,
1163 .intctl_base = 0xff1400000ULL,
1164 .idreg_base = 0xef0000000ULL,
1165 .dma_base = 0xef0400000ULL,
1166 .esp_base = 0xef0800000ULL,
1167 .le_base = 0xef0c00000ULL,
1168 .bpp_base = 0xef4800000ULL,
1169 .apc_base = 0xefa000000ULL,
1170 .aux1_base = 0xff1800000ULL,
1171 .aux2_base = 0xff1a01000ULL,
1172 .dbri_base = 0xee0000000ULL,
1173 .sx_base = 0xf80000000ULL,
1174 .vsimm = {
1175 {
1176 .reg_base = 0x9c000000ULL,
1177 .vram_base = 0xfc000000ULL
1178 }, {
1179 .reg_base = 0x90000000ULL,
1180 .vram_base = 0xf0000000ULL
1181 }, {
1182 .reg_base = 0x94000000ULL
1183 }, {
1184 .reg_base = 0x98000000ULL
1185 }
1186 },
1187 .ecc_base = 0xf00000000ULL,
1188 .ecc_version = 0x20000000,
1189 .nvram_machine_id = 0x72,
1190 .machine_id = ss20_id,
1191 .iommu_version = 0x13000000,
1192 .max_mem = 0xf00000000ULL,
1193 .default_cpu_model = "TI SuperSparc II",
1194 },
1195
1196 {
1197 .iommu_base = 0x10000000,
1198 .tcx_base = 0x50000000,
1199 .slavio_base = 0x70000000,
1200 .ms_kb_base = 0x71000000,
1201 .serial_base = 0x71100000,
1202 .nvram_base = 0x71200000,
1203 .fd_base = 0x71400000,
1204 .counter_base = 0x71d00000,
1205 .intctl_base = 0x71e00000,
1206 .idreg_base = 0x78000000,
1207 .dma_base = 0x78400000,
1208 .esp_base = 0x78800000,
1209 .le_base = 0x78c00000,
1210 .apc_base = 0x71300000,
1211 .aux1_base = 0x71900000,
1212 .aux2_base = 0x71910000,
1213 .nvram_machine_id = 0x80,
1214 .machine_id = vger_id,
1215 .iommu_version = 0x05000000,
1216 .max_mem = 0x10000000,
1217 .default_cpu_model = "Fujitsu MB86904",
1218 },
1219
1220 {
1221 .iommu_base = 0x10000000,
1222 .iommu_pad_base = 0x10004000,
1223 .iommu_pad_len = 0x0fffb000,
1224 .tcx_base = 0x50000000,
1225 .slavio_base = 0x70000000,
1226 .ms_kb_base = 0x71000000,
1227 .serial_base = 0x71100000,
1228 .nvram_base = 0x71200000,
1229 .fd_base = 0x71400000,
1230 .counter_base = 0x71d00000,
1231 .intctl_base = 0x71e00000,
1232 .idreg_base = 0x78000000,
1233 .dma_base = 0x78400000,
1234 .esp_base = 0x78800000,
1235 .le_base = 0x78c00000,
1236 .aux1_base = 0x71900000,
1237 .aux2_base = 0x71910000,
1238 .nvram_machine_id = 0x80,
1239 .machine_id = lx_id,
1240 .iommu_version = 0x04000000,
1241 .max_mem = 0x10000000,
1242 .default_cpu_model = "TI MicroSparc I",
1243 },
1244
1245 {
1246 .iommu_base = 0x10000000,
1247 .tcx_base = 0x50000000,
1248 .cs_base = 0x6c000000,
1249 .slavio_base = 0x70000000,
1250 .ms_kb_base = 0x71000000,
1251 .serial_base = 0x71100000,
1252 .nvram_base = 0x71200000,
1253 .fd_base = 0x71400000,
1254 .counter_base = 0x71d00000,
1255 .intctl_base = 0x71e00000,
1256 .idreg_base = 0x78000000,
1257 .dma_base = 0x78400000,
1258 .esp_base = 0x78800000,
1259 .le_base = 0x78c00000,
1260 .apc_base = 0x6a000000,
1261 .aux1_base = 0x71900000,
1262 .aux2_base = 0x71910000,
1263 .nvram_machine_id = 0x80,
1264 .machine_id = ss4_id,
1265 .iommu_version = 0x05000000,
1266 .max_mem = 0x10000000,
1267 .default_cpu_model = "Fujitsu MB86904",
1268 },
1269
1270 {
1271 .iommu_base = 0x10000000,
1272 .tcx_base = 0x50000000,
1273 .slavio_base = 0x70000000,
1274 .ms_kb_base = 0x71000000,
1275 .serial_base = 0x71100000,
1276 .nvram_base = 0x71200000,
1277 .fd_base = 0x71400000,
1278 .counter_base = 0x71d00000,
1279 .intctl_base = 0x71e00000,
1280 .idreg_base = 0x78000000,
1281 .dma_base = 0x78400000,
1282 .esp_base = 0x78800000,
1283 .le_base = 0x78c00000,
1284 .apc_base = 0x6a000000,
1285 .aux1_base = 0x71900000,
1286 .aux2_base = 0x71910000,
1287 .nvram_machine_id = 0x80,
1288 .machine_id = scls_id,
1289 .iommu_version = 0x05000000,
1290 .max_mem = 0x10000000,
1291 .default_cpu_model = "TI MicroSparc I",
1292 },
1293
1294 {
1295 .iommu_base = 0x10000000,
1296 .tcx_base = 0x50000000,
1297 .slavio_base = 0x70000000,
1298 .ms_kb_base = 0x71000000,
1299 .serial_base = 0x71100000,
1300 .nvram_base = 0x71200000,
1301 .fd_base = 0x71400000,
1302 .counter_base = 0x71d00000,
1303 .intctl_base = 0x71e00000,
1304 .idreg_base = 0x78000000,
1305 .dma_base = 0x78400000,
1306 .esp_base = 0x78800000,
1307 .le_base = 0x78c00000,
1308 .apc_base = 0x6a000000,
1309 .aux1_base = 0x71900000,
1310 .aux2_base = 0x71910000,
1311 .nvram_machine_id = 0x80,
1312 .machine_id = sbook_id,
1313 .iommu_version = 0x05000000,
1314 .max_mem = 0x10000000,
1315 .default_cpu_model = "TI MicroSparc I",
1316 },
1317};
1318
1319
1320static void ss5_init(MachineState *machine)
1321{
1322 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1323}
1324
1325
1326static void ss10_init(MachineState *machine)
1327{
1328 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1329}
1330
1331
1332static void ss600mp_init(MachineState *machine)
1333{
1334 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1335}
1336
1337
1338static void ss20_init(MachineState *machine)
1339{
1340 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1341}
1342
1343
1344static void vger_init(MachineState *machine)
1345{
1346 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1347}
1348
1349
1350static void ss_lx_init(MachineState *machine)
1351{
1352 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1353}
1354
1355
1356static void ss4_init(MachineState *machine)
1357{
1358 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1359}
1360
1361
1362static void scls_init(MachineState *machine)
1363{
1364 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1365}
1366
1367
1368static void sbook_init(MachineState *machine)
1369{
1370 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1371}
1372
1373static void ss5_class_init(ObjectClass *oc, void *data)
1374{
1375 MachineClass *mc = MACHINE_CLASS(oc);
1376
1377 mc->desc = "Sun4m platform, SPARCstation 5";
1378 mc->init = ss5_init;
1379 mc->block_default_type = IF_SCSI;
1380 mc->is_default = 1;
1381 mc->default_boot_order = "c";
1382}
1383
1384static const TypeInfo ss5_type = {
1385 .name = MACHINE_TYPE_NAME("SS-5"),
1386 .parent = TYPE_MACHINE,
1387 .class_init = ss5_class_init,
1388};
1389
1390static void ss10_class_init(ObjectClass *oc, void *data)
1391{
1392 MachineClass *mc = MACHINE_CLASS(oc);
1393
1394 mc->desc = "Sun4m platform, SPARCstation 10";
1395 mc->init = ss10_init;
1396 mc->block_default_type = IF_SCSI;
1397 mc->max_cpus = 4;
1398 mc->default_boot_order = "c";
1399}
1400
1401static const TypeInfo ss10_type = {
1402 .name = MACHINE_TYPE_NAME("SS-10"),
1403 .parent = TYPE_MACHINE,
1404 .class_init = ss10_class_init,
1405};
1406
1407static void ss600mp_class_init(ObjectClass *oc, void *data)
1408{
1409 MachineClass *mc = MACHINE_CLASS(oc);
1410
1411 mc->desc = "Sun4m platform, SPARCserver 600MP";
1412 mc->init = ss600mp_init;
1413 mc->block_default_type = IF_SCSI;
1414 mc->max_cpus = 4;
1415 mc->default_boot_order = "c";
1416}
1417
1418static const TypeInfo ss600mp_type = {
1419 .name = MACHINE_TYPE_NAME("SS-600MP"),
1420 .parent = TYPE_MACHINE,
1421 .class_init = ss600mp_class_init,
1422};
1423
1424static void ss20_class_init(ObjectClass *oc, void *data)
1425{
1426 MachineClass *mc = MACHINE_CLASS(oc);
1427
1428 mc->desc = "Sun4m platform, SPARCstation 20";
1429 mc->init = ss20_init;
1430 mc->block_default_type = IF_SCSI;
1431 mc->max_cpus = 4;
1432 mc->default_boot_order = "c";
1433}
1434
1435static const TypeInfo ss20_type = {
1436 .name = MACHINE_TYPE_NAME("SS-20"),
1437 .parent = TYPE_MACHINE,
1438 .class_init = ss20_class_init,
1439};
1440
1441static void voyager_class_init(ObjectClass *oc, void *data)
1442{
1443 MachineClass *mc = MACHINE_CLASS(oc);
1444
1445 mc->desc = "Sun4m platform, SPARCstation Voyager";
1446 mc->init = vger_init;
1447 mc->block_default_type = IF_SCSI;
1448 mc->default_boot_order = "c";
1449}
1450
1451static const TypeInfo voyager_type = {
1452 .name = MACHINE_TYPE_NAME("Voyager"),
1453 .parent = TYPE_MACHINE,
1454 .class_init = voyager_class_init,
1455};
1456
1457static void ss_lx_class_init(ObjectClass *oc, void *data)
1458{
1459 MachineClass *mc = MACHINE_CLASS(oc);
1460
1461 mc->desc = "Sun4m platform, SPARCstation LX";
1462 mc->init = ss_lx_init;
1463 mc->block_default_type = IF_SCSI;
1464 mc->default_boot_order = "c";
1465}
1466
1467static const TypeInfo ss_lx_type = {
1468 .name = MACHINE_TYPE_NAME("LX"),
1469 .parent = TYPE_MACHINE,
1470 .class_init = ss_lx_class_init,
1471};
1472
1473static void ss4_class_init(ObjectClass *oc, void *data)
1474{
1475 MachineClass *mc = MACHINE_CLASS(oc);
1476
1477 mc->desc = "Sun4m platform, SPARCstation 4";
1478 mc->init = ss4_init;
1479 mc->block_default_type = IF_SCSI;
1480 mc->default_boot_order = "c";
1481}
1482
1483static const TypeInfo ss4_type = {
1484 .name = MACHINE_TYPE_NAME("SS-4"),
1485 .parent = TYPE_MACHINE,
1486 .class_init = ss4_class_init,
1487};
1488
1489static void scls_class_init(ObjectClass *oc, void *data)
1490{
1491 MachineClass *mc = MACHINE_CLASS(oc);
1492
1493 mc->desc = "Sun4m platform, SPARCClassic";
1494 mc->init = scls_init;
1495 mc->block_default_type = IF_SCSI;
1496 mc->default_boot_order = "c";
1497}
1498
1499static const TypeInfo scls_type = {
1500 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1501 .parent = TYPE_MACHINE,
1502 .class_init = scls_class_init,
1503};
1504
1505static void sbook_class_init(ObjectClass *oc, void *data)
1506{
1507 MachineClass *mc = MACHINE_CLASS(oc);
1508
1509 mc->desc = "Sun4m platform, SPARCbook";
1510 mc->init = sbook_init;
1511 mc->block_default_type = IF_SCSI;
1512 mc->default_boot_order = "c";
1513}
1514
1515static const TypeInfo sbook_type = {
1516 .name = MACHINE_TYPE_NAME("SPARCbook"),
1517 .parent = TYPE_MACHINE,
1518 .class_init = sbook_class_init,
1519};
1520
1521static void sun4m_register_types(void)
1522{
1523 type_register_static(&idreg_info);
1524 type_register_static(&afx_info);
1525 type_register_static(&prom_info);
1526 type_register_static(&ram_info);
1527
1528 type_register_static(&ss5_type);
1529 type_register_static(&ss10_type);
1530 type_register_static(&ss600mp_type);
1531 type_register_static(&ss20_type);
1532 type_register_static(&voyager_type);
1533 type_register_static(&ss_lx_type);
1534 type_register_static(&ss4_type);
1535 type_register_static(&scls_type);
1536 type_register_static(&sbook_type);
1537}
1538
1539type_init(sun4m_register_types)
1540
