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28#include "qemu/osdep.h"
29#include "cpu.h"
30#include "hw/hw.h"
31#include "qemu/log.h"
32#include "qemu/timer.h"
33
34void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d)
35{
36 uint32_t old_ccount = env->sregs[CCOUNT] + 1;
37
38 env->sregs[CCOUNT] += d;
39
40 if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
41 int i;
42 for (i = 0; i < env->config->nccompare; ++i) {
43 if (env->sregs[CCOMPARE + i] - old_ccount < d) {
44 xtensa_timer_irq(env, i, 1);
45 }
46 }
47 }
48}
49
50void check_interrupts(CPUXtensaState *env)
51{
52 CPUState *cs = CPU(xtensa_env_get_cpu(env));
53 int minlevel = xtensa_get_cintlevel(env);
54 uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
55 int level;
56
57
58
59
60 if (cs->halted) {
61 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
62
63 xtensa_advance_ccount(env,
64 muldiv64(now - env->halt_clock,
65 env->config->clock_freq_khz, 1000000));
66 env->halt_clock = now;
67 }
68 for (level = env->config->nlevel; level > minlevel; --level) {
69 if (env->config->level_mask[level] & int_set_enabled) {
70 env->pending_irq_level = level;
71 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
72 qemu_log_mask(CPU_LOG_INT,
73 "%s level = %d, cintlevel = %d, "
74 "pc = %08x, a0 = %08x, ps = %08x, "
75 "intset = %08x, intenable = %08x, "
76 "ccount = %08x\n",
77 __func__, level, xtensa_get_cintlevel(env),
78 env->pc, env->regs[0], env->sregs[PS],
79 env->sregs[INTSET], env->sregs[INTENABLE],
80 env->sregs[CCOUNT]);
81 return;
82 }
83 }
84 env->pending_irq_level = 0;
85 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
86}
87
88static void xtensa_set_irq(void *opaque, int irq, int active)
89{
90 CPUXtensaState *env = opaque;
91
92 if (irq >= env->config->ninterrupt) {
93 qemu_log("%s: bad IRQ %d\n", __func__, irq);
94 } else {
95 uint32_t irq_bit = 1 << irq;
96
97 if (active) {
98 env->sregs[INTSET] |= irq_bit;
99 } else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) {
100 env->sregs[INTSET] &= ~irq_bit;
101 }
102
103 check_interrupts(env);
104 }
105}
106
107void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active)
108{
109 qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active);
110}
111
112void xtensa_rearm_ccompare_timer(CPUXtensaState *env)
113{
114 int i;
115 uint32_t wake_ccount = env->sregs[CCOUNT] - 1;
116
117 for (i = 0; i < env->config->nccompare; ++i) {
118 if (env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] <
119 wake_ccount - env->sregs[CCOUNT]) {
120 wake_ccount = env->sregs[CCOMPARE + i];
121 }
122 }
123 env->wake_ccount = wake_ccount;
124 timer_mod(env->ccompare_timer, env->halt_clock +
125 (uint64_t)(wake_ccount - env->sregs[CCOUNT]) *
126 1000000 / env->config->clock_freq_khz);
127}
128
129static void xtensa_ccompare_cb(void *opaque)
130{
131 XtensaCPU *cpu = opaque;
132 CPUXtensaState *env = &cpu->env;
133 CPUState *cs = CPU(cpu);
134
135 if (cs->halted) {
136 env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
137 xtensa_advance_ccount(env, env->wake_ccount - env->sregs[CCOUNT]);
138 if (!cpu_has_work(cs)) {
139 env->sregs[CCOUNT] = env->wake_ccount + 1;
140 xtensa_rearm_ccompare_timer(env);
141 }
142 }
143}
144
145void xtensa_irq_init(CPUXtensaState *env)
146{
147 XtensaCPU *cpu = xtensa_env_get_cpu(env);
148
149 env->irq_inputs = (void **)qemu_allocate_irqs(
150 xtensa_set_irq, env, env->config->ninterrupt);
151 if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT) &&
152 env->config->nccompare > 0) {
153 env->ccompare_timer =
154 timer_new_ns(QEMU_CLOCK_VIRTUAL, &xtensa_ccompare_cb, cpu);
155 }
156}
157
158void *xtensa_get_extint(CPUXtensaState *env, unsigned extint)
159{
160 if (extint < env->config->nextint) {
161 unsigned irq = env->config->extint[extint];
162 return env->irq_inputs[irq];
163 } else {
164 qemu_log("%s: trying to acquire invalid external interrupt %d\n",
165 __func__, extint);
166 return NULL;
167 }
168}
169