LXR qemu/include/hw/intc/arm_gic

   1/*
   2 * ARM GIC support
   3 *
   4 * Copyright (c) 2012 Linaro Limited
   5 * Written by Peter Maydell
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation, either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along
  18 * with this program; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#ifndef HW_ARM_GIC_COMMON_H
  22#define HW_ARM_GIC_COMMON_H
  23
  24#include "hw/sysbus.h"
  25
  26/* Maximum number of possible interrupts, determined by the GIC architecture */
  27#define GIC_MAXIRQ 1020
  28/* First 32 are private to each CPU (SGIs and PPIs). */
  29#define GIC_INTERNAL 32
  30#define GIC_NR_SGIS 16
  31/* Maximum number of possible CPU interfaces, determined by GIC architecture */
  32#define GIC_NCPU 8
  33
  34#define MAX_NR_GROUP_PRIO 128
  35#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
  36
  37#define GIC_MIN_BPR 0
  38#define GIC_MIN_ABPR (GIC_MIN_BPR + 1)
  39
  40typedef struct gic_irq_state {
  41    /* The enable bits are only banked for per-cpu interrupts.  */
  42    uint8_t enabled;
  43    uint8_t pending;
  44    uint8_t active;
  45    uint8_t level;
  46    bool model; /* 0 = N:N, 1 = 1:N */
  47    bool edge_trigger; /* true: edge-triggered, false: level-triggered  */
  48    uint8_t group;
  49} gic_irq_state;
  50
  51typedef struct GICState {
  52    /*< private >*/
  53    SysBusDevice parent_obj;
  54    /*< public >*/
  55
  56    qemu_irq parent_irq[GIC_NCPU];
  57    qemu_irq parent_fiq[GIC_NCPU];
  58    /* GICD_CTLR; for a GIC with the security extensions the NS banked version
  59     * of this register is just an alias of bit 1 of the S banked version.
  60     */
  61    uint32_t ctlr;
  62    /* GICC_CTLR; again, the NS banked version is just aliases of bits of
  63     * the S banked register, so our state only needs to store the S version.
  64     */
  65    uint32_t cpu_ctlr[GIC_NCPU];
  66
  67    gic_irq_state irq_state[GIC_MAXIRQ];
  68    uint8_t irq_target[GIC_MAXIRQ];
  69    uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
  70    uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
  71    /* For each SGI on the target CPU, we store 8 bits
  72     * indicating which source CPUs have made this SGI
  73     * pending on the target CPU. These correspond to
  74     * the bytes in the GIC_SPENDSGIR* registers as
  75     * read by the target CPU.
  76     */
  77    uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
  78
  79    uint16_t priority_mask[GIC_NCPU];
  80    uint16_t running_priority[GIC_NCPU];
  81    uint16_t current_pending[GIC_NCPU];
  82
  83    /* If we present the GICv2 without security extensions to a guest,
  84     * the guest can configure the GICC_CTLR to configure group 1 binary point
  85     * in the abpr.
  86     * For a GIC with Security Extensions we use use bpr for the
  87     * secure copy and abpr as storage for the non-secure copy of the register.
  88     */
  89    uint8_t  bpr[GIC_NCPU];
  90    uint8_t  abpr[GIC_NCPU];
  91
  92    /* The APR is implementation defined, so we choose a layout identical to
  93     * the KVM ABI layout for QEMU's implementation of the gic:
  94     * If an interrupt for preemption level X is active, then
  95     *   APRn[X mod 32] == 0b1,  where n = X / 32
  96     * otherwise the bit is clear.
  97     */
  98    uint32_t apr[GIC_NR_APRS][GIC_NCPU];
  99    uint32_t nsapr[GIC_NR_APRS][GIC_NCPU];
 100
 101    uint32_t num_cpu;
 102
 103    MemoryRegion iomem; /* Distributor */
 104    /* This is just so we can have an opaque pointer which identifies
 105     * both this GIC and which CPU interface we should be accessing.
 106     */
 107    struct GICState *backref[GIC_NCPU];
 108    MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
 109    uint32_t num_irq;
 110    uint32_t revision;
 111    bool security_extn;
 112    bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? */
 113    int dev_fd; /* kvm device fd if backed by kvm vgic support */
 114    Error *migration_blocker;
 115} GICState;
 116
 117#define TYPE_ARM_GIC_COMMON "arm_gic_common"
 118#define ARM_GIC_COMMON(obj) \
 119     OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
 120#define ARM_GIC_COMMON_CLASS(klass) \
 121     OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
 122#define ARM_GIC_COMMON_GET_CLASS(obj) \
 123     OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
 124
 125typedef struct ARMGICCommonClass {
 126    /*< private >*/
 127    SysBusDeviceClass parent_class;
 128    /*< public >*/
 129
 130    void (*pre_save)(GICState *s);
 131    void (*post_load)(GICState *s);
 132} ARMGICCommonClass;
 133
 134void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
 135                            const MemoryRegionOps *ops);
 136
 137#endif
 138