1#ifndef HW_SPAPR_H
2#define HW_SPAPR_H
3
4#include "sysemu/dma.h"
5#include "hw/boards.h"
6#include "hw/ppc/xics.h"
7#include "hw/ppc/spapr_drc.h"
8#include "hw/mem/pc-dimm.h"
9#include "hw/ppc/spapr_ovec.h"
10
11struct VIOsPAPRBus;
12struct sPAPRPHBState;
13struct sPAPRNVRAM;
14typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState;
15typedef struct sPAPREventLogEntry sPAPREventLogEntry;
16typedef struct sPAPREventSource sPAPREventSource;
17
18#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
19#define SPAPR_ENTRY_POINT 0x100
20
21#define SPAPR_TIMEBASE_FREQ 512000000ULL
22
23typedef struct sPAPRMachineClass sPAPRMachineClass;
24typedef struct sPAPRMachineState sPAPRMachineState;
25
26#define TYPE_SPAPR_MACHINE "spapr-machine"
27#define SPAPR_MACHINE(obj) \
28 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
29#define SPAPR_MACHINE_GET_CLASS(obj) \
30 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
31#define SPAPR_MACHINE_CLASS(klass) \
32 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
33
34
35
36
37struct sPAPRMachineClass {
38
39 MachineClass parent_class;
40
41
42 bool dr_lmb_enabled;
43 bool use_ohci_by_default;
44 const char *tcg_default_cpu;
45 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
46 uint64_t *buid, hwaddr *pio,
47 hwaddr *mmio32, hwaddr *mmio64,
48 unsigned n_dma, uint32_t *liobns, Error **errp);
49};
50
51
52
53
54struct sPAPRMachineState {
55
56 MachineState parent_obj;
57
58 struct VIOsPAPRBus *vio_bus;
59 QLIST_HEAD(, sPAPRPHBState) phbs;
60 struct sPAPRNVRAM *nvram;
61 XICSState *xics;
62 DeviceState *rtc;
63
64 void *htab;
65 uint32_t htab_shift;
66 hwaddr rma_size;
67 int vrma_adjust;
68 ssize_t rtas_size;
69 void *rtas_blob;
70 long kernel_size;
71 bool kernel_le;
72 uint32_t initrd_base;
73 long initrd_size;
74 uint64_t rtc_offset;
75 struct PPCTimebase tb;
76 bool has_graphics;
77 sPAPROptionVector *ov5;
78 sPAPROptionVector *ov5_cas;
79 bool cas_reboot;
80
81 Notifier epow_notifier;
82 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
83 bool use_hotplug_event_source;
84 sPAPREventSource *event_sources;
85
86
87 int htab_save_index;
88 bool htab_first_pass;
89 int htab_fd;
90
91
92 QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list;
93
94
95 char *kvm_type;
96 MemoryHotplugState hotplug_memory;
97 Object **cores;
98};
99
100#define H_SUCCESS 0
101#define H_BUSY 1
102#define H_CLOSED 2
103#define H_NOT_AVAILABLE 3
104#define H_CONSTRAINED 4
105#define H_PARTIAL 5
106#define H_IN_PROGRESS 14
107#define H_PAGE_REGISTERED 15
108#define H_PARTIAL_STORE 16
109#define H_PENDING 17
110#define H_CONTINUE 18
111#define H_LONG_BUSY_START_RANGE 9900
112#define H_LONG_BUSY_ORDER_1_MSEC 9900
113
114#define H_LONG_BUSY_ORDER_10_MSEC 9901
115
116#define H_LONG_BUSY_ORDER_100_MSEC 9902
117
118#define H_LONG_BUSY_ORDER_1_SEC 9903
119
120#define H_LONG_BUSY_ORDER_10_SEC 9904
121
122#define H_LONG_BUSY_ORDER_100_SEC 9905
123
124#define H_LONG_BUSY_END_RANGE 9905
125#define H_HARDWARE -1
126#define H_FUNCTION -2
127#define H_PRIVILEGE -3
128#define H_PARAMETER -4
129#define H_BAD_MODE -5
130#define H_PTEG_FULL -6
131#define H_NOT_FOUND -7
132#define H_RESERVED_DABR -8
133#define H_NO_MEM -9
134#define H_AUTHORITY -10
135#define H_PERMISSION -11
136#define H_DROPPED -12
137#define H_SOURCE_PARM -13
138#define H_DEST_PARM -14
139#define H_REMOTE_PARM -15
140#define H_RESOURCE -16
141#define H_ADAPTER_PARM -17
142#define H_RH_PARM -18
143#define H_RCQ_PARM -19
144#define H_SCQ_PARM -20
145#define H_EQ_PARM -21
146#define H_RT_PARM -22
147#define H_ST_PARM -23
148#define H_SIGT_PARM -24
149#define H_TOKEN_PARM -25
150#define H_MLENGTH_PARM -27
151#define H_MEM_PARM -28
152#define H_MEM_ACCESS_PARM -29
153#define H_ATTR_PARM -30
154#define H_PORT_PARM -31
155#define H_MCG_PARM -32
156#define H_VL_PARM -33
157#define H_TSIZE_PARM -34
158#define H_TRACE_PARM -35
159
160#define H_MASK_PARM -37
161#define H_MCG_FULL -38
162#define H_ALIAS_EXIST -39
163#define H_P_COUNTER -40
164#define H_TABLE_FULL -41
165#define H_ALT_TABLE -42
166#define H_MR_CONDITION -43
167#define H_NOT_ENOUGH_RESOURCES -44
168#define H_R_STATE -45
169#define H_RESCINDEND -46
170#define H_P2 -55
171#define H_P3 -56
172#define H_P4 -57
173#define H_P5 -58
174#define H_P6 -59
175#define H_P7 -60
176#define H_P8 -61
177#define H_P9 -62
178#define H_UNSUPPORTED_FLAG -256
179#define H_MULTI_THREADS_ACTIVE -9005
180
181
182
183
184
185
186
187
188
189
190#define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
191 && (x <= H_LONG_BUSY_END_RANGE))
192
193
194#define H_LARGE_PAGE (1ULL<<(63-16))
195#define H_EXACT (1ULL<<(63-24))
196#define H_R_XLATE (1ULL<<(63-25))
197#define H_READ_4 (1ULL<<(63-26))
198#define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
199#define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
200#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
201#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
202#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
203#define H_AVPN (1ULL<<(63-32))
204#define H_ANDCOND (1ULL<<(63-33))
205#define H_ICACHE_INVALIDATE (1ULL<<(63-40))
206#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))
207#define H_ZERO_PAGE (1ULL<<(63-48))
208#define H_COPY_PAGE (1ULL<<(63-49))
209#define H_N (1ULL<<(63-61))
210#define H_PP1 (1ULL<<(63-62))
211#define H_PP2 (1ULL<<(63-63))
212
213
214#define H_SET_MODE_RESOURCE_SET_CIABR 1
215#define H_SET_MODE_RESOURCE_SET_DAWR 2
216#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
217#define H_SET_MODE_RESOURCE_LE 4
218
219
220#define H_SET_MODE_ENDIAN_BIG 0
221#define H_SET_MODE_ENDIAN_LITTLE 1
222
223
224#define H_VASI_INVALID 0
225#define H_VASI_ENABLED 1
226#define H_VASI_ABORTED 2
227#define H_VASI_SUSPENDING 3
228#define H_VASI_SUSPENDED 4
229#define H_VASI_RESUMED 5
230#define H_VASI_COMPLETED 6
231
232
233#define H_DABRX_HYPERVISOR (1ULL<<(63-61))
234#define H_DABRX_KERNEL (1ULL<<(63-62))
235#define H_DABRX_USER (1ULL<<(63-63))
236
237
238#define H_CB_ALIGNMENT 4096
239
240
241#define H_REMOVE 0x04
242#define H_ENTER 0x08
243#define H_READ 0x0c
244#define H_CLEAR_MOD 0x10
245#define H_CLEAR_REF 0x14
246#define H_PROTECT 0x18
247#define H_GET_TCE 0x1c
248#define H_PUT_TCE 0x20
249#define H_SET_SPRG0 0x24
250#define H_SET_DABR 0x28
251#define H_PAGE_INIT 0x2c
252#define H_SET_ASR 0x30
253#define H_ASR_ON 0x34
254#define H_ASR_OFF 0x38
255#define H_LOGICAL_CI_LOAD 0x3c
256#define H_LOGICAL_CI_STORE 0x40
257#define H_LOGICAL_CACHE_LOAD 0x44
258#define H_LOGICAL_CACHE_STORE 0x48
259#define H_LOGICAL_ICBI 0x4c
260#define H_LOGICAL_DCBF 0x50
261#define H_GET_TERM_CHAR 0x54
262#define H_PUT_TERM_CHAR 0x58
263#define H_REAL_TO_LOGICAL 0x5c
264#define H_HYPERVISOR_DATA 0x60
265#define H_EOI 0x64
266#define H_CPPR 0x68
267#define H_IPI 0x6c
268#define H_IPOLL 0x70
269#define H_XIRR 0x74
270#define H_PERFMON 0x7c
271#define H_MIGRATE_DMA 0x78
272#define H_REGISTER_VPA 0xDC
273#define H_CEDE 0xE0
274#define H_CONFER 0xE4
275#define H_PROD 0xE8
276#define H_GET_PPP 0xEC
277#define H_SET_PPP 0xF0
278#define H_PURR 0xF4
279#define H_PIC 0xF8
280#define H_REG_CRQ 0xFC
281#define H_FREE_CRQ 0x100
282#define H_VIO_SIGNAL 0x104
283#define H_SEND_CRQ 0x108
284#define H_COPY_RDMA 0x110
285#define H_REGISTER_LOGICAL_LAN 0x114
286#define H_FREE_LOGICAL_LAN 0x118
287#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
288#define H_SEND_LOGICAL_LAN 0x120
289#define H_BULK_REMOVE 0x124
290#define H_MULTICAST_CTRL 0x130
291#define H_SET_XDABR 0x134
292#define H_STUFF_TCE 0x138
293#define H_PUT_TCE_INDIRECT 0x13C
294#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
295#define H_VTERM_PARTNER_INFO 0x150
296#define H_REGISTER_VTERM 0x154
297#define H_FREE_VTERM 0x158
298#define H_RESET_EVENTS 0x15C
299#define H_ALLOC_RESOURCE 0x160
300#define H_FREE_RESOURCE 0x164
301#define H_MODIFY_QP 0x168
302#define H_QUERY_QP 0x16C
303#define H_REREGISTER_PMR 0x170
304#define H_REGISTER_SMR 0x174
305#define H_QUERY_MR 0x178
306#define H_QUERY_MW 0x17C
307#define H_QUERY_HCA 0x180
308#define H_QUERY_PORT 0x184
309#define H_MODIFY_PORT 0x188
310#define H_DEFINE_AQP1 0x18C
311#define H_GET_TRACE_BUFFER 0x190
312#define H_DEFINE_AQP0 0x194
313#define H_RESIZE_MR 0x198
314#define H_ATTACH_MCQP 0x19C
315#define H_DETACH_MCQP 0x1A0
316#define H_CREATE_RPT 0x1A4
317#define H_REMOVE_RPT 0x1A8
318#define H_REGISTER_RPAGES 0x1AC
319#define H_DISABLE_AND_GETC 0x1B0
320#define H_ERROR_DATA 0x1B4
321#define H_GET_HCA_INFO 0x1B8
322#define H_GET_PERF_COUNT 0x1BC
323#define H_MANAGE_TRACE 0x1C0
324#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
325#define H_QUERY_INT_STATE 0x1E4
326#define H_POLL_PENDING 0x1D8
327#define H_ILLAN_ATTRIBUTES 0x244
328#define H_MODIFY_HEA_QP 0x250
329#define H_QUERY_HEA_QP 0x254
330#define H_QUERY_HEA 0x258
331#define H_QUERY_HEA_PORT 0x25C
332#define H_MODIFY_HEA_PORT 0x260
333#define H_REG_BCMC 0x264
334#define H_DEREG_BCMC 0x268
335#define H_REGISTER_HEA_RPAGES 0x26C
336#define H_DISABLE_AND_GET_HEA 0x270
337#define H_GET_HEA_INFO 0x274
338#define H_ALLOC_HEA_RESOURCE 0x278
339#define H_ADD_CONN 0x284
340#define H_DEL_CONN 0x288
341#define H_JOIN 0x298
342#define H_VASI_STATE 0x2A4
343#define H_ENABLE_CRQ 0x2B0
344#define H_GET_EM_PARMS 0x2B8
345#define H_SET_MPP 0x2D0
346#define H_GET_MPP 0x2D4
347#define H_XIRR_X 0x2FC
348#define H_RANDOM 0x300
349#define H_SET_MODE 0x31C
350#define MAX_HCALL_OPCODE H_SET_MODE
351
352
353
354
355
356
357
358
359
360#define KVMPPC_HCALL_BASE 0xf000
361#define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
362#define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
363
364#define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
365#define KVMPPC_HCALL_MAX KVMPPC_H_CAS
366
367typedef struct sPAPRDeviceTreeUpdateHeader {
368 uint32_t version_id;
369} sPAPRDeviceTreeUpdateHeader;
370
371#define hcall_dprintf(fmt, ...) \
372 do { \
373 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
374 } while (0)
375
376typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
377 target_ulong opcode,
378 target_ulong *args);
379
380void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
381target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
382 target_ulong *args);
383
384
385#define RTAS_EEH_DISABLE 0
386#define RTAS_EEH_ENABLE 1
387#define RTAS_EEH_THAW_IO 2
388#define RTAS_EEH_THAW_DMA 3
389
390
391#define RTAS_GET_PE_ADDR 0
392#define RTAS_GET_PE_MODE 1
393#define RTAS_PE_MODE_NONE 0
394#define RTAS_PE_MODE_NOT_SHARED 1
395#define RTAS_PE_MODE_SHARED 2
396
397
398#define RTAS_EEH_PE_STATE_NORMAL 0
399#define RTAS_EEH_PE_STATE_RESET 1
400#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
401#define RTAS_EEH_PE_STATE_STOPPED_DMA 4
402#define RTAS_EEH_PE_STATE_UNAVAIL 5
403#define RTAS_EEH_NOT_SUPPORT 0
404#define RTAS_EEH_SUPPORT 1
405#define RTAS_EEH_PE_UNAVAIL_INFO 1000
406#define RTAS_EEH_PE_RECOVER_INFO 0
407
408
409#define RTAS_SLOT_RESET_DEACTIVATE 0
410#define RTAS_SLOT_RESET_HOT 1
411#define RTAS_SLOT_RESET_FUNDAMENTAL 3
412
413
414#define RTAS_SLOT_TEMP_ERR_LOG 1
415#define RTAS_SLOT_PERM_ERR_LOG 2
416
417
418#define RTAS_OUT_SUCCESS 0
419#define RTAS_OUT_NO_ERRORS_FOUND 1
420#define RTAS_OUT_HW_ERROR -1
421#define RTAS_OUT_BUSY -2
422#define RTAS_OUT_PARAM_ERROR -3
423#define RTAS_OUT_NOT_SUPPORTED -3
424#define RTAS_OUT_NO_SUCH_INDICATOR -3
425#define RTAS_OUT_NOT_AUTHORIZED -9002
426#define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
427
428
429#define RTAS_DDW_PGSIZE_4K 0x01
430#define RTAS_DDW_PGSIZE_64K 0x02
431#define RTAS_DDW_PGSIZE_16M 0x04
432#define RTAS_DDW_PGSIZE_32M 0x08
433#define RTAS_DDW_PGSIZE_64M 0x10
434#define RTAS_DDW_PGSIZE_128M 0x20
435#define RTAS_DDW_PGSIZE_256M 0x40
436#define RTAS_DDW_PGSIZE_16G 0x80
437
438
439#define RTAS_TOKEN_BASE 0x2000
440
441#define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
442#define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
443#define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
444#define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
445#define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
446#define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
447#define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
448#define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
449#define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
450#define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
451#define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
452#define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
453#define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
454#define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
455#define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
456#define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
457#define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
458#define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
459#define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
460#define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
461#define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
462#define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
463#define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
464#define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
465#define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
466#define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
467#define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
468#define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
469#define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
470#define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
471#define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
472#define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
473#define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
474#define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
475#define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
476#define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
477#define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
478#define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
479#define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
480#define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
481#define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
482#define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
483
484#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A)
485
486
487#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
488#define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
489#define RTAS_SYSPARM_UUID 48
490
491
492
493
494
495
496
497#define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
498#define RTAS_SENSOR_TYPE_DR 9002
499#define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
500#define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
501
502
503
504
505#define DIAGNOSTICS_RUN_MODE_DISABLED 0
506#define DIAGNOSTICS_RUN_MODE_STAGGERED 1
507#define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
508#define DIAGNOSTICS_RUN_MODE_PERIODIC 3
509
510static inline uint64_t ppc64_phys_to_real(uint64_t addr)
511{
512 return addr & ~0xF000000000000000ULL;
513}
514
515static inline uint32_t rtas_ld(target_ulong phys, int n)
516{
517 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
518}
519
520static inline uint64_t rtas_ldq(target_ulong phys, int n)
521{
522 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
523}
524
525static inline void rtas_st(target_ulong phys, int n, uint32_t val)
526{
527 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
528}
529
530typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
531 uint32_t token,
532 uint32_t nargs, target_ulong args,
533 uint32_t nret, target_ulong rets);
534void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
535target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
536 uint32_t token, uint32_t nargs, target_ulong args,
537 uint32_t nret, target_ulong rets);
538void spapr_dt_rtas_tokens(void *fdt, int rtas);
539void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
540
541#define SPAPR_TCE_PAGE_SHIFT 12
542#define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
543#define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
544
545#define SPAPR_VIO_BASE_LIOBN 0x00000000
546#define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
547#define SPAPR_PCI_LIOBN(phb_index, window_num) \
548 (0x80000000 | ((phb_index) << 8) | (window_num))
549#define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
550#define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
551
552#define RTAS_ERROR_LOG_MAX 2048
553
554#define RTAS_EVENT_SCAN_RATE 1
555
556typedef struct sPAPRTCETable sPAPRTCETable;
557
558#define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
559#define SPAPR_TCE_TABLE(obj) \
560 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
561
562struct sPAPRTCETable {
563 DeviceState parent;
564 uint32_t liobn;
565 uint32_t nb_table;
566 uint64_t bus_offset;
567 uint32_t page_shift;
568 uint64_t *table;
569 uint32_t mig_nb_table;
570 uint64_t *mig_table;
571 bool bypass;
572 bool need_vfio;
573 int fd;
574 MemoryRegion root, iommu;
575 struct VIOsPAPRDevice *vdev;
576 QLIST_ENTRY(sPAPRTCETable) list;
577};
578
579sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
580
581struct sPAPREventLogEntry {
582 int log_type;
583 bool exception;
584 void *data;
585 QTAILQ_ENTRY(sPAPREventLogEntry) next;
586};
587
588void spapr_events_init(sPAPRMachineState *sm);
589void spapr_dt_events(sPAPRMachineState *sm, void *fdt);
590int spapr_h_cas_compose_response(sPAPRMachineState *sm,
591 target_ulong addr, target_ulong size,
592 bool cpu_update,
593 sPAPROptionVector *ov5_updates);
594sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
595void spapr_tce_table_enable(sPAPRTCETable *tcet,
596 uint32_t page_shift, uint64_t bus_offset,
597 uint32_t nb_table);
598void spapr_tce_table_disable(sPAPRTCETable *tcet);
599void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
600
601MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
602int spapr_dma_dt(void *fdt, int node_off, const char *propname,
603 uint32_t liobn, uint64_t window, uint32_t size);
604int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
605 sPAPRTCETable *tcet);
606void spapr_pci_switch_vga(bool big_endian);
607void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
608void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
609void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
610 uint32_t count);
611void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
612 uint32_t count);
613void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type,
614 uint32_t count, uint32_t index);
615void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type,
616 uint32_t count, uint32_t index);
617void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp);
618void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
619 sPAPRMachineState *spapr);
620
621
622struct sPAPRConfigureConnectorState {
623 uint32_t drc_index;
624 int fdt_offset;
625 int fdt_depth;
626 QTAILQ_ENTRY(sPAPRConfigureConnectorState) next;
627};
628
629void spapr_ccs_reset_hook(void *opaque);
630
631#define TYPE_SPAPR_RTC "spapr-rtc"
632#define TYPE_SPAPR_RNG "spapr-rng"
633
634void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns);
635int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset);
636
637int spapr_rng_populate_dt(void *fdt);
638
639#define SPAPR_MEMORY_BLOCK_SIZE (1 << 28)
640
641
642
643
644
645
646#define SPAPR_MAX_RAM_SLOTS 32
647
648
649#define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
650
651
652
653
654
655#define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
656
657
658
659
660
661#define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
662#define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
663#define SPAPR_LMB_FLAGS_RESERVED 0x00000080
664
665#endif
666