LXR qemu/include/hw/scsi/esp.h

   1#ifndef QEMU_HW_ESP_H
   2#define QEMU_HW_ESP_H
   3
   4#include "hw/scsi/scsi.h"
   5
   6/* esp.c */
   7#define ESP_MAX_DEVS 7
   8typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
   9void esp_init(hwaddr espaddr, int it_shift,
  10              ESPDMAMemoryReadWriteFunc dma_memory_read,
  11              ESPDMAMemoryReadWriteFunc dma_memory_write,
  12              void *dma_opaque, qemu_irq irq, qemu_irq *reset,
  13              qemu_irq *dma_enable);
  14
  15#define ESP_REGS 16
  16#define TI_BUFSZ 16
  17#define ESP_CMDBUF_SZ 32
  18
  19typedef struct ESPState ESPState;
  20
  21struct ESPState {
  22    uint8_t rregs[ESP_REGS];
  23    uint8_t wregs[ESP_REGS];
  24    qemu_irq irq;
  25    uint8_t chip_id;
  26    bool tchi_written;
  27    int32_t ti_size;
  28    uint32_t ti_rptr, ti_wptr;
  29    uint32_t status;
  30    uint32_t dma;
  31    uint8_t ti_buf[TI_BUFSZ];
  32    SCSIBus bus;
  33    SCSIDevice *current_dev;
  34    SCSIRequest *current_req;
  35    uint8_t cmdbuf[ESP_CMDBUF_SZ];
  36    uint32_t cmdlen;
  37    uint32_t do_cmd;
  38
  39    /* The amount of data left in the current DMA transfer.  */
  40    uint32_t dma_left;
  41    /* The size of the current DMA transfer.  Zero if no transfer is in
  42       progress.  */
  43    uint32_t dma_counter;
  44    int dma_enabled;
  45
  46    uint32_t async_len;
  47    uint8_t *async_buf;
  48
  49    ESPDMAMemoryReadWriteFunc dma_memory_read;
  50    ESPDMAMemoryReadWriteFunc dma_memory_write;
  51    void *dma_opaque;
  52    void (*dma_cb)(ESPState *s);
  53};
  54
  55#define ESP_TCLO   0x0
  56#define ESP_TCMID  0x1
  57#define ESP_FIFO   0x2
  58#define ESP_CMD    0x3
  59#define ESP_RSTAT  0x4
  60#define ESP_WBUSID 0x4
  61#define ESP_RINTR  0x5
  62#define ESP_WSEL   0x5
  63#define ESP_RSEQ   0x6
  64#define ESP_WSYNTP 0x6
  65#define ESP_RFLAGS 0x7
  66#define ESP_WSYNO  0x7
  67#define ESP_CFG1   0x8
  68#define ESP_RRES1  0x9
  69#define ESP_WCCF   0x9
  70#define ESP_RRES2  0xa
  71#define ESP_WTEST  0xa
  72#define ESP_CFG2   0xb
  73#define ESP_CFG3   0xc
  74#define ESP_RES3   0xd
  75#define ESP_TCHI   0xe
  76#define ESP_RES4   0xf
  77
  78#define CMD_DMA 0x80
  79#define CMD_CMD 0x7f
  80
  81#define CMD_NOP      0x00
  82#define CMD_FLUSH    0x01
  83#define CMD_RESET    0x02
  84#define CMD_BUSRESET 0x03
  85#define CMD_TI       0x10
  86#define CMD_ICCS     0x11
  87#define CMD_MSGACC   0x12
  88#define CMD_PAD      0x18
  89#define CMD_SATN     0x1a
  90#define CMD_RSTATN   0x1b
  91#define CMD_SEL      0x41
  92#define CMD_SELATN   0x42
  93#define CMD_SELATNS  0x43
  94#define CMD_ENSEL    0x44
  95#define CMD_DISSEL   0x45
  96
  97#define STAT_DO 0x00
  98#define STAT_DI 0x01
  99#define STAT_CD 0x02
 100#define STAT_ST 0x03
 101#define STAT_MO 0x06
 102#define STAT_MI 0x07
 103#define STAT_PIO_MASK 0x06
 104
 105#define STAT_TC 0x10
 106#define STAT_PE 0x20
 107#define STAT_GE 0x40
 108#define STAT_INT 0x80
 109
 110#define BUSID_DID 0x07
 111
 112#define INTR_FC 0x08
 113#define INTR_BS 0x10
 114#define INTR_DC 0x20
 115#define INTR_RST 0x80
 116
 117#define SEQ_0 0x0
 118#define SEQ_CD 0x4
 119
 120#define CFG1_RESREPT 0x40
 121
 122#define TCHI_FAS100A 0x4
 123#define TCHI_AM53C974 0x12
 124
 125void esp_dma_enable(ESPState *s, int irq, int level);
 126void esp_request_cancelled(SCSIRequest *req);
 127void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid);
 128void esp_transfer_data(SCSIRequest *req, uint32_t len);
 129void esp_hard_reset(ESPState *s);
 130uint64_t esp_reg_read(ESPState *s, uint32_t saddr);
 131void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val);
 132extern const VMStateDescription vmstate_esp;
 133
 134#endif
 135