LXR qemu/include/hw/ssi/aspeed

   1/*
   2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
   3 *
   4 * Copyright (C) 2016 IBM Corp.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#ifndef ASPEED_SMC_H
  26#define ASPEED_SMC_H
  27
  28#include "hw/ssi/ssi.h"
  29
  30typedef struct AspeedSegments {
  31    hwaddr addr;
  32    uint32_t size;
  33} AspeedSegments;
  34
  35struct AspeedSMCState;
  36typedef struct AspeedSMCController {
  37    const char *name;
  38    uint8_t r_conf;
  39    uint8_t r_ce_ctrl;
  40    uint8_t r_ctrl0;
  41    uint8_t r_timings;
  42    uint8_t conf_enable_w0;
  43    uint8_t max_slaves;
  44    const AspeedSegments *segments;
  45    hwaddr flash_window_base;
  46    uint32_t flash_window_size;
  47} AspeedSMCController;
  48
  49typedef struct AspeedSMCFlash {
  50    const struct AspeedSMCState *controller;
  51
  52    uint8_t id;
  53    uint32_t size;
  54
  55    MemoryRegion mmio;
  56    DeviceState *flash;
  57} AspeedSMCFlash;
  58
  59#define TYPE_ASPEED_SMC "aspeed.smc"
  60#define ASPEED_SMC(obj) OBJECT_CHECK(AspeedSMCState, (obj), TYPE_ASPEED_SMC)
  61#define ASPEED_SMC_CLASS(klass) \
  62     OBJECT_CLASS_CHECK(AspeedSMCClass, (klass), TYPE_ASPEED_SMC)
  63#define ASPEED_SMC_GET_CLASS(obj) \
  64     OBJECT_GET_CLASS(AspeedSMCClass, (obj), TYPE_ASPEED_SMC)
  65
  66typedef struct  AspeedSMCClass {
  67    SysBusDevice parent_obj;
  68    const AspeedSMCController *ctrl;
  69}  AspeedSMCClass;
  70
  71#define ASPEED_SMC_R_MAX        (0x100 / 4)
  72
  73typedef struct AspeedSMCState {
  74    SysBusDevice parent_obj;
  75
  76    const AspeedSMCController *ctrl;
  77
  78    MemoryRegion mmio;
  79    MemoryRegion mmio_flash;
  80
  81    qemu_irq irq;
  82    int irqline;
  83
  84    uint32_t num_cs;
  85    qemu_irq *cs_lines;
  86
  87    SSIBus *spi;
  88
  89    uint32_t regs[ASPEED_SMC_R_MAX];
  90
  91    /* depends on the controller type */
  92    uint8_t r_conf;
  93    uint8_t r_ce_ctrl;
  94    uint8_t r_ctrl0;
  95    uint8_t r_timings;
  96    uint8_t conf_enable_w0;
  97
  98    AspeedSMCFlash *flashes;
  99} AspeedSMCState;
 100
 101#endif /* ASPEED_SMC_H */
 102