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11#include "qemu/osdep.h"
12#include "cpu.h"
13#include "cpu-qom.h"
14#include "internals.h"
15#include "arm-powerctl.h"
16#include "qemu/log.h"
17#include "exec/exec-all.h"
18
19#ifndef DEBUG_ARM_POWERCTL
20#define DEBUG_ARM_POWERCTL 0
21#endif
22
23#define DPRINTF(fmt, args...) \
24 do { \
25 if (DEBUG_ARM_POWERCTL) { \
26 fprintf(stderr, "[ARM]%s: " fmt , __func__, ##args); \
27 } \
28 } while (0)
29
30CPUState *arm_get_cpu_by_id(uint64_t id)
31{
32 CPUState *cpu;
33
34 DPRINTF("cpu %" PRId64 "\n", id);
35
36 CPU_FOREACH(cpu) {
37 ARMCPU *armcpu = ARM_CPU(cpu);
38
39 if (armcpu->mp_affinity == id) {
40 return cpu;
41 }
42 }
43
44 qemu_log_mask(LOG_GUEST_ERROR,
45 "[ARM]%s: Requesting unknown CPU %" PRId64 "\n",
46 __func__, id);
47
48 return NULL;
49}
50
51int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id,
52 uint32_t target_el, bool target_aa64)
53{
54 CPUState *target_cpu_state;
55 ARMCPU *target_cpu;
56
57 DPRINTF("cpu %" PRId64 " (EL %d, %s) @ 0x%" PRIx64 " with R0 = 0x%" PRIx64
58 "\n", cpuid, target_el, target_aa64 ? "aarch64" : "aarch32", entry,
59 context_id);
60
61
62 assert((target_el > 0) && (target_el < 4));
63
64 if (target_aa64 && (entry & 3)) {
65
66
67
68
69 return QEMU_ARM_POWERCTL_INVALID_PARAM;
70 }
71
72
73 target_cpu_state = arm_get_cpu_by_id(cpuid);
74 if (!target_cpu_state) {
75
76 return QEMU_ARM_POWERCTL_INVALID_PARAM;
77 }
78
79 target_cpu = ARM_CPU(target_cpu_state);
80 if (!target_cpu->powered_off) {
81 qemu_log_mask(LOG_GUEST_ERROR,
82 "[ARM]%s: CPU %" PRId64 " is already on\n",
83 __func__, cpuid);
84 return QEMU_ARM_POWERCTL_ALREADY_ON;
85 }
86
87
88
89
90
91
92 if (((target_el == 3) && !arm_feature(&target_cpu->env, ARM_FEATURE_EL3)) ||
93 ((target_el == 2) && !arm_feature(&target_cpu->env, ARM_FEATURE_EL2))) {
94
95
96
97 return QEMU_ARM_POWERCTL_INVALID_PARAM;
98 }
99
100 if (!target_aa64 && arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64)) {
101
102
103
104
105 qemu_log_mask(LOG_UNIMP,
106 "[ARM]%s: Starting AArch64 CPU %" PRId64
107 " in AArch32 mode is not supported yet\n",
108 __func__, cpuid);
109 return QEMU_ARM_POWERCTL_INVALID_PARAM;
110 }
111
112
113 cpu_reset(target_cpu_state);
114 target_cpu->powered_off = false;
115 target_cpu_state->halted = 0;
116
117 if (target_aa64) {
118 if ((target_el < 3) && arm_feature(&target_cpu->env, ARM_FEATURE_EL3)) {
119
120
121
122
123 target_cpu->env.cp15.scr_el3 |= SCR_RW;
124 }
125
126 if ((target_el < 2) && arm_feature(&target_cpu->env, ARM_FEATURE_EL2)) {
127
128
129
130
131 target_cpu->env.cp15.hcr_el2 |= HCR_RW;
132 }
133
134 target_cpu->env.pstate = aarch64_pstate_mode(target_el, true);
135 } else {
136
137 static uint32_t mode_for_el[] = { 0,
138 ARM_CPU_MODE_SVC,
139 ARM_CPU_MODE_HYP,
140 ARM_CPU_MODE_SVC };
141
142 cpsr_write(&target_cpu->env, mode_for_el[target_el], CPSR_M,
143 CPSRWriteRaw);
144 }
145
146 if (target_el == 3) {
147
148 target_cpu->env.cp15.scr_el3 &= ~SCR_NS;
149 } else {
150
151 target_cpu->env.cp15.scr_el3 |= SCR_NS;
152 }
153
154
155 assert(target_el == arm_current_el(&target_cpu->env));
156
157 if (target_aa64) {
158 target_cpu->env.xregs[0] = context_id;
159 target_cpu->env.thumb = false;
160 } else {
161 target_cpu->env.regs[0] = context_id;
162 target_cpu->env.thumb = entry & 1;
163 entry &= 0xfffffffe;
164 }
165
166
167 cpu_set_pc(target_cpu_state, entry);
168
169 qemu_cpu_kick(target_cpu_state);
170
171
172 return QEMU_ARM_POWERCTL_RET_SUCCESS;
173}
174
175int arm_set_cpu_off(uint64_t cpuid)
176{
177 CPUState *target_cpu_state;
178 ARMCPU *target_cpu;
179
180 DPRINTF("cpu %" PRId64 "\n", cpuid);
181
182
183 target_cpu_state = arm_get_cpu_by_id(cpuid);
184 if (!target_cpu_state) {
185 return QEMU_ARM_POWERCTL_INVALID_PARAM;
186 }
187 target_cpu = ARM_CPU(target_cpu_state);
188 if (target_cpu->powered_off) {
189 qemu_log_mask(LOG_GUEST_ERROR,
190 "[ARM]%s: CPU %" PRId64 " is already off\n",
191 __func__, cpuid);
192 return QEMU_ARM_POWERCTL_IS_OFF;
193 }
194
195 target_cpu->powered_off = true;
196 target_cpu_state->halted = 1;
197 target_cpu_state->exception_index = EXCP_HLT;
198 cpu_loop_exit(target_cpu_state);
199
200
201 return QEMU_ARM_POWERCTL_RET_SUCCESS;
202}
203
204int arm_reset_cpu(uint64_t cpuid)
205{
206 CPUState *target_cpu_state;
207 ARMCPU *target_cpu;
208
209 DPRINTF("cpu %" PRId64 "\n", cpuid);
210
211
212 target_cpu_state = arm_get_cpu_by_id(cpuid);
213 if (!target_cpu_state) {
214 return QEMU_ARM_POWERCTL_INVALID_PARAM;
215 }
216 target_cpu = ARM_CPU(target_cpu_state);
217 if (target_cpu->powered_off) {
218 qemu_log_mask(LOG_GUEST_ERROR,
219 "[ARM]%s: CPU %" PRId64 " is off\n",
220 __func__, cpuid);
221 return QEMU_ARM_POWERCTL_IS_OFF;
222 }
223
224
225 cpu_reset(target_cpu_state);
226
227 return QEMU_ARM_POWERCTL_RET_SUCCESS;
228}
229