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21#include "qemu/osdep.h"
22#include "qemu/error-report.h"
23#include "qapi/error.h"
24#include "cpu.h"
25#include "internals.h"
26#include "qemu-common.h"
27#include "exec/exec-all.h"
28#include "hw/qdev-properties.h"
29#if !defined(CONFIG_USER_ONLY)
30#include "hw/loader.h"
31#endif
32#include "hw/arm/arm.h"
33#include "sysemu/sysemu.h"
34#include "sysemu/kvm.h"
35#include "kvm_arm.h"
36
37static void arm_cpu_set_pc(CPUState *cs, vaddr value)
38{
39 ARMCPU *cpu = ARM_CPU(cs);
40
41 cpu->env.regs[15] = value;
42}
43
44static bool arm_cpu_has_work(CPUState *cs)
45{
46 ARMCPU *cpu = ARM_CPU(cs);
47
48 return !cpu->powered_off
49 && cs->interrupt_request &
50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
52 | CPU_INTERRUPT_EXITTB);
53}
54
55void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
56 void *opaque)
57{
58
59 assert(!cpu->el_change_hook);
60 cpu->el_change_hook = hook;
61 cpu->el_change_hook_opaque = opaque;
62}
63
64static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
65{
66
67 ARMCPRegInfo *ri = value;
68 ARMCPU *cpu = opaque;
69
70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
71 return;
72 }
73
74 if (ri->resetfn) {
75 ri->resetfn(&cpu->env, ri);
76 return;
77 }
78
79
80
81
82
83
84 if (!ri->fieldoffset) {
85 return;
86 }
87
88 if (cpreg_field_is_64bit(ri)) {
89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
90 } else {
91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
92 }
93}
94
95static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
96{
97
98
99
100
101
102 ARMCPRegInfo *ri = value;
103 ARMCPU *cpu = opaque;
104 uint64_t oldvalue, newvalue;
105
106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
107 return;
108 }
109
110 oldvalue = read_raw_cp_reg(&cpu->env, ri);
111 cp_reg_reset(key, value, opaque);
112 newvalue = read_raw_cp_reg(&cpu->env, ri);
113 assert(oldvalue == newvalue);
114}
115
116
117static void arm_cpu_reset(CPUState *s)
118{
119 ARMCPU *cpu = ARM_CPU(s);
120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
121 CPUARMState *env = &cpu->env;
122
123 acc->parent_reset(s);
124
125 memset(env, 0, offsetof(CPUARMState, features));
126 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
127 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
128
129 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
130 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
131 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
132 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
133
134 cpu->powered_off = cpu->start_powered_off;
135 s->halted = cpu->start_powered_off;
136
137 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
138 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
139 }
140
141 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
142
143 env->aarch64 = 1;
144#if defined(CONFIG_USER_ONLY)
145 env->pstate = PSTATE_MODE_EL0t;
146
147 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
148
149 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
150#else
151
152 if (arm_feature(env, ARM_FEATURE_EL3)) {
153 env->pstate = PSTATE_MODE_EL3h;
154 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
155 env->pstate = PSTATE_MODE_EL2h;
156 } else {
157 env->pstate = PSTATE_MODE_EL1h;
158 }
159 env->pc = cpu->rvbar;
160#endif
161 } else {
162#if defined(CONFIG_USER_ONLY)
163
164 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
165#endif
166 }
167
168#if defined(CONFIG_USER_ONLY)
169 env->uncached_cpsr = ARM_CPU_MODE_USR;
170
171 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
172 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
173 env->cp15.c15_cpar = 3;
174 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
175 env->cp15.c15_cpar = 1;
176 }
177#else
178
179 env->uncached_cpsr = ARM_CPU_MODE_SVC;
180 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
181
182
183
184 if (IS_M(env)) {
185 uint32_t initial_msp;
186 uint32_t initial_pc;
187 uint8_t *rom;
188
189 env->daif &= ~PSTATE_I;
190 rom = rom_ptr(0);
191 if (rom) {
192
193
194
195 initial_msp = ldl_p(rom);
196 initial_pc = ldl_p(rom + 4);
197 } else {
198
199
200
201
202
203 initial_msp = ldl_phys(s->as, 0);
204 initial_pc = ldl_phys(s->as, 4);
205 }
206
207 env->regs[13] = initial_msp & 0xFFFFFFFC;
208 env->regs[15] = initial_pc & ~1;
209 env->thumb = initial_pc & 1;
210 }
211
212
213
214
215
216 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
217 env->regs[15] = 0xFFFF0000;
218 }
219
220 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
221#endif
222 set_flush_to_zero(1, &env->vfp.standard_fp_status);
223 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
224 set_default_nan_mode(1, &env->vfp.standard_fp_status);
225 set_float_detect_tininess(float_tininess_before_rounding,
226 &env->vfp.fp_status);
227 set_float_detect_tininess(float_tininess_before_rounding,
228 &env->vfp.standard_fp_status);
229 tlb_flush(s, 1);
230
231#ifndef CONFIG_USER_ONLY
232 if (kvm_enabled()) {
233 kvm_arm_reset_vcpu(cpu);
234 }
235#endif
236
237 hw_breakpoint_update_all(cpu);
238 hw_watchpoint_update_all(cpu);
239}
240
241bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
242{
243 CPUClass *cc = CPU_GET_CLASS(cs);
244 CPUARMState *env = cs->env_ptr;
245 uint32_t cur_el = arm_current_el(env);
246 bool secure = arm_is_secure(env);
247 uint32_t target_el;
248 uint32_t excp_idx;
249 bool ret = false;
250
251 if (interrupt_request & CPU_INTERRUPT_FIQ) {
252 excp_idx = EXCP_FIQ;
253 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
254 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
255 cs->exception_index = excp_idx;
256 env->exception.target_el = target_el;
257 cc->do_interrupt(cs);
258 ret = true;
259 }
260 }
261 if (interrupt_request & CPU_INTERRUPT_HARD) {
262 excp_idx = EXCP_IRQ;
263 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
264 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
265 cs->exception_index = excp_idx;
266 env->exception.target_el = target_el;
267 cc->do_interrupt(cs);
268 ret = true;
269 }
270 }
271 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
272 excp_idx = EXCP_VIRQ;
273 target_el = 1;
274 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
275 cs->exception_index = excp_idx;
276 env->exception.target_el = target_el;
277 cc->do_interrupt(cs);
278 ret = true;
279 }
280 }
281 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
282 excp_idx = EXCP_VFIQ;
283 target_el = 1;
284 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
285 cs->exception_index = excp_idx;
286 env->exception.target_el = target_el;
287 cc->do_interrupt(cs);
288 ret = true;
289 }
290 }
291
292 return ret;
293}
294
295#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
296static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
297{
298 CPUClass *cc = CPU_GET_CLASS(cs);
299 ARMCPU *cpu = ARM_CPU(cs);
300 CPUARMState *env = &cpu->env;
301 bool ret = false;
302
303
304 if (interrupt_request & CPU_INTERRUPT_FIQ
305 && !(env->daif & PSTATE_F)) {
306 cs->exception_index = EXCP_FIQ;
307 cc->do_interrupt(cs);
308 ret = true;
309 }
310
311
312
313
314
315
316
317
318
319
320 if (interrupt_request & CPU_INTERRUPT_HARD
321 && !(env->daif & PSTATE_I)
322 && (env->regs[15] < 0xfffffff0)) {
323 cs->exception_index = EXCP_IRQ;
324 cc->do_interrupt(cs);
325 ret = true;
326 }
327 return ret;
328}
329#endif
330
331#ifndef CONFIG_USER_ONLY
332static void arm_cpu_set_irq(void *opaque, int irq, int level)
333{
334 ARMCPU *cpu = opaque;
335 CPUARMState *env = &cpu->env;
336 CPUState *cs = CPU(cpu);
337 static const int mask[] = {
338 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
339 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
340 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
341 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
342 };
343
344 switch (irq) {
345 case ARM_CPU_VIRQ:
346 case ARM_CPU_VFIQ:
347 assert(arm_feature(env, ARM_FEATURE_EL2));
348
349 case ARM_CPU_IRQ:
350 case ARM_CPU_FIQ:
351 if (level) {
352 cpu_interrupt(cs, mask[irq]);
353 } else {
354 cpu_reset_interrupt(cs, mask[irq]);
355 }
356 break;
357 default:
358 g_assert_not_reached();
359 }
360}
361
362static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
363{
364#ifdef CONFIG_KVM
365 ARMCPU *cpu = opaque;
366 CPUState *cs = CPU(cpu);
367 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
368
369 switch (irq) {
370 case ARM_CPU_IRQ:
371 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
372 break;
373 case ARM_CPU_FIQ:
374 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
375 break;
376 default:
377 g_assert_not_reached();
378 }
379 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
380 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
381#endif
382}
383
384static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
385{
386 ARMCPU *cpu = ARM_CPU(cs);
387 CPUARMState *env = &cpu->env;
388
389 cpu_synchronize_state(cs);
390 return arm_cpu_data_is_big_endian(env);
391}
392
393#endif
394
395static inline void set_feature(CPUARMState *env, int feature)
396{
397 env->features |= 1ULL << feature;
398}
399
400static inline void unset_feature(CPUARMState *env, int feature)
401{
402 env->features &= ~(1ULL << feature);
403}
404
405static int
406print_insn_thumb1(bfd_vma pc, disassemble_info *info)
407{
408 return print_insn_arm(pc | 1, info);
409}
410
411static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
412{
413 ARMCPU *ac = ARM_CPU(cpu);
414 CPUARMState *env = &ac->env;
415
416 if (is_a64(env)) {
417
418
419
420
421#if defined(CONFIG_ARM_A64_DIS)
422 info->print_insn = print_insn_arm_a64;
423#endif
424 } else if (env->thumb) {
425 info->print_insn = print_insn_thumb1;
426 } else {
427 info->print_insn = print_insn_arm;
428 }
429 if (bswap_code(arm_sctlr_b(env))) {
430#ifdef TARGET_WORDS_BIGENDIAN
431 info->endian = BFD_ENDIAN_LITTLE;
432#else
433 info->endian = BFD_ENDIAN_BIG;
434#endif
435 }
436}
437
438static void arm_cpu_initfn(Object *obj)
439{
440 CPUState *cs = CPU(obj);
441 ARMCPU *cpu = ARM_CPU(obj);
442 static bool inited;
443
444 cs->env_ptr = &cpu->env;
445 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
446 g_free, g_free);
447
448#ifndef CONFIG_USER_ONLY
449
450 if (kvm_enabled()) {
451
452
453
454 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
455 } else {
456 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
457 }
458
459 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
460 arm_gt_ptimer_cb, cpu);
461 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
462 arm_gt_vtimer_cb, cpu);
463 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
464 arm_gt_htimer_cb, cpu);
465 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
466 arm_gt_stimer_cb, cpu);
467 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
468 ARRAY_SIZE(cpu->gt_timer_outputs));
469#endif
470
471
472
473
474
475 cpu->dtb_compatible = "qemu,unknown";
476 cpu->psci_version = 1;
477 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
478
479 if (tcg_enabled()) {
480 cpu->psci_version = 2;
481 if (!inited) {
482 inited = true;
483 arm_translate_init();
484 }
485 }
486}
487
488static Property arm_cpu_reset_cbar_property =
489 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
490
491static Property arm_cpu_reset_hivecs_property =
492 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
493
494static Property arm_cpu_rvbar_property =
495 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
496
497static Property arm_cpu_has_el3_property =
498 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
499
500
501static Property arm_cpu_has_pmu_property =
502 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
503
504static Property arm_cpu_has_mpu_property =
505 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
506
507static Property arm_cpu_pmsav7_dregion_property =
508 DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
509
510static void arm_cpu_post_init(Object *obj)
511{
512 ARMCPU *cpu = ARM_CPU(obj);
513
514 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
515 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
516 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
517 &error_abort);
518 }
519
520 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
521 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
522 &error_abort);
523 }
524
525 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
526 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
527 &error_abort);
528 }
529
530 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
531
532
533
534 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
535 &error_abort);
536
537#ifndef CONFIG_USER_ONLY
538 object_property_add_link(obj, "secure-memory",
539 TYPE_MEMORY_REGION,
540 (Object **)&cpu->secure_memory,
541 qdev_prop_allow_set_link_before_realize,
542 OBJ_PROP_LINK_UNREF_ON_RELEASE,
543 &error_abort);
544#endif
545 }
546
547 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
548 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
549 &error_abort);
550 }
551
552 if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
553 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
554 &error_abort);
555 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
556 qdev_property_add_static(DEVICE(obj),
557 &arm_cpu_pmsav7_dregion_property,
558 &error_abort);
559 }
560 }
561
562}
563
564static void arm_cpu_finalizefn(Object *obj)
565{
566 ARMCPU *cpu = ARM_CPU(obj);
567 g_hash_table_destroy(cpu->cp_regs);
568}
569
570static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
571{
572 CPUState *cs = CPU(dev);
573 ARMCPU *cpu = ARM_CPU(dev);
574 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
575 CPUARMState *env = &cpu->env;
576 int pagebits;
577 Error *local_err = NULL;
578
579 cpu_exec_realizefn(cs, &local_err);
580 if (local_err != NULL) {
581 error_propagate(errp, local_err);
582 return;
583 }
584
585
586 if (arm_feature(env, ARM_FEATURE_V8)) {
587 set_feature(env, ARM_FEATURE_V7);
588 set_feature(env, ARM_FEATURE_ARM_DIV);
589 set_feature(env, ARM_FEATURE_LPAE);
590 }
591 if (arm_feature(env, ARM_FEATURE_V7)) {
592 set_feature(env, ARM_FEATURE_VAPA);
593 set_feature(env, ARM_FEATURE_THUMB2);
594 set_feature(env, ARM_FEATURE_MPIDR);
595 if (!arm_feature(env, ARM_FEATURE_M)) {
596 set_feature(env, ARM_FEATURE_V6K);
597 } else {
598 set_feature(env, ARM_FEATURE_V6);
599 }
600 }
601 if (arm_feature(env, ARM_FEATURE_V6K)) {
602 set_feature(env, ARM_FEATURE_V6);
603 set_feature(env, ARM_FEATURE_MVFR);
604 }
605 if (arm_feature(env, ARM_FEATURE_V6)) {
606 set_feature(env, ARM_FEATURE_V5);
607 if (!arm_feature(env, ARM_FEATURE_M)) {
608 set_feature(env, ARM_FEATURE_AUXCR);
609 }
610 }
611 if (arm_feature(env, ARM_FEATURE_V5)) {
612 set_feature(env, ARM_FEATURE_V4T);
613 }
614 if (arm_feature(env, ARM_FEATURE_M)) {
615 set_feature(env, ARM_FEATURE_THUMB_DIV);
616 }
617 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
618 set_feature(env, ARM_FEATURE_THUMB_DIV);
619 }
620 if (arm_feature(env, ARM_FEATURE_VFP4)) {
621 set_feature(env, ARM_FEATURE_VFP3);
622 set_feature(env, ARM_FEATURE_VFP_FP16);
623 }
624 if (arm_feature(env, ARM_FEATURE_VFP3)) {
625 set_feature(env, ARM_FEATURE_VFP);
626 }
627 if (arm_feature(env, ARM_FEATURE_LPAE)) {
628 set_feature(env, ARM_FEATURE_V7MP);
629 set_feature(env, ARM_FEATURE_PXN);
630 }
631 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
632 set_feature(env, ARM_FEATURE_CBAR);
633 }
634 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
635 !arm_feature(env, ARM_FEATURE_M)) {
636 set_feature(env, ARM_FEATURE_THUMB_DSP);
637 }
638
639 if (arm_feature(env, ARM_FEATURE_V7) &&
640 !arm_feature(env, ARM_FEATURE_M) &&
641 !arm_feature(env, ARM_FEATURE_MPU)) {
642
643
644
645 pagebits = 12;
646 } else {
647
648
649
650 pagebits = 10;
651 }
652 if (!set_preferred_target_page_bits(pagebits)) {
653
654
655
656
657 error_setg(errp, "This CPU requires a smaller page size than the "
658 "system is using");
659 return;
660 }
661
662
663
664
665
666
667 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
668 uint32_t Aff1 = cs->cpu_index / ARM_DEFAULT_CPUS_PER_CLUSTER;
669 uint32_t Aff0 = cs->cpu_index % ARM_DEFAULT_CPUS_PER_CLUSTER;
670 cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
671 }
672
673 if (cpu->reset_hivecs) {
674 cpu->reset_sctlr |= (1 << 13);
675 }
676
677 if (!cpu->has_el3) {
678
679
680
681 unset_feature(env, ARM_FEATURE_EL3);
682
683
684
685
686 cpu->id_pfr1 &= ~0xf0;
687 cpu->id_aa64pfr0 &= ~0xf000;
688 }
689
690 if (!cpu->has_pmu || !kvm_enabled()) {
691 cpu->has_pmu = false;
692 unset_feature(env, ARM_FEATURE_PMU);
693 }
694
695 if (!arm_feature(env, ARM_FEATURE_EL2)) {
696
697
698
699
700 cpu->id_aa64pfr0 &= ~0xf00;
701 cpu->id_pfr1 &= ~0xf000;
702 }
703
704 if (!cpu->has_mpu) {
705 unset_feature(env, ARM_FEATURE_MPU);
706 }
707
708 if (arm_feature(env, ARM_FEATURE_MPU) &&
709 arm_feature(env, ARM_FEATURE_V7)) {
710 uint32_t nr = cpu->pmsav7_dregion;
711
712 if (nr > 0xff) {
713 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
714 return;
715 }
716
717 if (nr) {
718 env->pmsav7.drbar = g_new0(uint32_t, nr);
719 env->pmsav7.drsr = g_new0(uint32_t, nr);
720 env->pmsav7.dracr = g_new0(uint32_t, nr);
721 }
722 }
723
724 register_cp_regs_for_features(cpu);
725 arm_cpu_register_gdb_regs_for_features(cpu);
726
727 init_cpreg_list(cpu);
728
729#ifndef CONFIG_USER_ONLY
730 if (cpu->has_el3) {
731 cs->num_ases = 2;
732 } else {
733 cs->num_ases = 1;
734 }
735
736 if (cpu->has_el3) {
737 AddressSpace *as;
738
739 if (!cpu->secure_memory) {
740 cpu->secure_memory = cs->memory;
741 }
742 as = address_space_init_shareable(cpu->secure_memory,
743 "cpu-secure-memory");
744 cpu_address_space_init(cs, as, ARMASIdx_S);
745 }
746 cpu_address_space_init(cs,
747 address_space_init_shareable(cs->memory,
748 "cpu-memory"),
749 ARMASIdx_NS);
750#endif
751
752 qemu_init_vcpu(cs);
753 cpu_reset(cs);
754
755 acc->parent_realize(dev, errp);
756}
757
758static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
759{
760 ObjectClass *oc;
761 char *typename;
762 char **cpuname;
763
764 if (!cpu_model) {
765 return NULL;
766 }
767
768 cpuname = g_strsplit(cpu_model, ",", 1);
769 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
770 oc = object_class_by_name(typename);
771 g_strfreev(cpuname);
772 g_free(typename);
773 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
774 object_class_is_abstract(oc)) {
775 return NULL;
776 }
777 return oc;
778}
779
780
781#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
782
783static void arm926_initfn(Object *obj)
784{
785 ARMCPU *cpu = ARM_CPU(obj);
786
787 cpu->dtb_compatible = "arm,arm926";
788 set_feature(&cpu->env, ARM_FEATURE_V5);
789 set_feature(&cpu->env, ARM_FEATURE_VFP);
790 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
791 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
792 cpu->midr = 0x41069265;
793 cpu->reset_fpsid = 0x41011090;
794 cpu->ctr = 0x1dd20d2;
795 cpu->reset_sctlr = 0x00090078;
796}
797
798static void arm946_initfn(Object *obj)
799{
800 ARMCPU *cpu = ARM_CPU(obj);
801
802 cpu->dtb_compatible = "arm,arm946";
803 set_feature(&cpu->env, ARM_FEATURE_V5);
804 set_feature(&cpu->env, ARM_FEATURE_MPU);
805 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
806 cpu->midr = 0x41059461;
807 cpu->ctr = 0x0f004006;
808 cpu->reset_sctlr = 0x00000078;
809}
810
811static void arm1026_initfn(Object *obj)
812{
813 ARMCPU *cpu = ARM_CPU(obj);
814
815 cpu->dtb_compatible = "arm,arm1026";
816 set_feature(&cpu->env, ARM_FEATURE_V5);
817 set_feature(&cpu->env, ARM_FEATURE_VFP);
818 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
819 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
820 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
821 cpu->midr = 0x4106a262;
822 cpu->reset_fpsid = 0x410110a0;
823 cpu->ctr = 0x1dd20d2;
824 cpu->reset_sctlr = 0x00090078;
825 cpu->reset_auxcr = 1;
826 {
827
828 ARMCPRegInfo ifar = {
829 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
830 .access = PL1_RW,
831 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
832 .resetvalue = 0
833 };
834 define_one_arm_cp_reg(cpu, &ifar);
835 }
836}
837
838static void arm1136_r2_initfn(Object *obj)
839{
840 ARMCPU *cpu = ARM_CPU(obj);
841
842
843
844
845
846
847
848
849 cpu->dtb_compatible = "arm,arm1136";
850 set_feature(&cpu->env, ARM_FEATURE_V6);
851 set_feature(&cpu->env, ARM_FEATURE_VFP);
852 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
853 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
854 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
855 cpu->midr = 0x4107b362;
856 cpu->reset_fpsid = 0x410120b4;
857 cpu->mvfr0 = 0x11111111;
858 cpu->mvfr1 = 0x00000000;
859 cpu->ctr = 0x1dd20d2;
860 cpu->reset_sctlr = 0x00050078;
861 cpu->id_pfr0 = 0x111;
862 cpu->id_pfr1 = 0x1;
863 cpu->id_dfr0 = 0x2;
864 cpu->id_afr0 = 0x3;
865 cpu->id_mmfr0 = 0x01130003;
866 cpu->id_mmfr1 = 0x10030302;
867 cpu->id_mmfr2 = 0x01222110;
868 cpu->id_isar0 = 0x00140011;
869 cpu->id_isar1 = 0x12002111;
870 cpu->id_isar2 = 0x11231111;
871 cpu->id_isar3 = 0x01102131;
872 cpu->id_isar4 = 0x141;
873 cpu->reset_auxcr = 7;
874}
875
876static void arm1136_initfn(Object *obj)
877{
878 ARMCPU *cpu = ARM_CPU(obj);
879
880 cpu->dtb_compatible = "arm,arm1136";
881 set_feature(&cpu->env, ARM_FEATURE_V6K);
882 set_feature(&cpu->env, ARM_FEATURE_V6);
883 set_feature(&cpu->env, ARM_FEATURE_VFP);
884 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
885 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
886 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
887 cpu->midr = 0x4117b363;
888 cpu->reset_fpsid = 0x410120b4;
889 cpu->mvfr0 = 0x11111111;
890 cpu->mvfr1 = 0x00000000;
891 cpu->ctr = 0x1dd20d2;
892 cpu->reset_sctlr = 0x00050078;
893 cpu->id_pfr0 = 0x111;
894 cpu->id_pfr1 = 0x1;
895 cpu->id_dfr0 = 0x2;
896 cpu->id_afr0 = 0x3;
897 cpu->id_mmfr0 = 0x01130003;
898 cpu->id_mmfr1 = 0x10030302;
899 cpu->id_mmfr2 = 0x01222110;
900 cpu->id_isar0 = 0x00140011;
901 cpu->id_isar1 = 0x12002111;
902 cpu->id_isar2 = 0x11231111;
903 cpu->id_isar3 = 0x01102131;
904 cpu->id_isar4 = 0x141;
905 cpu->reset_auxcr = 7;
906}
907
908static void arm1176_initfn(Object *obj)
909{
910 ARMCPU *cpu = ARM_CPU(obj);
911
912 cpu->dtb_compatible = "arm,arm1176";
913 set_feature(&cpu->env, ARM_FEATURE_V6K);
914 set_feature(&cpu->env, ARM_FEATURE_VFP);
915 set_feature(&cpu->env, ARM_FEATURE_VAPA);
916 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
917 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
918 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
919 set_feature(&cpu->env, ARM_FEATURE_EL3);
920 cpu->midr = 0x410fb767;
921 cpu->reset_fpsid = 0x410120b5;
922 cpu->mvfr0 = 0x11111111;
923 cpu->mvfr1 = 0x00000000;
924 cpu->ctr = 0x1dd20d2;
925 cpu->reset_sctlr = 0x00050078;
926 cpu->id_pfr0 = 0x111;
927 cpu->id_pfr1 = 0x11;
928 cpu->id_dfr0 = 0x33;
929 cpu->id_afr0 = 0;
930 cpu->id_mmfr0 = 0x01130003;
931 cpu->id_mmfr1 = 0x10030302;
932 cpu->id_mmfr2 = 0x01222100;
933 cpu->id_isar0 = 0x0140011;
934 cpu->id_isar1 = 0x12002111;
935 cpu->id_isar2 = 0x11231121;
936 cpu->id_isar3 = 0x01102131;
937 cpu->id_isar4 = 0x01141;
938 cpu->reset_auxcr = 7;
939}
940
941static void arm11mpcore_initfn(Object *obj)
942{
943 ARMCPU *cpu = ARM_CPU(obj);
944
945 cpu->dtb_compatible = "arm,arm11mpcore";
946 set_feature(&cpu->env, ARM_FEATURE_V6K);
947 set_feature(&cpu->env, ARM_FEATURE_VFP);
948 set_feature(&cpu->env, ARM_FEATURE_VAPA);
949 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
950 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
951 cpu->midr = 0x410fb022;
952 cpu->reset_fpsid = 0x410120b4;
953 cpu->mvfr0 = 0x11111111;
954 cpu->mvfr1 = 0x00000000;
955 cpu->ctr = 0x1d192992;
956 cpu->id_pfr0 = 0x111;
957 cpu->id_pfr1 = 0x1;
958 cpu->id_dfr0 = 0;
959 cpu->id_afr0 = 0x2;
960 cpu->id_mmfr0 = 0x01100103;
961 cpu->id_mmfr1 = 0x10020302;
962 cpu->id_mmfr2 = 0x01222000;
963 cpu->id_isar0 = 0x00100011;
964 cpu->id_isar1 = 0x12002111;
965 cpu->id_isar2 = 0x11221011;
966 cpu->id_isar3 = 0x01102131;
967 cpu->id_isar4 = 0x141;
968 cpu->reset_auxcr = 1;
969}
970
971static void cortex_m3_initfn(Object *obj)
972{
973 ARMCPU *cpu = ARM_CPU(obj);
974 set_feature(&cpu->env, ARM_FEATURE_V7);
975 set_feature(&cpu->env, ARM_FEATURE_M);
976 cpu->midr = 0x410fc231;
977}
978
979static void cortex_m4_initfn(Object *obj)
980{
981 ARMCPU *cpu = ARM_CPU(obj);
982
983 set_feature(&cpu->env, ARM_FEATURE_V7);
984 set_feature(&cpu->env, ARM_FEATURE_M);
985 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
986 cpu->midr = 0x410fc240;
987}
988static void arm_v7m_class_init(ObjectClass *oc, void *data)
989{
990 CPUClass *cc = CPU_CLASS(oc);
991
992#ifndef CONFIG_USER_ONLY
993 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
994#endif
995
996 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
997}
998
999static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1000
1001 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1002 .access = PL1_RW, .type = ARM_CP_CONST },
1003 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1004 .access = PL1_RW, .type = ARM_CP_CONST },
1005 REGINFO_SENTINEL
1006};
1007
1008static void cortex_r5_initfn(Object *obj)
1009{
1010 ARMCPU *cpu = ARM_CPU(obj);
1011
1012 set_feature(&cpu->env, ARM_FEATURE_V7);
1013 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
1014 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1015 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1016 set_feature(&cpu->env, ARM_FEATURE_MPU);
1017 cpu->midr = 0x411fc153;
1018 cpu->id_pfr0 = 0x0131;
1019 cpu->id_pfr1 = 0x001;
1020 cpu->id_dfr0 = 0x010400;
1021 cpu->id_afr0 = 0x0;
1022 cpu->id_mmfr0 = 0x0210030;
1023 cpu->id_mmfr1 = 0x00000000;
1024 cpu->id_mmfr2 = 0x01200000;
1025 cpu->id_mmfr3 = 0x0211;
1026 cpu->id_isar0 = 0x2101111;
1027 cpu->id_isar1 = 0x13112111;
1028 cpu->id_isar2 = 0x21232141;
1029 cpu->id_isar3 = 0x01112131;
1030 cpu->id_isar4 = 0x0010142;
1031 cpu->id_isar5 = 0x0;
1032 cpu->mp_is_up = true;
1033 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1034}
1035
1036static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1037 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1038 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1039 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1040 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1041 REGINFO_SENTINEL
1042};
1043
1044static void cortex_a8_initfn(Object *obj)
1045{
1046 ARMCPU *cpu = ARM_CPU(obj);
1047
1048 cpu->dtb_compatible = "arm,cortex-a8";
1049 set_feature(&cpu->env, ARM_FEATURE_V7);
1050 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1051 set_feature(&cpu->env, ARM_FEATURE_NEON);
1052 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1053 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1054 set_feature(&cpu->env, ARM_FEATURE_EL3);
1055 cpu->midr = 0x410fc080;
1056 cpu->reset_fpsid = 0x410330c0;
1057 cpu->mvfr0 = 0x11110222;
1058 cpu->mvfr1 = 0x00011100;
1059 cpu->ctr = 0x82048004;
1060 cpu->reset_sctlr = 0x00c50078;
1061 cpu->id_pfr0 = 0x1031;
1062 cpu->id_pfr1 = 0x11;
1063 cpu->id_dfr0 = 0x400;
1064 cpu->id_afr0 = 0;
1065 cpu->id_mmfr0 = 0x31100003;
1066 cpu->id_mmfr1 = 0x20000000;
1067 cpu->id_mmfr2 = 0x01202000;
1068 cpu->id_mmfr3 = 0x11;
1069 cpu->id_isar0 = 0x00101111;
1070 cpu->id_isar1 = 0x12112111;
1071 cpu->id_isar2 = 0x21232031;
1072 cpu->id_isar3 = 0x11112131;
1073 cpu->id_isar4 = 0x00111142;
1074 cpu->dbgdidr = 0x15141000;
1075 cpu->clidr = (1 << 27) | (2 << 24) | 3;
1076 cpu->ccsidr[0] = 0xe007e01a;
1077 cpu->ccsidr[1] = 0x2007e01a;
1078 cpu->ccsidr[2] = 0xf0000000;
1079 cpu->reset_auxcr = 2;
1080 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1081}
1082
1083static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1084
1085
1086
1087 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1088 .access = PL1_RW, .resetvalue = 0,
1089 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1090 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1091 .access = PL1_RW, .resetvalue = 0,
1092 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1093 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1094 .access = PL1_RW, .resetvalue = 0,
1095 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1096 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1097 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1098
1099 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1100 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1101 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1102 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1103 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1104 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1105 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1106 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1107 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1108 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1109 REGINFO_SENTINEL
1110};
1111
1112static void cortex_a9_initfn(Object *obj)
1113{
1114 ARMCPU *cpu = ARM_CPU(obj);
1115
1116 cpu->dtb_compatible = "arm,cortex-a9";
1117 set_feature(&cpu->env, ARM_FEATURE_V7);
1118 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1119 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1120 set_feature(&cpu->env, ARM_FEATURE_NEON);
1121 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1122 set_feature(&cpu->env, ARM_FEATURE_EL3);
1123
1124
1125
1126
1127 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1128 set_feature(&cpu->env, ARM_FEATURE_CBAR);
1129 cpu->midr = 0x410fc090;
1130 cpu->reset_fpsid = 0x41033090;
1131 cpu->mvfr0 = 0x11110222;
1132 cpu->mvfr1 = 0x01111111;
1133 cpu->ctr = 0x80038003;
1134 cpu->reset_sctlr = 0x00c50078;
1135 cpu->id_pfr0 = 0x1031;
1136 cpu->id_pfr1 = 0x11;
1137 cpu->id_dfr0 = 0x000;
1138 cpu->id_afr0 = 0;
1139 cpu->id_mmfr0 = 0x00100103;
1140 cpu->id_mmfr1 = 0x20000000;
1141 cpu->id_mmfr2 = 0x01230000;
1142 cpu->id_mmfr3 = 0x00002111;
1143 cpu->id_isar0 = 0x00101111;
1144 cpu->id_isar1 = 0x13112111;
1145 cpu->id_isar2 = 0x21232041;
1146 cpu->id_isar3 = 0x11112131;
1147 cpu->id_isar4 = 0x00111142;
1148 cpu->dbgdidr = 0x35141000;
1149 cpu->clidr = (1 << 27) | (1 << 24) | 3;
1150 cpu->ccsidr[0] = 0xe00fe019;
1151 cpu->ccsidr[1] = 0x200fe019;
1152 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1153}
1154
1155#ifndef CONFIG_USER_ONLY
1156static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1157{
1158
1159
1160
1161 return ((smp_cpus - 1) << 24) | (1 << 23);
1162}
1163#endif
1164
1165static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1166#ifndef CONFIG_USER_ONLY
1167 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1168 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1169 .writefn = arm_cp_write_ignore, },
1170#endif
1171 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1172 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1173 REGINFO_SENTINEL
1174};
1175
1176static void cortex_a7_initfn(Object *obj)
1177{
1178 ARMCPU *cpu = ARM_CPU(obj);
1179
1180 cpu->dtb_compatible = "arm,cortex-a7";
1181 set_feature(&cpu->env, ARM_FEATURE_V7);
1182 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1183 set_feature(&cpu->env, ARM_FEATURE_NEON);
1184 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1185 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1186 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1187 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1188 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1189 set_feature(&cpu->env, ARM_FEATURE_LPAE);
1190 set_feature(&cpu->env, ARM_FEATURE_EL3);
1191 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1192 cpu->midr = 0x410fc075;
1193 cpu->reset_fpsid = 0x41023075;
1194 cpu->mvfr0 = 0x10110222;
1195 cpu->mvfr1 = 0x11111111;
1196 cpu->ctr = 0x84448003;
1197 cpu->reset_sctlr = 0x00c50078;
1198 cpu->id_pfr0 = 0x00001131;
1199 cpu->id_pfr1 = 0x00011011;
1200 cpu->id_dfr0 = 0x02010555;
1201 cpu->pmceid0 = 0x00000000;
1202 cpu->pmceid1 = 0x00000000;
1203 cpu->id_afr0 = 0x00000000;
1204 cpu->id_mmfr0 = 0x10101105;
1205 cpu->id_mmfr1 = 0x40000000;
1206 cpu->id_mmfr2 = 0x01240000;
1207 cpu->id_mmfr3 = 0x02102211;
1208 cpu->id_isar0 = 0x01101110;
1209 cpu->id_isar1 = 0x13112111;
1210 cpu->id_isar2 = 0x21232041;
1211 cpu->id_isar3 = 0x11112131;
1212 cpu->id_isar4 = 0x10011142;
1213 cpu->dbgdidr = 0x3515f005;
1214 cpu->clidr = 0x0a200023;
1215 cpu->ccsidr[0] = 0x701fe00a;
1216 cpu->ccsidr[1] = 0x201fe00a;
1217 cpu->ccsidr[2] = 0x711fe07a;
1218 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1219}
1220
1221static void cortex_a15_initfn(Object *obj)
1222{
1223 ARMCPU *cpu = ARM_CPU(obj);
1224
1225 cpu->dtb_compatible = "arm,cortex-a15";
1226 set_feature(&cpu->env, ARM_FEATURE_V7);
1227 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1228 set_feature(&cpu->env, ARM_FEATURE_NEON);
1229 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1230 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1231 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1232 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1233 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1234 set_feature(&cpu->env, ARM_FEATURE_LPAE);
1235 set_feature(&cpu->env, ARM_FEATURE_EL3);
1236 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1237 cpu->midr = 0x412fc0f1;
1238 cpu->reset_fpsid = 0x410430f0;
1239 cpu->mvfr0 = 0x10110222;
1240 cpu->mvfr1 = 0x11111111;
1241 cpu->ctr = 0x8444c004;
1242 cpu->reset_sctlr = 0x00c50078;
1243 cpu->id_pfr0 = 0x00001131;
1244 cpu->id_pfr1 = 0x00011011;
1245 cpu->id_dfr0 = 0x02010555;
1246 cpu->pmceid0 = 0x0000000;
1247 cpu->pmceid1 = 0x00000000;
1248 cpu->id_afr0 = 0x00000000;
1249 cpu->id_mmfr0 = 0x10201105;
1250 cpu->id_mmfr1 = 0x20000000;
1251 cpu->id_mmfr2 = 0x01240000;
1252 cpu->id_mmfr3 = 0x02102211;
1253 cpu->id_isar0 = 0x02101110;
1254 cpu->id_isar1 = 0x13112111;
1255 cpu->id_isar2 = 0x21232041;
1256 cpu->id_isar3 = 0x11112131;
1257 cpu->id_isar4 = 0x10011142;
1258 cpu->dbgdidr = 0x3515f021;
1259 cpu->clidr = 0x0a200023;
1260 cpu->ccsidr[0] = 0x701fe00a;
1261 cpu->ccsidr[1] = 0x201fe00a;
1262 cpu->ccsidr[2] = 0x711fe07a;
1263 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1264}
1265
1266static void ti925t_initfn(Object *obj)
1267{
1268 ARMCPU *cpu = ARM_CPU(obj);
1269 set_feature(&cpu->env, ARM_FEATURE_V4T);
1270 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1271 cpu->midr = ARM_CPUID_TI925T;
1272 cpu->ctr = 0x5109149;
1273 cpu->reset_sctlr = 0x00000070;
1274}
1275
1276static void sa1100_initfn(Object *obj)
1277{
1278 ARMCPU *cpu = ARM_CPU(obj);
1279
1280 cpu->dtb_compatible = "intel,sa1100";
1281 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1282 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1283 cpu->midr = 0x4401A11B;
1284 cpu->reset_sctlr = 0x00000070;
1285}
1286
1287static void sa1110_initfn(Object *obj)
1288{
1289 ARMCPU *cpu = ARM_CPU(obj);
1290 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1291 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1292 cpu->midr = 0x6901B119;
1293 cpu->reset_sctlr = 0x00000070;
1294}
1295
1296static void pxa250_initfn(Object *obj)
1297{
1298 ARMCPU *cpu = ARM_CPU(obj);
1299
1300 cpu->dtb_compatible = "marvell,xscale";
1301 set_feature(&cpu->env, ARM_FEATURE_V5);
1302 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1303 cpu->midr = 0x69052100;
1304 cpu->ctr = 0xd172172;
1305 cpu->reset_sctlr = 0x00000078;
1306}
1307
1308static void pxa255_initfn(Object *obj)
1309{
1310 ARMCPU *cpu = ARM_CPU(obj);
1311
1312 cpu->dtb_compatible = "marvell,xscale";
1313 set_feature(&cpu->env, ARM_FEATURE_V5);
1314 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1315 cpu->midr = 0x69052d00;
1316 cpu->ctr = 0xd172172;
1317 cpu->reset_sctlr = 0x00000078;
1318}
1319
1320static void pxa260_initfn(Object *obj)
1321{
1322 ARMCPU *cpu = ARM_CPU(obj);
1323
1324 cpu->dtb_compatible = "marvell,xscale";
1325 set_feature(&cpu->env, ARM_FEATURE_V5);
1326 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1327 cpu->midr = 0x69052903;
1328 cpu->ctr = 0xd172172;
1329 cpu->reset_sctlr = 0x00000078;
1330}
1331
1332static void pxa261_initfn(Object *obj)
1333{
1334 ARMCPU *cpu = ARM_CPU(obj);
1335
1336 cpu->dtb_compatible = "marvell,xscale";
1337 set_feature(&cpu->env, ARM_FEATURE_V5);
1338 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1339 cpu->midr = 0x69052d05;
1340 cpu->ctr = 0xd172172;
1341 cpu->reset_sctlr = 0x00000078;
1342}
1343
1344static void pxa262_initfn(Object *obj)
1345{
1346 ARMCPU *cpu = ARM_CPU(obj);
1347
1348 cpu->dtb_compatible = "marvell,xscale";
1349 set_feature(&cpu->env, ARM_FEATURE_V5);
1350 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1351 cpu->midr = 0x69052d06;
1352 cpu->ctr = 0xd172172;
1353 cpu->reset_sctlr = 0x00000078;
1354}
1355
1356static void pxa270a0_initfn(Object *obj)
1357{
1358 ARMCPU *cpu = ARM_CPU(obj);
1359
1360 cpu->dtb_compatible = "marvell,xscale";
1361 set_feature(&cpu->env, ARM_FEATURE_V5);
1362 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1363 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1364 cpu->midr = 0x69054110;
1365 cpu->ctr = 0xd172172;
1366 cpu->reset_sctlr = 0x00000078;
1367}
1368
1369static void pxa270a1_initfn(Object *obj)
1370{
1371 ARMCPU *cpu = ARM_CPU(obj);
1372
1373 cpu->dtb_compatible = "marvell,xscale";
1374 set_feature(&cpu->env, ARM_FEATURE_V5);
1375 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1376 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1377 cpu->midr = 0x69054111;
1378 cpu->ctr = 0xd172172;
1379 cpu->reset_sctlr = 0x00000078;
1380}
1381
1382static void pxa270b0_initfn(Object *obj)
1383{
1384 ARMCPU *cpu = ARM_CPU(obj);
1385
1386 cpu->dtb_compatible = "marvell,xscale";
1387 set_feature(&cpu->env, ARM_FEATURE_V5);
1388 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1389 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1390 cpu->midr = 0x69054112;
1391 cpu->ctr = 0xd172172;
1392 cpu->reset_sctlr = 0x00000078;
1393}
1394
1395static void pxa270b1_initfn(Object *obj)
1396{
1397 ARMCPU *cpu = ARM_CPU(obj);
1398
1399 cpu->dtb_compatible = "marvell,xscale";
1400 set_feature(&cpu->env, ARM_FEATURE_V5);
1401 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1402 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1403 cpu->midr = 0x69054113;
1404 cpu->ctr = 0xd172172;
1405 cpu->reset_sctlr = 0x00000078;
1406}
1407
1408static void pxa270c0_initfn(Object *obj)
1409{
1410 ARMCPU *cpu = ARM_CPU(obj);
1411
1412 cpu->dtb_compatible = "marvell,xscale";
1413 set_feature(&cpu->env, ARM_FEATURE_V5);
1414 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1415 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1416 cpu->midr = 0x69054114;
1417 cpu->ctr = 0xd172172;
1418 cpu->reset_sctlr = 0x00000078;
1419}
1420
1421static void pxa270c5_initfn(Object *obj)
1422{
1423 ARMCPU *cpu = ARM_CPU(obj);
1424
1425 cpu->dtb_compatible = "marvell,xscale";
1426 set_feature(&cpu->env, ARM_FEATURE_V5);
1427 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1428 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1429 cpu->midr = 0x69054117;
1430 cpu->ctr = 0xd172172;
1431 cpu->reset_sctlr = 0x00000078;
1432}
1433
1434#ifdef CONFIG_USER_ONLY
1435static void arm_any_initfn(Object *obj)
1436{
1437 ARMCPU *cpu = ARM_CPU(obj);
1438 set_feature(&cpu->env, ARM_FEATURE_V8);
1439 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1440 set_feature(&cpu->env, ARM_FEATURE_NEON);
1441 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1442 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1443 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1444 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1445 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1446 set_feature(&cpu->env, ARM_FEATURE_CRC);
1447 cpu->midr = 0xffffffff;
1448}
1449#endif
1450
1451#endif
1452
1453typedef struct ARMCPUInfo {
1454 const char *name;
1455 void (*initfn)(Object *obj);
1456 void (*class_init)(ObjectClass *oc, void *data);
1457} ARMCPUInfo;
1458
1459static const ARMCPUInfo arm_cpus[] = {
1460#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1461 { .name = "arm926", .initfn = arm926_initfn },
1462 { .name = "arm946", .initfn = arm946_initfn },
1463 { .name = "arm1026", .initfn = arm1026_initfn },
1464
1465
1466
1467
1468 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1469 { .name = "arm1136", .initfn = arm1136_initfn },
1470 { .name = "arm1176", .initfn = arm1176_initfn },
1471 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1472 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1473 .class_init = arm_v7m_class_init },
1474 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1475 .class_init = arm_v7m_class_init },
1476 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1477 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
1478 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1479 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1480 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1481 { .name = "ti925t", .initfn = ti925t_initfn },
1482 { .name = "sa1100", .initfn = sa1100_initfn },
1483 { .name = "sa1110", .initfn = sa1110_initfn },
1484 { .name = "pxa250", .initfn = pxa250_initfn },
1485 { .name = "pxa255", .initfn = pxa255_initfn },
1486 { .name = "pxa260", .initfn = pxa260_initfn },
1487 { .name = "pxa261", .initfn = pxa261_initfn },
1488 { .name = "pxa262", .initfn = pxa262_initfn },
1489
1490 { .name = "pxa270", .initfn = pxa270a0_initfn },
1491 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1492 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1493 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1494 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1495 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1496 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1497#ifdef CONFIG_USER_ONLY
1498 { .name = "any", .initfn = arm_any_initfn },
1499#endif
1500#endif
1501 { .name = NULL }
1502};
1503
1504static Property arm_cpu_properties[] = {
1505 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1506 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1507 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1508 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1509 mp_affinity, ARM64_AFFINITY_INVALID),
1510 DEFINE_PROP_END_OF_LIST()
1511};
1512
1513#ifdef CONFIG_USER_ONLY
1514static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1515 int mmu_idx)
1516{
1517 ARMCPU *cpu = ARM_CPU(cs);
1518 CPUARMState *env = &cpu->env;
1519
1520 env->exception.vaddress = address;
1521 if (rw == 2) {
1522 cs->exception_index = EXCP_PREFETCH_ABORT;
1523 } else {
1524 cs->exception_index = EXCP_DATA_ABORT;
1525 }
1526 return 1;
1527}
1528#endif
1529
1530static gchar *arm_gdb_arch_name(CPUState *cs)
1531{
1532 ARMCPU *cpu = ARM_CPU(cs);
1533 CPUARMState *env = &cpu->env;
1534
1535 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1536 return g_strdup("iwmmxt");
1537 }
1538 return g_strdup("arm");
1539}
1540
1541static void arm_cpu_class_init(ObjectClass *oc, void *data)
1542{
1543 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1544 CPUClass *cc = CPU_CLASS(acc);
1545 DeviceClass *dc = DEVICE_CLASS(oc);
1546
1547 acc->parent_realize = dc->realize;
1548 dc->realize = arm_cpu_realizefn;
1549 dc->props = arm_cpu_properties;
1550
1551 acc->parent_reset = cc->reset;
1552 cc->reset = arm_cpu_reset;
1553
1554 cc->class_by_name = arm_cpu_class_by_name;
1555 cc->has_work = arm_cpu_has_work;
1556 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1557 cc->dump_state = arm_cpu_dump_state;
1558 cc->set_pc = arm_cpu_set_pc;
1559 cc->gdb_read_register = arm_cpu_gdb_read_register;
1560 cc->gdb_write_register = arm_cpu_gdb_write_register;
1561#ifdef CONFIG_USER_ONLY
1562 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1563#else
1564 cc->do_interrupt = arm_cpu_do_interrupt;
1565 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1566 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1567 cc->asidx_from_attrs = arm_asidx_from_attrs;
1568 cc->vmsd = &vmstate_arm_cpu;
1569 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1570 cc->write_elf64_note = arm_cpu_write_elf64_note;
1571 cc->write_elf32_note = arm_cpu_write_elf32_note;
1572#endif
1573 cc->gdb_num_core_regs = 26;
1574 cc->gdb_core_xml_file = "arm-core.xml";
1575 cc->gdb_arch_name = arm_gdb_arch_name;
1576 cc->gdb_stop_before_watchpoint = true;
1577 cc->debug_excp_handler = arm_debug_excp_handler;
1578 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1579
1580 cc->disas_set_info = arm_disas_set_info;
1581}
1582
1583static void cpu_register(const ARMCPUInfo *info)
1584{
1585 TypeInfo type_info = {
1586 .parent = TYPE_ARM_CPU,
1587 .instance_size = sizeof(ARMCPU),
1588 .instance_init = info->initfn,
1589 .class_size = sizeof(ARMCPUClass),
1590 .class_init = info->class_init,
1591 };
1592
1593 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1594 type_register(&type_info);
1595 g_free((void *)type_info.name);
1596}
1597
1598static const TypeInfo arm_cpu_type_info = {
1599 .name = TYPE_ARM_CPU,
1600 .parent = TYPE_CPU,
1601 .instance_size = sizeof(ARMCPU),
1602 .instance_init = arm_cpu_initfn,
1603 .instance_post_init = arm_cpu_post_init,
1604 .instance_finalize = arm_cpu_finalizefn,
1605 .abstract = true,
1606 .class_size = sizeof(ARMCPUClass),
1607 .class_init = arm_cpu_class_init,
1608};
1609
1610static void arm_cpu_register_types(void)
1611{
1612 const ARMCPUInfo *info = arm_cpus;
1613
1614 type_register_static(&arm_cpu_type_info);
1615
1616 while (info->name) {
1617 cpu_register(info);
1618 info++;
1619 }
1620}
1621
1622type_init(arm_cpu_register_types)
1623