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20#ifndef ARM_CPU_H
21#define ARM_CPU_H
22
23#include "kvm-consts.h"
24
25#if defined(TARGET_AARCH64)
26
27# define TARGET_LONG_BITS 64
28#else
29# define TARGET_LONG_BITS 32
30#endif
31
32#define CPUArchState struct CPUARMState
33
34#include "qemu-common.h"
35#include "cpu-qom.h"
36#include "exec/cpu-defs.h"
37
38#include "fpu/softfloat.h"
39
40#define EXCP_UDEF 1
41#define EXCP_SWI 2
42#define EXCP_PREFETCH_ABORT 3
43#define EXCP_DATA_ABORT 4
44#define EXCP_IRQ 5
45#define EXCP_FIQ 6
46#define EXCP_BKPT 7
47#define EXCP_EXCEPTION_EXIT 8
48#define EXCP_KERNEL_TRAP 9
49#define EXCP_HVC 11
50#define EXCP_HYP_TRAP 12
51#define EXCP_SMC 13
52#define EXCP_VIRQ 14
53#define EXCP_VFIQ 15
54#define EXCP_SEMIHOST 16
55
56#define ARMV7M_EXCP_RESET 1
57#define ARMV7M_EXCP_NMI 2
58#define ARMV7M_EXCP_HARD 3
59#define ARMV7M_EXCP_MEM 4
60#define ARMV7M_EXCP_BUS 5
61#define ARMV7M_EXCP_USAGE 6
62#define ARMV7M_EXCP_SVC 11
63#define ARMV7M_EXCP_DEBUG 12
64#define ARMV7M_EXCP_PENDSV 14
65#define ARMV7M_EXCP_SYSTICK 15
66
67
68#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
69#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
70#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
71
72
73
74
75
76
77
78#ifdef HOST_WORDS_BIGENDIAN
79#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
80#define offsetofhigh32(S, M) offsetof(S, M)
81#else
82#define offsetoflow32(S, M) offsetof(S, M)
83#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
84#endif
85
86
87#define ARM_CPU_IRQ 0
88#define ARM_CPU_FIQ 1
89#define ARM_CPU_VIRQ 2
90#define ARM_CPU_VFIQ 3
91
92#define NB_MMU_MODES 7
93
94
95
96
97#define TARGET_INSN_START_EXTRA_WORDS 2
98
99
100
101
102
103
104#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
105#define ARM_INSN_START_WORD2_SHIFT 14
106
107
108
109
110
111
112
113
114
115
116typedef struct ARMGenericTimer {
117 uint64_t cval;
118 uint64_t ctl;
119} ARMGenericTimer;
120
121#define GTIMER_PHYS 0
122#define GTIMER_VIRT 1
123#define GTIMER_HYP 2
124#define GTIMER_SEC 3
125#define NUM_GTIMERS 4
126
127typedef struct {
128 uint64_t raw_tcr;
129 uint32_t mask;
130 uint32_t base_mask;
131} TCR;
132
133typedef struct CPUARMState {
134
135 uint32_t regs[16];
136
137
138
139
140
141
142 uint64_t xregs[32];
143 uint64_t pc;
144
145
146
147
148
149
150
151
152
153
154
155 uint32_t pstate;
156 uint32_t aarch64;
157
158
159
160
161 uint32_t uncached_cpsr;
162 uint32_t spsr;
163
164
165 uint64_t banked_spsr[8];
166 uint32_t banked_r13[8];
167 uint32_t banked_r14[8];
168
169
170 uint32_t usr_regs[5];
171 uint32_t fiq_regs[5];
172
173
174 uint32_t CF;
175 uint32_t VF;
176 uint32_t NF;
177 uint32_t ZF;
178 uint32_t QF;
179 uint32_t GE;
180 uint32_t thumb;
181 uint32_t condexec_bits;
182 uint64_t daif;
183
184 uint64_t elr_el[4];
185 uint64_t sp_el[4];
186
187
188 struct {
189 uint32_t c0_cpuid;
190 union {
191 struct {
192 uint64_t _unused_csselr0;
193 uint64_t csselr_ns;
194 uint64_t _unused_csselr1;
195 uint64_t csselr_s;
196 };
197 uint64_t csselr_el[4];
198 };
199 union {
200 struct {
201 uint64_t _unused_sctlr;
202 uint64_t sctlr_ns;
203 uint64_t hsctlr;
204 uint64_t sctlr_s;
205 };
206 uint64_t sctlr_el[4];
207 };
208 uint64_t cpacr_el1;
209 uint64_t cptr_el[4];
210 uint32_t c1_xscaleauxcr;
211 uint64_t sder;
212 uint32_t nsacr;
213 union {
214 struct {
215 uint64_t _unused_ttbr0_0;
216 uint64_t ttbr0_ns;
217 uint64_t _unused_ttbr0_1;
218 uint64_t ttbr0_s;
219 };
220 uint64_t ttbr0_el[4];
221 };
222 union {
223 struct {
224 uint64_t _unused_ttbr1_0;
225 uint64_t ttbr1_ns;
226 uint64_t _unused_ttbr1_1;
227 uint64_t ttbr1_s;
228 };
229 uint64_t ttbr1_el[4];
230 };
231 uint64_t vttbr_el2;
232
233 TCR tcr_el[4];
234 TCR vtcr_el2;
235 uint32_t c2_data;
236 uint32_t c2_insn;
237 union {
238
239
240 struct {
241 uint64_t dacr_ns;
242 uint64_t dacr_s;
243 };
244 struct {
245 uint64_t dacr32_el2;
246 };
247 };
248 uint32_t pmsav5_data_ap;
249 uint32_t pmsav5_insn_ap;
250 uint64_t hcr_el2;
251 uint64_t scr_el3;
252 union {
253 struct {
254 uint64_t ifsr_ns;
255 uint64_t ifsr_s;
256 };
257 struct {
258 uint64_t ifsr32_el2;
259 };
260 };
261 union {
262 struct {
263 uint64_t _unused_dfsr;
264 uint64_t dfsr_ns;
265 uint64_t hsr;
266 uint64_t dfsr_s;
267 };
268 uint64_t esr_el[4];
269 };
270 uint32_t c6_region[8];
271 union {
272 struct {
273 uint64_t _unused_far0;
274#ifdef HOST_WORDS_BIGENDIAN
275 uint32_t ifar_ns;
276 uint32_t dfar_ns;
277 uint32_t ifar_s;
278 uint32_t dfar_s;
279#else
280 uint32_t dfar_ns;
281 uint32_t ifar_ns;
282 uint32_t dfar_s;
283 uint32_t ifar_s;
284#endif
285 uint64_t _unused_far3;
286 };
287 uint64_t far_el[4];
288 };
289 uint64_t hpfar_el2;
290 uint64_t hstr_el2;
291 union {
292 struct {
293 uint64_t _unused_par_0;
294 uint64_t par_ns;
295 uint64_t _unused_par_1;
296 uint64_t par_s;
297 };
298 uint64_t par_el[4];
299 };
300
301 uint32_t c6_rgnr;
302
303 uint32_t c9_insn;
304 uint32_t c9_data;
305 uint64_t c9_pmcr;
306 uint64_t c9_pmcnten;
307 uint32_t c9_pmovsr;
308 uint32_t c9_pmxevtyper;
309 uint32_t c9_pmuserenr;
310 uint32_t c9_pminten;
311 union {
312 struct {
313#ifdef HOST_WORDS_BIGENDIAN
314 uint64_t _unused_mair_0;
315 uint32_t mair1_ns;
316 uint32_t mair0_ns;
317 uint64_t _unused_mair_1;
318 uint32_t mair1_s;
319 uint32_t mair0_s;
320#else
321 uint64_t _unused_mair_0;
322 uint32_t mair0_ns;
323 uint32_t mair1_ns;
324 uint64_t _unused_mair_1;
325 uint32_t mair0_s;
326 uint32_t mair1_s;
327#endif
328 };
329 uint64_t mair_el[4];
330 };
331 union {
332 struct {
333 uint64_t _unused_vbar;
334 uint64_t vbar_ns;
335 uint64_t hvbar;
336 uint64_t vbar_s;
337 };
338 uint64_t vbar_el[4];
339 };
340 uint32_t mvbar;
341 struct {
342 uint32_t fcseidr_ns;
343 uint32_t fcseidr_s;
344 };
345 union {
346 struct {
347 uint64_t _unused_contextidr_0;
348 uint64_t contextidr_ns;
349 uint64_t _unused_contextidr_1;
350 uint64_t contextidr_s;
351 };
352 uint64_t contextidr_el[4];
353 };
354 union {
355 struct {
356 uint64_t tpidrurw_ns;
357 uint64_t tpidrprw_ns;
358 uint64_t htpidr;
359 uint64_t _tpidr_el3;
360 };
361 uint64_t tpidr_el[4];
362 };
363
364 uint64_t tpidrurw_s;
365 uint64_t tpidrprw_s;
366 uint64_t tpidruro_s;
367
368 union {
369 uint64_t tpidruro_ns;
370 uint64_t tpidrro_el[1];
371 };
372 uint64_t c14_cntfrq;
373 uint64_t c14_cntkctl;
374 uint32_t cnthctl_el2;
375 uint64_t cntvoff_el2;
376 ARMGenericTimer c14_timer[NUM_GTIMERS];
377 uint32_t c15_cpar;
378 uint32_t c15_ticonfig;
379 uint32_t c15_i_max;
380 uint32_t c15_i_min;
381 uint32_t c15_threadid;
382 uint32_t c15_config_base_address;
383 uint32_t c15_diagnostic;
384 uint32_t c15_power_diagnostic;
385 uint32_t c15_power_control;
386 uint64_t dbgbvr[16];
387 uint64_t dbgbcr[16];
388 uint64_t dbgwvr[16];
389 uint64_t dbgwcr[16];
390 uint64_t mdscr_el1;
391 uint64_t oslsr_el1;
392 uint64_t mdcr_el2;
393 uint64_t mdcr_el3;
394
395
396
397 uint64_t c15_ccnt;
398 uint64_t pmccfiltr_el0;
399 uint64_t vpidr_el2;
400 uint64_t vmpidr_el2;
401 } cp15;
402
403 struct {
404 uint32_t other_sp;
405 uint32_t vecbase;
406 uint32_t basepri;
407 uint32_t control;
408 int current_sp;
409 int exception;
410 } v7m;
411
412
413
414
415
416
417
418 struct {
419 uint32_t syndrome;
420 uint32_t fsr;
421 uint64_t vaddress;
422 uint32_t target_el;
423
424
425
426 } exception;
427
428
429 uint32_t teecr;
430 uint32_t teehbr;
431
432
433 struct {
434
435
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439
440
441
442
443
444
445
446
447
448
449 float64 regs[64];
450
451 uint32_t xregs[16];
452
453 int vec_len;
454 int vec_stride;
455
456
457 uint32_t scratch[8];
458
459
460
461
462
463
464
465
466
467
468
469
470
471 float_status fp_status;
472 float_status standard_fp_status;
473 } vfp;
474 uint64_t exclusive_addr;
475 uint64_t exclusive_val;
476 uint64_t exclusive_high;
477
478
479 struct {
480 uint64_t regs[16];
481 uint64_t val;
482
483 uint32_t cregs[16];
484 } iwmmxt;
485
486#if defined(CONFIG_USER_ONLY)
487
488 int eabi;
489#endif
490
491 struct CPUBreakpoint *cpu_breakpoint[16];
492 struct CPUWatchpoint *cpu_watchpoint[16];
493
494 CPU_COMMON
495
496
497
498
499 uint64_t features;
500
501
502 struct {
503 uint32_t *drbar;
504 uint32_t *drsr;
505 uint32_t *dracr;
506 } pmsav7;
507
508 void *nvic;
509 const struct arm_boot_info *boot_info;
510} CPUARMState;
511
512
513
514
515
516
517typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
518
519
520
521
522
523
524
525struct ARMCPU {
526
527 CPUState parent_obj;
528
529
530 CPUARMState env;
531
532
533 GHashTable *cp_regs;
534
535
536
537
538
539
540
541 uint64_t *cpreg_indexes;
542
543 uint64_t *cpreg_values;
544
545 int32_t cpreg_array_len;
546
547
548
549
550 uint64_t *cpreg_vmstate_indexes;
551 uint64_t *cpreg_vmstate_values;
552 int32_t cpreg_vmstate_array_len;
553
554
555 QEMUTimer *gt_timer[NUM_GTIMERS];
556
557 qemu_irq gt_timer_outputs[NUM_GTIMERS];
558
559
560 MemoryRegion *secure_memory;
561
562
563 const char *dtb_compatible;
564
565
566
567
568
569 uint32_t psci_version;
570
571
572 bool start_powered_off;
573
574 bool powered_off;
575
576 bool has_el3;
577
578 bool has_pmu;
579
580
581 bool has_mpu;
582
583 uint32_t pmsav7_dregion;
584
585
586
587
588 uint32_t psci_conduit;
589
590
591
592
593 uint32_t kvm_target;
594
595
596 uint32_t kvm_init_features[7];
597
598
599 bool mp_is_up;
600
601
602
603
604
605
606
607
608
609
610
611 uint32_t midr;
612 uint32_t revidr;
613 uint32_t reset_fpsid;
614 uint32_t mvfr0;
615 uint32_t mvfr1;
616 uint32_t mvfr2;
617 uint32_t ctr;
618 uint32_t reset_sctlr;
619 uint32_t id_pfr0;
620 uint32_t id_pfr1;
621 uint32_t id_dfr0;
622 uint32_t pmceid0;
623 uint32_t pmceid1;
624 uint32_t id_afr0;
625 uint32_t id_mmfr0;
626 uint32_t id_mmfr1;
627 uint32_t id_mmfr2;
628 uint32_t id_mmfr3;
629 uint32_t id_mmfr4;
630 uint32_t id_isar0;
631 uint32_t id_isar1;
632 uint32_t id_isar2;
633 uint32_t id_isar3;
634 uint32_t id_isar4;
635 uint32_t id_isar5;
636 uint64_t id_aa64pfr0;
637 uint64_t id_aa64pfr1;
638 uint64_t id_aa64dfr0;
639 uint64_t id_aa64dfr1;
640 uint64_t id_aa64afr0;
641 uint64_t id_aa64afr1;
642 uint64_t id_aa64isar0;
643 uint64_t id_aa64isar1;
644 uint64_t id_aa64mmfr0;
645 uint64_t id_aa64mmfr1;
646 uint32_t dbgdidr;
647 uint32_t clidr;
648 uint64_t mp_affinity;
649
650
651
652 uint32_t ccsidr[16];
653 uint64_t reset_cbar;
654 uint32_t reset_auxcr;
655 bool reset_hivecs;
656
657 uint32_t dcz_blocksize;
658 uint64_t rvbar;
659
660 ARMELChangeHook *el_change_hook;
661 void *el_change_hook_opaque;
662};
663
664static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
665{
666 return container_of(env, ARMCPU, env);
667}
668
669#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
670
671#define ENV_OFFSET offsetof(ARMCPU, env)
672
673#ifndef CONFIG_USER_ONLY
674extern const struct VMStateDescription vmstate_arm_cpu;
675#endif
676
677void arm_cpu_do_interrupt(CPUState *cpu);
678void arm_v7m_cpu_do_interrupt(CPUState *cpu);
679bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
680
681void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
682 int flags);
683
684hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
685 MemTxAttrs *attrs);
686
687int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
688int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
689
690int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
691 int cpuid, void *opaque);
692int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
693 int cpuid, void *opaque);
694
695#ifdef TARGET_AARCH64
696int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
697int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
698#endif
699
700ARMCPU *cpu_arm_init(const char *cpu_model);
701target_ulong do_arm_semihosting(CPUARMState *env);
702void aarch64_sync_32_to_64(CPUARMState *env);
703void aarch64_sync_64_to_32(CPUARMState *env);
704
705static inline bool is_a64(CPUARMState *env)
706{
707 return env->aarch64;
708}
709
710
711
712
713int cpu_arm_signal_handler(int host_signum, void *pinfo,
714 void *puc);
715
716
717
718
719
720
721
722
723
724
725void pmccntr_sync(CPUARMState *env);
726
727
728
729
730
731
732
733#define SCTLR_M (1U << 0)
734#define SCTLR_A (1U << 1)
735#define SCTLR_C (1U << 2)
736#define SCTLR_W (1U << 3)
737#define SCTLR_SA (1U << 3)
738#define SCTLR_P (1U << 4)
739#define SCTLR_SA0 (1U << 4)
740#define SCTLR_D (1U << 5)
741#define SCTLR_CP15BEN (1U << 5)
742#define SCTLR_L (1U << 6)
743#define SCTLR_B (1U << 7)
744#define SCTLR_ITD (1U << 7)
745#define SCTLR_S (1U << 8)
746#define SCTLR_SED (1U << 8)
747#define SCTLR_R (1U << 9)
748#define SCTLR_UMA (1U << 9)
749#define SCTLR_F (1U << 10)
750#define SCTLR_SW (1U << 10)
751#define SCTLR_Z (1U << 11)
752#define SCTLR_I (1U << 12)
753#define SCTLR_V (1U << 13)
754#define SCTLR_RR (1U << 14)
755#define SCTLR_DZE (1U << 14)
756#define SCTLR_L4 (1U << 15)
757#define SCTLR_UCT (1U << 15)
758#define SCTLR_DT (1U << 16)
759#define SCTLR_nTWI (1U << 16)
760#define SCTLR_HA (1U << 17)
761#define SCTLR_BR (1U << 17)
762#define SCTLR_IT (1U << 18)
763#define SCTLR_nTWE (1U << 18)
764#define SCTLR_WXN (1U << 19)
765#define SCTLR_ST (1U << 20)
766#define SCTLR_UWXN (1U << 20)
767#define SCTLR_FI (1U << 21)
768#define SCTLR_U (1U << 22)
769#define SCTLR_XP (1U << 23)
770#define SCTLR_VE (1U << 24)
771#define SCTLR_E0E (1U << 24)
772#define SCTLR_EE (1U << 25)
773#define SCTLR_L2 (1U << 26)
774#define SCTLR_UCI (1U << 26)
775#define SCTLR_NMFI (1U << 27)
776#define SCTLR_TRE (1U << 28)
777#define SCTLR_AFE (1U << 29)
778#define SCTLR_TE (1U << 30)
779
780#define CPTR_TCPAC (1U << 31)
781#define CPTR_TTA (1U << 20)
782#define CPTR_TFP (1U << 10)
783
784#define MDCR_EPMAD (1U << 21)
785#define MDCR_EDAD (1U << 20)
786#define MDCR_SPME (1U << 17)
787#define MDCR_SDD (1U << 16)
788#define MDCR_SPD (3U << 14)
789#define MDCR_TDRA (1U << 11)
790#define MDCR_TDOSA (1U << 10)
791#define MDCR_TDA (1U << 9)
792#define MDCR_TDE (1U << 8)
793#define MDCR_HPME (1U << 7)
794#define MDCR_TPM (1U << 6)
795#define MDCR_TPMCR (1U << 5)
796
797
798#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
799
800#define CPSR_M (0x1fU)
801#define CPSR_T (1U << 5)
802#define CPSR_F (1U << 6)
803#define CPSR_I (1U << 7)
804#define CPSR_A (1U << 8)
805#define CPSR_E (1U << 9)
806#define CPSR_IT_2_7 (0xfc00U)
807#define CPSR_GE (0xfU << 16)
808#define CPSR_IL (1U << 20)
809
810
811
812
813
814#define CPSR_RESERVED (0x7U << 21)
815#define CPSR_J (1U << 24)
816#define CPSR_IT_0_1 (3U << 25)
817#define CPSR_Q (1U << 27)
818#define CPSR_V (1U << 28)
819#define CPSR_C (1U << 29)
820#define CPSR_Z (1U << 30)
821#define CPSR_N (1U << 31)
822#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
823#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
824
825#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
826#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
827 | CPSR_NZCV)
828
829#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
830
831#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
832
833#define CPSR_ERET_MASK (~CPSR_RESERVED)
834
835#define TTBCR_N (7U << 0)
836#define TTBCR_T0SZ (7U << 0)
837#define TTBCR_PD0 (1U << 4)
838#define TTBCR_PD1 (1U << 5)
839#define TTBCR_EPD0 (1U << 7)
840#define TTBCR_IRGN0 (3U << 8)
841#define TTBCR_ORGN0 (3U << 10)
842#define TTBCR_SH0 (3U << 12)
843#define TTBCR_T1SZ (3U << 16)
844#define TTBCR_A1 (1U << 22)
845#define TTBCR_EPD1 (1U << 23)
846#define TTBCR_IRGN1 (3U << 24)
847#define TTBCR_ORGN1 (3U << 26)
848#define TTBCR_SH1 (1U << 28)
849#define TTBCR_EAE (1U << 31)
850
851
852
853
854
855#define PSTATE_SP (1U)
856#define PSTATE_M (0xFU)
857#define PSTATE_nRW (1U << 4)
858#define PSTATE_F (1U << 6)
859#define PSTATE_I (1U << 7)
860#define PSTATE_A (1U << 8)
861#define PSTATE_D (1U << 9)
862#define PSTATE_IL (1U << 20)
863#define PSTATE_SS (1U << 21)
864#define PSTATE_V (1U << 28)
865#define PSTATE_C (1U << 29)
866#define PSTATE_Z (1U << 30)
867#define PSTATE_N (1U << 31)
868#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
869#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
870#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
871
872#define PSTATE_MODE_EL3h 13
873#define PSTATE_MODE_EL3t 12
874#define PSTATE_MODE_EL2h 9
875#define PSTATE_MODE_EL2t 8
876#define PSTATE_MODE_EL1h 5
877#define PSTATE_MODE_EL1t 4
878#define PSTATE_MODE_EL0t 0
879
880
881static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
882{
883 return (el << 2) | handler;
884}
885
886
887
888
889
890static inline uint32_t pstate_read(CPUARMState *env)
891{
892 int ZF;
893
894 ZF = (env->ZF == 0);
895 return (env->NF & 0x80000000) | (ZF << 30)
896 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
897 | env->pstate | env->daif;
898}
899
900static inline void pstate_write(CPUARMState *env, uint32_t val)
901{
902 env->ZF = (~val) & PSTATE_Z;
903 env->NF = val;
904 env->CF = (val >> 29) & 1;
905 env->VF = (val << 3) & 0x80000000;
906 env->daif = val & PSTATE_DAIF;
907 env->pstate = val & ~CACHED_PSTATE_BITS;
908}
909
910
911uint32_t cpsr_read(CPUARMState *env);
912
913typedef enum CPSRWriteType {
914 CPSRWriteByInstr = 0,
915 CPSRWriteExceptionReturn = 1,
916 CPSRWriteRaw = 2,
917 CPSRWriteByGDBStub = 3,
918} CPSRWriteType;
919
920
921void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
922 CPSRWriteType write_type);
923
924
925static inline uint32_t xpsr_read(CPUARMState *env)
926{
927 int ZF;
928 ZF = (env->ZF == 0);
929 return (env->NF & 0x80000000) | (ZF << 30)
930 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
931 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
932 | ((env->condexec_bits & 0xfc) << 8)
933 | env->v7m.exception;
934}
935
936
937static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
938{
939 if (mask & CPSR_NZCV) {
940 env->ZF = (~val) & CPSR_Z;
941 env->NF = val;
942 env->CF = (val >> 29) & 1;
943 env->VF = (val << 3) & 0x80000000;
944 }
945 if (mask & CPSR_Q)
946 env->QF = ((val & CPSR_Q) != 0);
947 if (mask & (1 << 24))
948 env->thumb = ((val & (1 << 24)) != 0);
949 if (mask & CPSR_IT_0_1) {
950 env->condexec_bits &= ~3;
951 env->condexec_bits |= (val >> 25) & 3;
952 }
953 if (mask & CPSR_IT_2_7) {
954 env->condexec_bits &= 3;
955 env->condexec_bits |= (val >> 8) & 0xfc;
956 }
957 if (mask & 0x1ff) {
958 env->v7m.exception = val & 0x1ff;
959 }
960}
961
962#define HCR_VM (1ULL << 0)
963#define HCR_SWIO (1ULL << 1)
964#define HCR_PTW (1ULL << 2)
965#define HCR_FMO (1ULL << 3)
966#define HCR_IMO (1ULL << 4)
967#define HCR_AMO (1ULL << 5)
968#define HCR_VF (1ULL << 6)
969#define HCR_VI (1ULL << 7)
970#define HCR_VSE (1ULL << 8)
971#define HCR_FB (1ULL << 9)
972#define HCR_BSU_MASK (3ULL << 10)
973#define HCR_DC (1ULL << 12)
974#define HCR_TWI (1ULL << 13)
975#define HCR_TWE (1ULL << 14)
976#define HCR_TID0 (1ULL << 15)
977#define HCR_TID1 (1ULL << 16)
978#define HCR_TID2 (1ULL << 17)
979#define HCR_TID3 (1ULL << 18)
980#define HCR_TSC (1ULL << 19)
981#define HCR_TIDCP (1ULL << 20)
982#define HCR_TACR (1ULL << 21)
983#define HCR_TSW (1ULL << 22)
984#define HCR_TPC (1ULL << 23)
985#define HCR_TPU (1ULL << 24)
986#define HCR_TTLB (1ULL << 25)
987#define HCR_TVM (1ULL << 26)
988#define HCR_TGE (1ULL << 27)
989#define HCR_TDZ (1ULL << 28)
990#define HCR_HCD (1ULL << 29)
991#define HCR_TRVM (1ULL << 30)
992#define HCR_RW (1ULL << 31)
993#define HCR_CD (1ULL << 32)
994#define HCR_ID (1ULL << 33)
995#define HCR_MASK ((1ULL << 34) - 1)
996
997#define SCR_NS (1U << 0)
998#define SCR_IRQ (1U << 1)
999#define SCR_FIQ (1U << 2)
1000#define SCR_EA (1U << 3)
1001#define SCR_FW (1U << 4)
1002#define SCR_AW (1U << 5)
1003#define SCR_NET (1U << 6)
1004#define SCR_SMD (1U << 7)
1005#define SCR_HCE (1U << 8)
1006#define SCR_SIF (1U << 9)
1007#define SCR_RW (1U << 10)
1008#define SCR_ST (1U << 11)
1009#define SCR_TWI (1U << 12)
1010#define SCR_TWE (1U << 13)
1011#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
1012#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
1013
1014
1015uint32_t vfp_get_fpscr(CPUARMState *env);
1016void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1017
1018
1019
1020
1021
1022#define FPSR_MASK 0xf800009f
1023#define FPCR_MASK 0x07f79f00
1024static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1025{
1026 return vfp_get_fpscr(env) & FPSR_MASK;
1027}
1028
1029static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1030{
1031 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1032 vfp_set_fpscr(env, new_fpscr);
1033}
1034
1035static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1036{
1037 return vfp_get_fpscr(env) & FPCR_MASK;
1038}
1039
1040static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1041{
1042 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1043 vfp_set_fpscr(env, new_fpscr);
1044}
1045
1046enum arm_cpu_mode {
1047 ARM_CPU_MODE_USR = 0x10,
1048 ARM_CPU_MODE_FIQ = 0x11,
1049 ARM_CPU_MODE_IRQ = 0x12,
1050 ARM_CPU_MODE_SVC = 0x13,
1051 ARM_CPU_MODE_MON = 0x16,
1052 ARM_CPU_MODE_ABT = 0x17,
1053 ARM_CPU_MODE_HYP = 0x1a,
1054 ARM_CPU_MODE_UND = 0x1b,
1055 ARM_CPU_MODE_SYS = 0x1f
1056};
1057
1058
1059#define ARM_VFP_FPSID 0
1060#define ARM_VFP_FPSCR 1
1061#define ARM_VFP_MVFR2 5
1062#define ARM_VFP_MVFR1 6
1063#define ARM_VFP_MVFR0 7
1064#define ARM_VFP_FPEXC 8
1065#define ARM_VFP_FPINST 9
1066#define ARM_VFP_FPINST2 10
1067
1068
1069#define ARM_IWMMXT_wCID 0
1070#define ARM_IWMMXT_wCon 1
1071#define ARM_IWMMXT_wCSSF 2
1072#define ARM_IWMMXT_wCASF 3
1073#define ARM_IWMMXT_wCGR0 8
1074#define ARM_IWMMXT_wCGR1 9
1075#define ARM_IWMMXT_wCGR2 10
1076#define ARM_IWMMXT_wCGR3 11
1077
1078
1079
1080
1081
1082enum arm_features {
1083 ARM_FEATURE_VFP,
1084 ARM_FEATURE_AUXCR,
1085 ARM_FEATURE_XSCALE,
1086 ARM_FEATURE_IWMMXT,
1087 ARM_FEATURE_V6,
1088 ARM_FEATURE_V6K,
1089 ARM_FEATURE_V7,
1090 ARM_FEATURE_THUMB2,
1091 ARM_FEATURE_MPU,
1092 ARM_FEATURE_VFP3,
1093 ARM_FEATURE_VFP_FP16,
1094 ARM_FEATURE_NEON,
1095 ARM_FEATURE_THUMB_DIV,
1096 ARM_FEATURE_M,
1097 ARM_FEATURE_OMAPCP,
1098 ARM_FEATURE_THUMB2EE,
1099 ARM_FEATURE_V7MP,
1100 ARM_FEATURE_V4T,
1101 ARM_FEATURE_V5,
1102 ARM_FEATURE_STRONGARM,
1103 ARM_FEATURE_VAPA,
1104 ARM_FEATURE_ARM_DIV,
1105 ARM_FEATURE_VFP4,
1106 ARM_FEATURE_GENERIC_TIMER,
1107 ARM_FEATURE_MVFR,
1108 ARM_FEATURE_DUMMY_C15_REGS,
1109 ARM_FEATURE_CACHE_TEST_CLEAN,
1110 ARM_FEATURE_CACHE_DIRTY_REG,
1111 ARM_FEATURE_CACHE_BLOCK_OPS,
1112 ARM_FEATURE_MPIDR,
1113 ARM_FEATURE_PXN,
1114 ARM_FEATURE_LPAE,
1115 ARM_FEATURE_V8,
1116 ARM_FEATURE_AARCH64,
1117 ARM_FEATURE_V8_AES,
1118 ARM_FEATURE_CBAR,
1119 ARM_FEATURE_CRC,
1120 ARM_FEATURE_CBAR_RO,
1121 ARM_FEATURE_EL2,
1122 ARM_FEATURE_EL3,
1123 ARM_FEATURE_V8_SHA1,
1124 ARM_FEATURE_V8_SHA256,
1125 ARM_FEATURE_V8_PMULL,
1126 ARM_FEATURE_THUMB_DSP,
1127 ARM_FEATURE_PMU,
1128};
1129
1130static inline int arm_feature(CPUARMState *env, int feature)
1131{
1132 return (env->features & (1ULL << feature)) != 0;
1133}
1134
1135#if !defined(CONFIG_USER_ONLY)
1136
1137
1138
1139
1140
1141
1142static inline bool arm_is_secure_below_el3(CPUARMState *env)
1143{
1144 if (arm_feature(env, ARM_FEATURE_EL3)) {
1145 return !(env->cp15.scr_el3 & SCR_NS);
1146 } else {
1147
1148
1149
1150 return false;
1151 }
1152}
1153
1154
1155static inline bool arm_is_el3_or_mon(CPUARMState *env)
1156{
1157 if (arm_feature(env, ARM_FEATURE_EL3)) {
1158 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
1159
1160 return true;
1161 } else if (!is_a64(env) &&
1162 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
1163
1164 return true;
1165 }
1166 }
1167 return false;
1168}
1169
1170
1171static inline bool arm_is_secure(CPUARMState *env)
1172{
1173 if (arm_is_el3_or_mon(env)) {
1174 return true;
1175 }
1176 return arm_is_secure_below_el3(env);
1177}
1178
1179#else
1180static inline bool arm_is_secure_below_el3(CPUARMState *env)
1181{
1182 return false;
1183}
1184
1185static inline bool arm_is_secure(CPUARMState *env)
1186{
1187 return false;
1188}
1189#endif
1190
1191
1192static inline bool arm_el_is_aa64(CPUARMState *env, int el)
1193{
1194
1195
1196
1197 assert(el >= 1 && el <= 3);
1198 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
1199
1200
1201
1202
1203
1204 if (el == 3) {
1205 return aa64;
1206 }
1207
1208 if (arm_feature(env, ARM_FEATURE_EL3)) {
1209 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
1210 }
1211
1212 if (el == 2) {
1213 return aa64;
1214 }
1215
1216 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
1217 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
1218 }
1219
1220 return aa64;
1221}
1222
1223
1224
1225
1226
1227
1228
1229
1230static inline bool access_secure_reg(CPUARMState *env)
1231{
1232 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
1233 !arm_el_is_aa64(env, 3) &&
1234 !(env->cp15.scr_el3 & SCR_NS));
1235
1236 return ret;
1237}
1238
1239
1240#define A32_BANKED_REG_GET(_env, _regname, _secure) \
1241 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1242
1243#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1244 do { \
1245 if (_secure) { \
1246 (_env)->cp15._regname##_s = (_val); \
1247 } else { \
1248 (_env)->cp15._regname##_ns = (_val); \
1249 } \
1250 } while (0)
1251
1252
1253
1254
1255
1256
1257#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1258 A32_BANKED_REG_GET((_env), _regname, \
1259 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1260
1261#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1262 A32_BANKED_REG_SET((_env), _regname, \
1263 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1264 (_val))
1265
1266void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1267uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1268 uint32_t cur_el, bool secure);
1269
1270
1271void armv7m_nvic_set_pending(void *opaque, int irq);
1272int armv7m_nvic_acknowledge_irq(void *opaque);
1273void armv7m_nvic_complete_irq(void *opaque, int irq);
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
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1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301#define CP_REG_AA64_SHIFT 28
1302#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1303
1304
1305
1306
1307
1308#define CP_REG_NS_SHIFT 29
1309#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1310
1311#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1312 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1313 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1314
1315#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1316 (CP_REG_AA64_MASK | \
1317 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1318 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1319 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1320 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1321 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1322 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1323
1324
1325
1326
1327static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
1328{
1329 uint32_t cpregid = kvmid;
1330 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
1331 cpregid |= CP_REG_AA64_MASK;
1332 } else {
1333 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
1334 cpregid |= (1 << 15);
1335 }
1336
1337
1338
1339
1340 cpregid |= 1 << CP_REG_NS_SHIFT;
1341 }
1342 return cpregid;
1343}
1344
1345
1346
1347
1348static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
1349{
1350 uint64_t kvmid;
1351
1352 if (cpregid & CP_REG_AA64_MASK) {
1353 kvmid = cpregid & ~CP_REG_AA64_MASK;
1354 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
1355 } else {
1356 kvmid = cpregid & ~(1 << 15);
1357 if (cpregid & (1 << 15)) {
1358 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
1359 } else {
1360 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
1361 }
1362 }
1363 return kvmid;
1364}
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388#define ARM_CP_SPECIAL 1
1389#define ARM_CP_CONST 2
1390#define ARM_CP_64BIT 4
1391#define ARM_CP_SUPPRESS_TB_END 8
1392#define ARM_CP_OVERRIDE 16
1393#define ARM_CP_ALIAS 32
1394#define ARM_CP_IO 64
1395#define ARM_CP_NO_RAW 128
1396#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1397#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1398#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1399#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1400#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1401#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1402
1403#define ARM_CP_SENTINEL 0xffff
1404
1405#define ARM_CP_FLAG_MASK 0xff
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416enum {
1417 ARM_CP_STATE_AA32 = 0,
1418 ARM_CP_STATE_AA64 = 1,
1419 ARM_CP_STATE_BOTH = 2,
1420};
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432enum {
1433 ARM_CP_SECSTATE_S = (1 << 0),
1434 ARM_CP_SECSTATE_NS = (1 << 1),
1435};
1436
1437
1438
1439
1440
1441static inline bool cptype_valid(int cptype)
1442{
1443 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
1444 || ((cptype & ARM_CP_SPECIAL) &&
1445 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
1446}
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465#define PL3_R 0x80
1466#define PL3_W 0x40
1467#define PL2_R (0x20 | PL3_R)
1468#define PL2_W (0x10 | PL3_W)
1469#define PL1_R (0x08 | PL2_R)
1470#define PL1_W (0x04 | PL2_W)
1471#define PL0_R (0x02 | PL1_R)
1472#define PL0_W (0x01 | PL1_W)
1473
1474#define PL3_RW (PL3_R | PL3_W)
1475#define PL2_RW (PL2_R | PL2_W)
1476#define PL1_RW (PL1_R | PL1_W)
1477#define PL0_RW (PL0_R | PL0_W)
1478
1479
1480static inline int arm_highest_el(CPUARMState *env)
1481{
1482 if (arm_feature(env, ARM_FEATURE_EL3)) {
1483 return 3;
1484 }
1485 if (arm_feature(env, ARM_FEATURE_EL2)) {
1486 return 2;
1487 }
1488 return 1;
1489}
1490
1491
1492
1493
1494static inline int arm_current_el(CPUARMState *env)
1495{
1496 if (arm_feature(env, ARM_FEATURE_M)) {
1497 return !((env->v7m.exception == 0) && (env->v7m.control & 1));
1498 }
1499
1500 if (is_a64(env)) {
1501 return extract32(env->pstate, 2, 2);
1502 }
1503
1504 switch (env->uncached_cpsr & 0x1f) {
1505 case ARM_CPU_MODE_USR:
1506 return 0;
1507 case ARM_CPU_MODE_HYP:
1508 return 2;
1509 case ARM_CPU_MODE_MON:
1510 return 3;
1511 default:
1512 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1513
1514
1515
1516 return 3;
1517 }
1518
1519 return 1;
1520 }
1521}
1522
1523typedef struct ARMCPRegInfo ARMCPRegInfo;
1524
1525typedef enum CPAccessResult {
1526
1527 CP_ACCESS_OK = 0,
1528
1529
1530
1531
1532
1533
1534 CP_ACCESS_TRAP = 1,
1535
1536
1537
1538
1539 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
1540
1541 CP_ACCESS_TRAP_EL2 = 3,
1542 CP_ACCESS_TRAP_EL3 = 4,
1543
1544 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
1545 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
1546
1547
1548
1549 CP_ACCESS_TRAP_FP_EL2 = 7,
1550 CP_ACCESS_TRAP_FP_EL3 = 8,
1551} CPAccessResult;
1552
1553
1554
1555
1556typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1557typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
1558 uint64_t value);
1559
1560typedef CPAccessResult CPAccessFn(CPUARMState *env,
1561 const ARMCPRegInfo *opaque,
1562 bool isread);
1563
1564typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1565
1566#define CP_ANY 0xff
1567
1568
1569struct ARMCPRegInfo {
1570
1571 const char *name;
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589 uint8_t cp;
1590 uint8_t crn;
1591 uint8_t crm;
1592 uint8_t opc0;
1593 uint8_t opc1;
1594 uint8_t opc2;
1595
1596 int state;
1597
1598 int type;
1599
1600 int access;
1601
1602 int secure;
1603
1604
1605
1606
1607 void *opaque;
1608
1609
1610
1611 uint64_t resetvalue;
1612
1613
1614
1615
1616
1617
1618 ptrdiff_t fieldoffset;
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631 ptrdiff_t bank_fieldoffsets[2];
1632
1633
1634
1635
1636
1637
1638 CPAccessFn *accessfn;
1639
1640
1641
1642
1643 CPReadFn *readfn;
1644
1645
1646
1647
1648 CPWriteFn *writefn;
1649
1650
1651
1652
1653
1654 CPReadFn *raw_readfn;
1655
1656
1657
1658
1659
1660
1661 CPWriteFn *raw_writefn;
1662
1663
1664
1665
1666 CPResetFn *resetfn;
1667};
1668
1669
1670
1671
1672#define CPREG_FIELD32(env, ri) \
1673 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1674#define CPREG_FIELD64(env, ri) \
1675 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1676
1677#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1678
1679void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1680 const ARMCPRegInfo *regs, void *opaque);
1681void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1682 const ARMCPRegInfo *regs, void *opaque);
1683static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
1684{
1685 define_arm_cp_regs_with_opaque(cpu, regs, 0);
1686}
1687static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
1688{
1689 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
1690}
1691const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
1692
1693
1694void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1695 uint64_t value);
1696
1697uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
1698
1699
1700
1701
1702void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
1703
1704
1705
1706
1707static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
1708{
1709 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
1710}
1711
1712static inline bool cp_access_ok(int current_el,
1713 const ARMCPRegInfo *ri, int isread)
1714{
1715 return (ri->access >> ((current_el * 2) + isread)) & 1;
1716}
1717
1718
1719uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735bool write_list_to_cpustate(ARMCPU *cpu);
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751bool write_cpustate_to_list(ARMCPU *cpu);
1752
1753
1754
1755
1756
1757#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1758
1759#define ARM_CPUID_TI915T 0x54029152
1760#define ARM_CPUID_TI925T 0x54029252
1761
1762#if defined(CONFIG_USER_ONLY)
1763#define TARGET_PAGE_BITS 12
1764#else
1765
1766
1767
1768#define TARGET_PAGE_BITS_VARY
1769#define TARGET_PAGE_BITS_MIN 10
1770#endif
1771
1772#if defined(TARGET_AARCH64)
1773# define TARGET_PHYS_ADDR_SPACE_BITS 48
1774# define TARGET_VIRT_ADDR_SPACE_BITS 64
1775#else
1776# define TARGET_PHYS_ADDR_SPACE_BITS 40
1777# define TARGET_VIRT_ADDR_SPACE_BITS 32
1778#endif
1779
1780static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
1781 unsigned int target_el)
1782{
1783 CPUARMState *env = cs->env_ptr;
1784 unsigned int cur_el = arm_current_el(env);
1785 bool secure = arm_is_secure(env);
1786 bool pstate_unmasked;
1787 int8_t unmasked = 0;
1788
1789
1790
1791
1792
1793 if (cur_el > target_el) {
1794 return false;
1795 }
1796
1797 switch (excp_idx) {
1798 case EXCP_FIQ:
1799 pstate_unmasked = !(env->daif & PSTATE_F);
1800 break;
1801
1802 case EXCP_IRQ:
1803 pstate_unmasked = !(env->daif & PSTATE_I);
1804 break;
1805
1806 case EXCP_VFIQ:
1807 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
1808
1809 return false;
1810 }
1811 return !(env->daif & PSTATE_F);
1812 case EXCP_VIRQ:
1813 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
1814
1815 return false;
1816 }
1817 return !(env->daif & PSTATE_I);
1818 default:
1819 g_assert_not_reached();
1820 }
1821
1822
1823
1824
1825
1826 if ((target_el > cur_el) && (target_el != 1)) {
1827
1828 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1829
1830
1831
1832
1833
1834 if (target_el == 3 || !secure) {
1835 unmasked = 1;
1836 }
1837 } else {
1838
1839
1840
1841
1842 bool hcr, scr;
1843
1844 switch (excp_idx) {
1845 case EXCP_FIQ:
1846
1847
1848
1849
1850
1851
1852 hcr = (env->cp15.hcr_el2 & HCR_FMO);
1853 scr = (env->cp15.scr_el3 & SCR_FIQ);
1854
1855
1856
1857
1858
1859
1860 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
1861 break;
1862 case EXCP_IRQ:
1863
1864
1865
1866
1867
1868
1869 hcr = (env->cp15.hcr_el2 & HCR_IMO);
1870 scr = false;
1871 break;
1872 default:
1873 g_assert_not_reached();
1874 }
1875
1876 if ((scr || hcr) && !secure) {
1877 unmasked = 1;
1878 }
1879 }
1880 }
1881
1882
1883
1884
1885 return unmasked || pstate_unmasked;
1886}
1887
1888#define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
1889
1890#define cpu_signal_handler cpu_arm_signal_handler
1891#define cpu_list arm_cpu_list
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944typedef enum ARMMMUIdx {
1945 ARMMMUIdx_S12NSE0 = 0,
1946 ARMMMUIdx_S12NSE1 = 1,
1947 ARMMMUIdx_S1E2 = 2,
1948 ARMMMUIdx_S1E3 = 3,
1949 ARMMMUIdx_S1SE0 = 4,
1950 ARMMMUIdx_S1SE1 = 5,
1951 ARMMMUIdx_S2NS = 6,
1952
1953
1954
1955 ARMMMUIdx_S1NSE0 = 7,
1956 ARMMMUIdx_S1NSE1 = 8,
1957} ARMMMUIdx;
1958
1959#define MMU_USER_IDX 0
1960
1961
1962static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
1963{
1964 assert(mmu_idx < ARMMMUIdx_S2NS);
1965 return mmu_idx & 3;
1966}
1967
1968
1969static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
1970{
1971 int el = arm_current_el(env);
1972
1973 if (el < 2 && arm_is_secure_below_el3(env)) {
1974 return ARMMMUIdx_S1SE0 + el;
1975 }
1976 return el;
1977}
1978
1979
1980typedef enum ARMASIdx {
1981 ARMASIdx_NS = 0,
1982 ARMASIdx_S = 1,
1983} ARMASIdx;
1984
1985
1986static inline int arm_debug_target_el(CPUARMState *env)
1987{
1988 bool secure = arm_is_secure(env);
1989 bool route_to_el2 = false;
1990
1991 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
1992 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
1993 env->cp15.mdcr_el2 & (1 << 8);
1994 }
1995
1996 if (route_to_el2) {
1997 return 2;
1998 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
1999 !arm_el_is_aa64(env, 3) && secure) {
2000 return 3;
2001 } else {
2002 return 1;
2003 }
2004}
2005
2006static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
2007{
2008 if (arm_is_secure(env)) {
2009
2010 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0
2011 || arm_current_el(env) == 3) {
2012 return false;
2013 }
2014 }
2015
2016 if (arm_current_el(env) == arm_debug_target_el(env)) {
2017 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
2018 || (env->daif & PSTATE_D)) {
2019 return false;
2020 }
2021 }
2022 return true;
2023}
2024
2025static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
2026{
2027 int el = arm_current_el(env);
2028
2029 if (el == 0 && arm_el_is_aa64(env, 1)) {
2030 return aa64_generate_debug_exceptions(env);
2031 }
2032
2033 if (arm_is_secure(env)) {
2034 int spd;
2035
2036 if (el == 0 && (env->cp15.sder & 1)) {
2037
2038
2039
2040
2041 return true;
2042 }
2043
2044 spd = extract32(env->cp15.mdcr_el3, 14, 2);
2045 switch (spd) {
2046 case 1:
2047
2048 case 0:
2049
2050
2051
2052
2053
2054 return true;
2055 case 2:
2056 return false;
2057 case 3:
2058 return true;
2059 }
2060 }
2061
2062 return el != 2;
2063}
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079static inline bool arm_generate_debug_exceptions(CPUARMState *env)
2080{
2081 if (env->aarch64) {
2082 return aa64_generate_debug_exceptions(env);
2083 } else {
2084 return aa32_generate_debug_exceptions(env);
2085 }
2086}
2087
2088
2089
2090
2091static inline bool arm_singlestep_active(CPUARMState *env)
2092{
2093 return extract32(env->cp15.mdscr_el1, 0, 1)
2094 && arm_el_is_aa64(env, arm_debug_target_el(env))
2095 && arm_generate_debug_exceptions(env);
2096}
2097
2098static inline bool arm_sctlr_b(CPUARMState *env)
2099{
2100 return
2101
2102
2103
2104
2105#ifndef CONFIG_USER_ONLY
2106 !arm_feature(env, ARM_FEATURE_V7) &&
2107#endif
2108 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
2109}
2110
2111
2112static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
2113{
2114 int cur_el;
2115
2116
2117 if (!is_a64(env)) {
2118 return
2119#ifdef CONFIG_USER_ONLY
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131 arm_sctlr_b(env) ||
2132#endif
2133 ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
2134 }
2135
2136 cur_el = arm_current_el(env);
2137
2138 if (cur_el == 0) {
2139 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
2140 }
2141
2142 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
2143}
2144
2145#include "exec/cpu-all.h"
2146
2147
2148
2149
2150
2151
2152#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
2153#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
2154#define ARM_TBFLAG_MMUIDX_SHIFT 28
2155#define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
2156#define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
2157#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
2158#define ARM_TBFLAG_PSTATE_SS_SHIFT 26
2159#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
2160
2161#define ARM_TBFLAG_FPEXC_EL_SHIFT 24
2162#define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
2163
2164
2165#define ARM_TBFLAG_THUMB_SHIFT 0
2166#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
2167#define ARM_TBFLAG_VECLEN_SHIFT 1
2168#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
2169#define ARM_TBFLAG_VECSTRIDE_SHIFT 4
2170#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
2171#define ARM_TBFLAG_VFPEN_SHIFT 7
2172#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
2173#define ARM_TBFLAG_CONDEXEC_SHIFT 8
2174#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
2175#define ARM_TBFLAG_SCTLR_B_SHIFT 16
2176#define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
2177
2178
2179
2180#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
2181#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2182
2183
2184
2185
2186#define ARM_TBFLAG_NS_SHIFT 19
2187#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
2188#define ARM_TBFLAG_BE_DATA_SHIFT 20
2189#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
2190
2191
2192#define ARM_TBFLAG_TBI0_SHIFT 0
2193#define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT)
2194#define ARM_TBFLAG_TBI1_SHIFT 1
2195#define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT)
2196
2197
2198#define ARM_TBFLAG_AARCH64_STATE(F) \
2199 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
2200#define ARM_TBFLAG_MMUIDX(F) \
2201 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
2202#define ARM_TBFLAG_SS_ACTIVE(F) \
2203 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
2204#define ARM_TBFLAG_PSTATE_SS(F) \
2205 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
2206#define ARM_TBFLAG_FPEXC_EL(F) \
2207 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
2208#define ARM_TBFLAG_THUMB(F) \
2209 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
2210#define ARM_TBFLAG_VECLEN(F) \
2211 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
2212#define ARM_TBFLAG_VECSTRIDE(F) \
2213 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
2214#define ARM_TBFLAG_VFPEN(F) \
2215 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
2216#define ARM_TBFLAG_CONDEXEC(F) \
2217 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
2218#define ARM_TBFLAG_SCTLR_B(F) \
2219 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
2220#define ARM_TBFLAG_XSCALE_CPAR(F) \
2221 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2222#define ARM_TBFLAG_NS(F) \
2223 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
2224#define ARM_TBFLAG_BE_DATA(F) \
2225 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
2226#define ARM_TBFLAG_TBI0(F) \
2227 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
2228#define ARM_TBFLAG_TBI1(F) \
2229 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT)
2230
2231static inline bool bswap_code(bool sctlr_b)
2232{
2233#ifdef CONFIG_USER_ONLY
2234
2235
2236
2237
2238 return
2239#ifdef TARGET_WORDS_BIGENDIAN
2240 1 ^
2241#endif
2242 sctlr_b;
2243#else
2244
2245
2246
2247 return 0;
2248#endif
2249}
2250
2251
2252
2253
2254static inline int fp_exception_el(CPUARMState *env)
2255{
2256 int fpen;
2257 int cur_el = arm_current_el(env);
2258
2259
2260
2261
2262 if (!arm_feature(env, ARM_FEATURE_V6)) {
2263 return 0;
2264 }
2265
2266
2267
2268
2269
2270
2271 fpen = extract32(env->cp15.cpacr_el1, 20, 2);
2272 switch (fpen) {
2273 case 0:
2274 case 2:
2275 if (cur_el == 0 || cur_el == 1) {
2276
2277 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2278 return 3;
2279 }
2280 return 1;
2281 }
2282 if (cur_el == 3 && !is_a64(env)) {
2283
2284 return 3;
2285 }
2286 break;
2287 case 1:
2288 if (cur_el == 0) {
2289 return 1;
2290 }
2291 break;
2292 case 3:
2293 break;
2294 }
2295
2296
2297
2298
2299
2300
2301 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
2302 && !arm_is_secure_below_el3(env)) {
2303
2304 return 2;
2305 }
2306
2307
2308 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
2309
2310 return 3;
2311 }
2312
2313 return 0;
2314}
2315
2316#ifdef CONFIG_USER_ONLY
2317static inline bool arm_cpu_bswap_data(CPUARMState *env)
2318{
2319 return
2320#ifdef TARGET_WORDS_BIGENDIAN
2321 1 ^
2322#endif
2323 arm_cpu_data_is_big_endian(env);
2324}
2325#endif
2326
2327#ifndef CONFIG_USER_ONLY
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx);
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx);
2349#else
2350
2351static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
2352{
2353 return 0;
2354}
2355
2356static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
2357{
2358 return 0;
2359}
2360#endif
2361
2362static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
2363 target_ulong *cs_base, uint32_t *flags)
2364{
2365 ARMMMUIdx mmu_idx = cpu_mmu_index(env, false);
2366 if (is_a64(env)) {
2367 *pc = env->pc;
2368 *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
2369
2370 *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT);
2371 *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);
2372 } else {
2373 *pc = env->regs[15];
2374 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
2375 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
2376 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
2377 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
2378 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT);
2379 if (!(access_secure_reg(env))) {
2380 *flags |= ARM_TBFLAG_NS_MASK;
2381 }
2382 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
2383 || arm_el_is_aa64(env, 1)) {
2384 *flags |= ARM_TBFLAG_VFPEN_MASK;
2385 }
2386 *flags |= (extract32(env->cp15.c15_cpar, 0, 2)
2387 << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
2388 }
2389
2390 *flags |= (mmu_idx << ARM_TBFLAG_MMUIDX_SHIFT);
2391
2392
2393
2394
2395
2396
2397
2398
2399 if (arm_singlestep_active(env)) {
2400 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
2401 if (is_a64(env)) {
2402 if (env->pstate & PSTATE_SS) {
2403 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
2404 }
2405 } else {
2406 if (env->uncached_cpsr & PSTATE_SS) {
2407 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
2408 }
2409 }
2410 }
2411 if (arm_cpu_data_is_big_endian(env)) {
2412 *flags |= ARM_TBFLAG_BE_DATA_MASK;
2413 }
2414 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
2415
2416 *cs_base = 0;
2417}
2418
2419enum {
2420 QEMU_PSCI_CONDUIT_DISABLED = 0,
2421 QEMU_PSCI_CONDUIT_SMC = 1,
2422 QEMU_PSCI_CONDUIT_HVC = 2,
2423};
2424
2425#ifndef CONFIG_USER_ONLY
2426
2427static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2428{
2429 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
2430}
2431
2432
2433
2434
2435
2436static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
2437{
2438 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
2439}
2440#endif
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
2454 void *opaque);
2455
2456
2457
2458
2459
2460
2461static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu)
2462{
2463 return cpu->el_change_hook_opaque;
2464}
2465
2466#endif
2467