LXR qemu/target-i386/gdbstub.c

   1/*
   2 * x86 gdb server stub
   3 *
   4 * Copyright (c) 2003-2005 Fabrice Bellard
   5 * Copyright (c) 2013 SUSE LINUX Products GmbH
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20#include "qemu/osdep.h"
  21#include "qemu-common.h"
  22#include "cpu.h"
  23#include "exec/gdbstub.h"
  24
  25#ifdef TARGET_X86_64
  26static const int gpr_map[16] = {
  27    R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
  28    8, 9, 10, 11, 12, 13, 14, 15
  29};
  30#else
  31#define gpr_map gpr_map32
  32#endif
  33static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
  34
  35#define IDX_IP_REG      CPU_NB_REGS
  36#define IDX_FLAGS_REG   (IDX_IP_REG + 1)
  37#define IDX_SEG_REGS    (IDX_FLAGS_REG + 1)
  38#define IDX_FP_REGS     (IDX_SEG_REGS + 6)
  39#define IDX_XMM_REGS    (IDX_FP_REGS + 16)
  40#define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)
  41
  42int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
  43{
  44    X86CPU *cpu = X86_CPU(cs);
  45    CPUX86State *env = &cpu->env;
  46
  47    if (n < CPU_NB_REGS) {
  48        if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
  49            return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
  50        } else if (n < CPU_NB_REGS32) {
  51            return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
  52        }
  53    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
  54#ifdef USE_X86LDOUBLE
  55        /* FIXME: byteswap float values - after fixing fpregs layout. */
  56        memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
  57#else
  58        memset(mem_buf, 0, 10);
  59#endif
  60        return 10;
  61    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
  62        n -= IDX_XMM_REGS;
  63        if (n < CPU_NB_REGS32 ||
  64            (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
  65            stq_p(mem_buf, env->xmm_regs[n].ZMM_Q(0));
  66            stq_p(mem_buf + 8, env->xmm_regs[n].ZMM_Q(1));
  67            return 16;
  68        }
  69    } else {
  70        switch (n) {
  71        case IDX_IP_REG:
  72            if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
  73                return gdb_get_reg64(mem_buf, env->eip);
  74            } else {
  75                return gdb_get_reg32(mem_buf, env->eip);
  76            }
  77        case IDX_FLAGS_REG:
  78            return gdb_get_reg32(mem_buf, env->eflags);
  79
  80        case IDX_SEG_REGS:
  81            return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
  82        case IDX_SEG_REGS + 1:
  83            return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
  84        case IDX_SEG_REGS + 2:
  85            return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
  86        case IDX_SEG_REGS + 3:
  87            return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
  88        case IDX_SEG_REGS + 4:
  89            return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
  90        case IDX_SEG_REGS + 5:
  91            return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
  92
  93        case IDX_FP_REGS + 8:
  94            return gdb_get_reg32(mem_buf, env->fpuc);
  95        case IDX_FP_REGS + 9:
  96            return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
  97                                          (env->fpstt & 0x7) << 11);
  98        case IDX_FP_REGS + 10:
  99            return gdb_get_reg32(mem_buf, 0); /* ftag */
 100        case IDX_FP_REGS + 11:
 101            return gdb_get_reg32(mem_buf, 0); /* fiseg */
 102        case IDX_FP_REGS + 12:
 103            return gdb_get_reg32(mem_buf, 0); /* fioff */
 104        case IDX_FP_REGS + 13:
 105            return gdb_get_reg32(mem_buf, 0); /* foseg */
 106        case IDX_FP_REGS + 14:
 107            return gdb_get_reg32(mem_buf, 0); /* fooff */
 108        case IDX_FP_REGS + 15:
 109            return gdb_get_reg32(mem_buf, 0); /* fop */
 110
 111        case IDX_MXCSR_REG:
 112            return gdb_get_reg32(mem_buf, env->mxcsr);
 113        }
 114    }
 115    return 0;
 116}
 117
 118static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf)
 119{
 120    CPUX86State *env = &cpu->env;
 121    uint16_t selector = ldl_p(mem_buf);
 122
 123    if (selector != env->segs[sreg].selector) {
 124#if defined(CONFIG_USER_ONLY)
 125        cpu_x86_load_seg(env, sreg, selector);
 126#else
 127        unsigned int limit, flags;
 128        target_ulong base;
 129
 130        if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 131            int dpl = (env->eflags & VM_MASK) ? 3 : 0;
 132            base = selector << 4;
 133            limit = 0xffff;
 134            flags = DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 135                    DESC_A_MASK | (dpl << DESC_DPL_SHIFT);
 136        } else {
 137            if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
 138                                         &flags)) {
 139                return 4;
 140            }
 141        }
 142        cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
 143#endif
 144    }
 145    return 4;
 146}
 147
 148int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 149{
 150    X86CPU *cpu = X86_CPU(cs);
 151    CPUX86State *env = &cpu->env;
 152    uint32_t tmp;
 153
 154    if (n < CPU_NB_REGS) {
 155        if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 156            env->regs[gpr_map[n]] = ldtul_p(mem_buf);
 157            return sizeof(target_ulong);
 158        } else if (n < CPU_NB_REGS32) {
 159            n = gpr_map32[n];
 160            env->regs[n] &= ~0xffffffffUL;
 161            env->regs[n] |= (uint32_t)ldl_p(mem_buf);
 162            return 4;
 163        }
 164    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
 165#ifdef USE_X86LDOUBLE
 166        /* FIXME: byteswap float values - after fixing fpregs layout. */
 167        memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
 168#endif
 169        return 10;
 170    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
 171        n -= IDX_XMM_REGS;
 172        if (n < CPU_NB_REGS32 ||
 173            (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
 174            env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
 175            env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
 176            return 16;
 177        }
 178    } else {
 179        switch (n) {
 180        case IDX_IP_REG:
 181            if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 182                env->eip = ldq_p(mem_buf);
 183                return 8;
 184            } else {
 185                env->eip &= ~0xffffffffUL;
 186                env->eip |= (uint32_t)ldl_p(mem_buf);
 187                return 4;
 188            }
 189        case IDX_FLAGS_REG:
 190            env->eflags = ldl_p(mem_buf);
 191            return 4;
 192
 193        case IDX_SEG_REGS:
 194            return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
 195        case IDX_SEG_REGS + 1:
 196            return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
 197        case IDX_SEG_REGS + 2:
 198            return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
 199        case IDX_SEG_REGS + 3:
 200            return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
 201        case IDX_SEG_REGS + 4:
 202            return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
 203        case IDX_SEG_REGS + 5:
 204            return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
 205
 206        case IDX_FP_REGS + 8:
 207            cpu_set_fpuc(env, ldl_p(mem_buf));
 208            return 4;
 209        case IDX_FP_REGS + 9:
 210            tmp = ldl_p(mem_buf);
 211            env->fpstt = (tmp >> 11) & 7;
 212            env->fpus = tmp & ~0x3800;
 213            return 4;
 214        case IDX_FP_REGS + 10: /* ftag */
 215            return 4;
 216        case IDX_FP_REGS + 11: /* fiseg */
 217            return 4;
 218        case IDX_FP_REGS + 12: /* fioff */
 219            return 4;
 220        case IDX_FP_REGS + 13: /* foseg */
 221            return 4;
 222        case IDX_FP_REGS + 14: /* fooff */
 223            return 4;
 224        case IDX_FP_REGS + 15: /* fop */
 225            return 4;
 226
 227        case IDX_MXCSR_REG:
 228            cpu_set_mxcsr(env, ldl_p(mem_buf));
 229            return 4;
 230        }
 231    }
 232    /* Unrecognised register.  */
 233    return 0;
 234}
 235