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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "cpu.h"
24#include "qemu-common.h"
25#include "exec/exec-all.h"
26
27
28static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
29{
30 LM32CPU *cpu = LM32_CPU(cs);
31
32 cpu->env.pc = value;
33}
34
35
36static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b)
37{
38 ObjectClass *class_a = (ObjectClass *)a;
39 ObjectClass *class_b = (ObjectClass *)b;
40 const char *name_a, *name_b;
41
42 name_a = object_class_get_name(class_a);
43 name_b = object_class_get_name(class_b);
44 return strcmp(name_a, name_b);
45}
46
47static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
48{
49 ObjectClass *oc = data;
50 CPUListState *s = user_data;
51 const char *typename = object_class_get_name(oc);
52 char *name;
53
54 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_LM32_CPU));
55 (*s->cpu_fprintf)(s->file, " %s\n", name);
56 g_free(name);
57}
58
59
60void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf)
61{
62 CPUListState s = {
63 .file = f,
64 .cpu_fprintf = cpu_fprintf,
65 };
66 GSList *list;
67
68 list = object_class_get_list(TYPE_LM32_CPU, false);
69 list = g_slist_sort(list, lm32_cpu_list_compare);
70 (*cpu_fprintf)(f, "Available CPUs:\n");
71 g_slist_foreach(list, lm32_cpu_list_entry, &s);
72 g_slist_free(list);
73}
74
75static void lm32_cpu_init_cfg_reg(LM32CPU *cpu)
76{
77 CPULM32State *env = &cpu->env;
78 uint32_t cfg = 0;
79
80 if (cpu->features & LM32_FEATURE_MULTIPLY) {
81 cfg |= CFG_M;
82 }
83
84 if (cpu->features & LM32_FEATURE_DIVIDE) {
85 cfg |= CFG_D;
86 }
87
88 if (cpu->features & LM32_FEATURE_SHIFT) {
89 cfg |= CFG_S;
90 }
91
92 if (cpu->features & LM32_FEATURE_SIGN_EXTEND) {
93 cfg |= CFG_X;
94 }
95
96 if (cpu->features & LM32_FEATURE_I_CACHE) {
97 cfg |= CFG_IC;
98 }
99
100 if (cpu->features & LM32_FEATURE_D_CACHE) {
101 cfg |= CFG_DC;
102 }
103
104 if (cpu->features & LM32_FEATURE_CYCLE_COUNT) {
105 cfg |= CFG_CC;
106 }
107
108 cfg |= (cpu->num_interrupts << CFG_INT_SHIFT);
109 cfg |= (cpu->num_breakpoints << CFG_BP_SHIFT);
110 cfg |= (cpu->num_watchpoints << CFG_WP_SHIFT);
111 cfg |= (cpu->revision << CFG_REV_SHIFT);
112
113 env->cfg = cfg;
114}
115
116static bool lm32_cpu_has_work(CPUState *cs)
117{
118 return cs->interrupt_request & CPU_INTERRUPT_HARD;
119}
120
121
122static void lm32_cpu_reset(CPUState *s)
123{
124 LM32CPU *cpu = LM32_CPU(s);
125 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
126 CPULM32State *env = &cpu->env;
127
128 lcc->parent_reset(s);
129
130
131 memset(env, 0, offsetof(CPULM32State, eba));
132
133 lm32_cpu_init_cfg_reg(cpu);
134 tlb_flush(s, 1);
135}
136
137static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
138{
139 info->mach = bfd_mach_lm32;
140 info->print_insn = print_insn_lm32;
141}
142
143static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
144{
145 CPUState *cs = CPU(dev);
146 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
147 Error *local_err = NULL;
148
149 cpu_exec_realizefn(cs, &local_err);
150 if (local_err != NULL) {
151 error_propagate(errp, local_err);
152 return;
153 }
154
155 cpu_reset(cs);
156
157 qemu_init_vcpu(cs);
158
159 lcc->parent_realize(dev, errp);
160}
161
162static void lm32_cpu_initfn(Object *obj)
163{
164 CPUState *cs = CPU(obj);
165 LM32CPU *cpu = LM32_CPU(obj);
166 CPULM32State *env = &cpu->env;
167 static bool tcg_initialized;
168
169 cs->env_ptr = env;
170
171 env->flags = 0;
172
173 if (tcg_enabled() && !tcg_initialized) {
174 tcg_initialized = true;
175 lm32_translate_init();
176 }
177}
178
179static void lm32_basic_cpu_initfn(Object *obj)
180{
181 LM32CPU *cpu = LM32_CPU(obj);
182
183 cpu->revision = 3;
184 cpu->num_interrupts = 32;
185 cpu->num_breakpoints = 4;
186 cpu->num_watchpoints = 4;
187 cpu->features = LM32_FEATURE_SHIFT
188 | LM32_FEATURE_SIGN_EXTEND
189 | LM32_FEATURE_CYCLE_COUNT;
190}
191
192static void lm32_standard_cpu_initfn(Object *obj)
193{
194 LM32CPU *cpu = LM32_CPU(obj);
195
196 cpu->revision = 3;
197 cpu->num_interrupts = 32;
198 cpu->num_breakpoints = 4;
199 cpu->num_watchpoints = 4;
200 cpu->features = LM32_FEATURE_MULTIPLY
201 | LM32_FEATURE_DIVIDE
202 | LM32_FEATURE_SHIFT
203 | LM32_FEATURE_SIGN_EXTEND
204 | LM32_FEATURE_I_CACHE
205 | LM32_FEATURE_CYCLE_COUNT;
206}
207
208static void lm32_full_cpu_initfn(Object *obj)
209{
210 LM32CPU *cpu = LM32_CPU(obj);
211
212 cpu->revision = 3;
213 cpu->num_interrupts = 32;
214 cpu->num_breakpoints = 4;
215 cpu->num_watchpoints = 4;
216 cpu->features = LM32_FEATURE_MULTIPLY
217 | LM32_FEATURE_DIVIDE
218 | LM32_FEATURE_SHIFT
219 | LM32_FEATURE_SIGN_EXTEND
220 | LM32_FEATURE_I_CACHE
221 | LM32_FEATURE_D_CACHE
222 | LM32_FEATURE_CYCLE_COUNT;
223}
224
225typedef struct LM32CPUInfo {
226 const char *name;
227 void (*initfn)(Object *obj);
228} LM32CPUInfo;
229
230static const LM32CPUInfo lm32_cpus[] = {
231 {
232 .name = "lm32-basic",
233 .initfn = lm32_basic_cpu_initfn,
234 },
235 {
236 .name = "lm32-standard",
237 .initfn = lm32_standard_cpu_initfn,
238 },
239 {
240 .name = "lm32-full",
241 .initfn = lm32_full_cpu_initfn,
242 },
243};
244
245static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
246{
247 ObjectClass *oc;
248 char *typename;
249
250 if (cpu_model == NULL) {
251 return NULL;
252 }
253
254 typename = g_strdup_printf("%s-" TYPE_LM32_CPU, cpu_model);
255 oc = object_class_by_name(typename);
256 g_free(typename);
257 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_LM32_CPU) ||
258 object_class_is_abstract(oc))) {
259 oc = NULL;
260 }
261 return oc;
262}
263
264static void lm32_cpu_class_init(ObjectClass *oc, void *data)
265{
266 LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
267 CPUClass *cc = CPU_CLASS(oc);
268 DeviceClass *dc = DEVICE_CLASS(oc);
269
270 lcc->parent_realize = dc->realize;
271 dc->realize = lm32_cpu_realizefn;
272
273 lcc->parent_reset = cc->reset;
274 cc->reset = lm32_cpu_reset;
275
276 cc->class_by_name = lm32_cpu_class_by_name;
277 cc->has_work = lm32_cpu_has_work;
278 cc->do_interrupt = lm32_cpu_do_interrupt;
279 cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
280 cc->dump_state = lm32_cpu_dump_state;
281 cc->set_pc = lm32_cpu_set_pc;
282 cc->gdb_read_register = lm32_cpu_gdb_read_register;
283 cc->gdb_write_register = lm32_cpu_gdb_write_register;
284#ifdef CONFIG_USER_ONLY
285 cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault;
286#else
287 cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
288 cc->vmsd = &vmstate_lm32_cpu;
289#endif
290 cc->gdb_num_core_regs = 32 + 7;
291 cc->gdb_stop_before_watchpoint = true;
292 cc->debug_excp_handler = lm32_debug_excp_handler;
293 cc->disas_set_info = lm32_cpu_disas_set_info;
294}
295
296static void lm32_register_cpu_type(const LM32CPUInfo *info)
297{
298 TypeInfo type_info = {
299 .parent = TYPE_LM32_CPU,
300 .instance_init = info->initfn,
301 };
302
303 type_info.name = g_strdup_printf("%s-" TYPE_LM32_CPU, info->name);
304 type_register(&type_info);
305 g_free((void *)type_info.name);
306}
307
308static const TypeInfo lm32_cpu_type_info = {
309 .name = TYPE_LM32_CPU,
310 .parent = TYPE_CPU,
311 .instance_size = sizeof(LM32CPU),
312 .instance_init = lm32_cpu_initfn,
313 .abstract = true,
314 .class_size = sizeof(LM32CPUClass),
315 .class_init = lm32_cpu_class_init,
316};
317
318static void lm32_cpu_register_types(void)
319{
320 int i;
321
322 type_register_static(&lm32_cpu_type_info);
323 for (i = 0; i < ARRAY_SIZE(lm32_cpus); i++) {
324 lm32_register_cpu_type(&lm32_cpus[i]);
325 }
326}
327
328type_init(lm32_cpu_register_types)
329
