1#include "qemu/osdep.h"
2#include "qemu-common.h"
3#include "cpu.h"
4#include "hw/hw.h"
5#include "migration/cpu.h"
6
7static int cpu_post_load(void *opaque, int version_id)
8{
9 MIPSCPU *cpu = opaque;
10 CPUMIPSState *env = &cpu->env;
11
12 restore_fp_status(env);
13 restore_msa_fp_status(env);
14 compute_hflags(env);
15 restore_pamask(env);
16
17 return 0;
18}
19
20
21
22static int get_fpr(QEMUFile *f, void *pv, size_t size)
23{
24 int i;
25 fpr_t *v = pv;
26
27 for (i = 0; i < MSA_WRLEN/64; i++) {
28 qemu_get_sbe64s(f, &v->wr.d[i]);
29 }
30 return 0;
31}
32
33static void put_fpr(QEMUFile *f, void *pv, size_t size)
34{
35 int i;
36 fpr_t *v = pv;
37
38 for (i = 0; i < MSA_WRLEN/64; i++) {
39 qemu_put_sbe64s(f, &v->wr.d[i]);
40 }
41}
42
43const VMStateInfo vmstate_info_fpr = {
44 .name = "fpr",
45 .get = get_fpr,
46 .put = put_fpr,
47};
48
49#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
50 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
51
52#define VMSTATE_FPR_ARRAY(_f, _s, _n) \
53 VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
54
55static VMStateField vmstate_fpu_fields[] = {
56 VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
57 VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
58 VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
59 VMSTATE_END_OF_LIST()
60};
61
62const VMStateDescription vmstate_fpu = {
63 .name = "cpu/fpu",
64 .version_id = 1,
65 .minimum_version_id = 1,
66 .fields = vmstate_fpu_fields
67};
68
69const VMStateDescription vmstate_inactive_fpu = {
70 .name = "cpu/inactive_fpu",
71 .version_id = 1,
72 .minimum_version_id = 1,
73 .fields = vmstate_fpu_fields
74};
75
76
77
78static VMStateField vmstate_tc_fields[] = {
79 VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
80 VMSTATE_UINTTL(PC, TCState),
81 VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
82 VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
83 VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
84 VMSTATE_UINTTL(DSPControl, TCState),
85 VMSTATE_INT32(CP0_TCStatus, TCState),
86 VMSTATE_INT32(CP0_TCBind, TCState),
87 VMSTATE_UINTTL(CP0_TCHalt, TCState),
88 VMSTATE_UINTTL(CP0_TCContext, TCState),
89 VMSTATE_UINTTL(CP0_TCSchedule, TCState),
90 VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
91 VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
92 VMSTATE_UINTTL(CP0_UserLocal, TCState),
93 VMSTATE_INT32(msacsr, TCState),
94 VMSTATE_END_OF_LIST()
95};
96
97const VMStateDescription vmstate_tc = {
98 .name = "cpu/tc",
99 .version_id = 1,
100 .minimum_version_id = 1,
101 .fields = vmstate_tc_fields
102};
103
104const VMStateDescription vmstate_inactive_tc = {
105 .name = "cpu/inactive_tc",
106 .version_id = 1,
107 .minimum_version_id = 1,
108 .fields = vmstate_tc_fields
109};
110
111
112
113const VMStateDescription vmstate_mvp = {
114 .name = "cpu/mvp",
115 .version_id = 1,
116 .minimum_version_id = 1,
117 .fields = (VMStateField[]) {
118 VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
119 VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
120 VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
121 VMSTATE_END_OF_LIST()
122 }
123};
124
125
126
127static int get_tlb(QEMUFile *f, void *pv, size_t size)
128{
129 r4k_tlb_t *v = pv;
130 uint16_t flags;
131
132 qemu_get_betls(f, &v->VPN);
133 qemu_get_be32s(f, &v->PageMask);
134 qemu_get_be16s(f, &v->ASID);
135 qemu_get_be16s(f, &flags);
136 v->G = (flags >> 10) & 1;
137 v->C0 = (flags >> 7) & 3;
138 v->C1 = (flags >> 4) & 3;
139 v->V0 = (flags >> 3) & 1;
140 v->V1 = (flags >> 2) & 1;
141 v->D0 = (flags >> 1) & 1;
142 v->D1 = (flags >> 0) & 1;
143 v->EHINV = (flags >> 15) & 1;
144 v->RI1 = (flags >> 14) & 1;
145 v->RI0 = (flags >> 13) & 1;
146 v->XI1 = (flags >> 12) & 1;
147 v->XI0 = (flags >> 11) & 1;
148 qemu_get_be64s(f, &v->PFN[0]);
149 qemu_get_be64s(f, &v->PFN[1]);
150
151 return 0;
152}
153
154static void put_tlb(QEMUFile *f, void *pv, size_t size)
155{
156 r4k_tlb_t *v = pv;
157
158 uint16_t asid = v->ASID;
159 uint16_t flags = ((v->EHINV << 15) |
160 (v->RI1 << 14) |
161 (v->RI0 << 13) |
162 (v->XI1 << 12) |
163 (v->XI0 << 11) |
164 (v->G << 10) |
165 (v->C0 << 7) |
166 (v->C1 << 4) |
167 (v->V0 << 3) |
168 (v->V1 << 2) |
169 (v->D0 << 1) |
170 (v->D1 << 0));
171
172 qemu_put_betls(f, &v->VPN);
173 qemu_put_be32s(f, &v->PageMask);
174 qemu_put_be16s(f, &asid);
175 qemu_put_be16s(f, &flags);
176 qemu_put_be64s(f, &v->PFN[0]);
177 qemu_put_be64s(f, &v->PFN[1]);
178}
179
180const VMStateInfo vmstate_info_tlb = {
181 .name = "tlb_entry",
182 .get = get_tlb,
183 .put = put_tlb,
184};
185
186#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \
187 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
188
189#define VMSTATE_TLB_ARRAY(_f, _s, _n) \
190 VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
191
192const VMStateDescription vmstate_tlb = {
193 .name = "cpu/tlb",
194 .version_id = 2,
195 .minimum_version_id = 2,
196 .fields = (VMStateField[]) {
197 VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
198 VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
199 VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
200 VMSTATE_END_OF_LIST()
201 }
202};
203
204
205
206const VMStateDescription vmstate_mips_cpu = {
207 .name = "cpu",
208 .version_id = 8,
209 .minimum_version_id = 8,
210 .post_load = cpu_post_load,
211 .fields = (VMStateField[]) {
212
213 VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
214
215
216 VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
217 CPUMIPSFPUContext),
218
219
220 VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
221 CPUMIPSMVPContext),
222
223
224 VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
225 CPUMIPSTLBContext),
226
227
228 VMSTATE_UINT32(env.current_tc, MIPSCPU),
229 VMSTATE_UINT32(env.current_fpu, MIPSCPU),
230 VMSTATE_INT32(env.error_code, MIPSCPU),
231 VMSTATE_UINTTL(env.btarget, MIPSCPU),
232 VMSTATE_UINTTL(env.bcond, MIPSCPU),
233
234
235 VMSTATE_INT32(env.CP0_Index, MIPSCPU),
236 VMSTATE_INT32(env.CP0_Random, MIPSCPU),
237 VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
238 VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
239 VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
240 VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
241 VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
242 VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
243 VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
244 VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
245 VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
246 VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
247 VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
248 VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
249 VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
250 VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
251 VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
252 VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
253 VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
254 VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
255 VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
256 VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
257 VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
258 VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
259 VMSTATE_INT32(env.CP0_Count, MIPSCPU),
260 VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
261 VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
262 VMSTATE_INT32(env.CP0_Status, MIPSCPU),
263 VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
264 VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
265 VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
266 VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
267 VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
268 VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
269 VMSTATE_INT32(env.CP0_EBase, MIPSCPU),
270 VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
271 VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
272 VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
273 VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
274 VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
275 VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
276 VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
277 VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
278 VMSTATE_UINT64(env.lladdr, MIPSCPU),
279 VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
280 VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
281 VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
282 VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
283 VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
284 VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
285 VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
286 VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
287 VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
288 VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
289 VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
290 VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
291 VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
292 VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
293
294
295 VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
296 vmstate_inactive_tc, TCState),
297 VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
298 vmstate_inactive_fpu, CPUMIPSFPUContext),
299
300 VMSTATE_END_OF_LIST()
301 },
302};
303
