LXR qemu/target-tilegx/cpu.c

   1/*
   2 * QEMU TILE-Gx CPU
   3 *
   4 *  Copyright (c) 2015 Chen Gang
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qapi/error.h"
  23#include "cpu.h"
  24#include "qemu-common.h"
  25#include "hw/qdev-properties.h"
  26#include "migration/vmstate.h"
  27#include "linux-user/syscall_defs.h"
  28#include "exec/exec-all.h"
  29
  30static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
  31                                  fprintf_function cpu_fprintf, int flags)
  32{
  33    static const char * const reg_names[TILEGX_R_COUNT] = {
  34         "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
  35         "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  36        "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  37        "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
  38        "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  39        "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  40        "r48", "r49", "r50", "r51",  "bp",  "tp",  "sp",  "lr"
  41    };
  42
  43    TileGXCPU *cpu = TILEGX_CPU(cs);
  44    CPUTLGState *env = &cpu->env;
  45    int i;
  46
  47    for (i = 0; i < TILEGX_R_COUNT; i++) {
  48        cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
  49                    reg_names[i], env->regs[i],
  50                    (i % 4) == 3 ? "\n" : " ");
  51    }
  52    cpu_fprintf(f, "PC  " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
  53                env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
  54}
  55
  56TileGXCPU *cpu_tilegx_init(const char *cpu_model)
  57{
  58    TileGXCPU *cpu;
  59
  60    cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
  61
  62    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
  63
  64    return cpu;
  65}
  66
  67static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
  68{
  69    TileGXCPU *cpu = TILEGX_CPU(cs);
  70
  71    cpu->env.pc = value;
  72}
  73
  74static bool tilegx_cpu_has_work(CPUState *cs)
  75{
  76    return true;
  77}
  78
  79static void tilegx_cpu_reset(CPUState *s)
  80{
  81    TileGXCPU *cpu = TILEGX_CPU(s);
  82    TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
  83    CPUTLGState *env = &cpu->env;
  84
  85    tcc->parent_reset(s);
  86
  87    memset(env, 0, sizeof(CPUTLGState));
  88    tlb_flush(s, 1);
  89}
  90
  91static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
  92{
  93    CPUState *cs = CPU(dev);
  94    TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
  95    Error *local_err = NULL;
  96
  97    cpu_exec_realizefn(cs, &local_err);
  98    if (local_err != NULL) {
  99        error_propagate(errp, local_err);
 100        return;
 101    }
 102
 103    cpu_reset(cs);
 104    qemu_init_vcpu(cs);
 105
 106    tcc->parent_realize(dev, errp);
 107}
 108
 109static void tilegx_cpu_initfn(Object *obj)
 110{
 111    CPUState *cs = CPU(obj);
 112    TileGXCPU *cpu = TILEGX_CPU(obj);
 113    CPUTLGState *env = &cpu->env;
 114    static bool tcg_initialized;
 115
 116    cs->env_ptr = env;
 117
 118    if (tcg_enabled() && !tcg_initialized) {
 119        tcg_initialized = true;
 120        tilegx_tcg_init();
 121    }
 122}
 123
 124static void tilegx_cpu_do_interrupt(CPUState *cs)
 125{
 126    cs->exception_index = -1;
 127}
 128
 129static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 130                                       int mmu_idx)
 131{
 132    TileGXCPU *cpu = TILEGX_CPU(cs);
 133
 134    /* The sigcode field will be filled in by do_signal in main.c.  */
 135    cs->exception_index = TILEGX_EXCP_SIGNAL;
 136    cpu->env.excaddr = address;
 137    cpu->env.signo = TARGET_SIGSEGV;
 138    cpu->env.sigcode = 0;
 139
 140    return 1;
 141}
 142
 143static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 144{
 145    if (interrupt_request & CPU_INTERRUPT_HARD) {
 146        tilegx_cpu_do_interrupt(cs);
 147        return true;
 148    }
 149    return false;
 150}
 151
 152static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
 153{
 154    DeviceClass *dc = DEVICE_CLASS(oc);
 155    CPUClass *cc = CPU_CLASS(oc);
 156    TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
 157
 158    tcc->parent_realize = dc->realize;
 159    dc->realize = tilegx_cpu_realizefn;
 160
 161    tcc->parent_reset = cc->reset;
 162    cc->reset = tilegx_cpu_reset;
 163
 164    cc->has_work = tilegx_cpu_has_work;
 165    cc->do_interrupt = tilegx_cpu_do_interrupt;
 166    cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
 167    cc->dump_state = tilegx_cpu_dump_state;
 168    cc->set_pc = tilegx_cpu_set_pc;
 169    cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
 170    cc->gdb_num_core_regs = 0;
 171}
 172
 173static const TypeInfo tilegx_cpu_type_info = {
 174    .name = TYPE_TILEGX_CPU,
 175    .parent = TYPE_CPU,
 176    .instance_size = sizeof(TileGXCPU),
 177    .instance_init = tilegx_cpu_initfn,
 178    .class_size = sizeof(TileGXCPUClass),
 179    .class_init = tilegx_cpu_class_init,
 180};
 181
 182static void tilegx_cpu_register_types(void)
 183{
 184    type_register_static(&tilegx_cpu_type_info);
 185}
 186
 187type_init(tilegx_cpu_register_types)
 188