LXR qemu/target-tricore/cpu.h

   1/*
   2 *  TriCore emulation for qemu: main CPU struct.
   3 *
   4 *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef TRICORE_CPU_H
  21#define TRICORE_CPU_H
  22
  23#include "tricore-defs.h"
  24#include "qemu-common.h"
  25#include "cpu-qom.h"
  26#include "exec/cpu-defs.h"
  27#include "fpu/softfloat.h"
  28
  29#define CPUArchState struct CPUTriCoreState
  30
  31struct CPUTriCoreState;
  32
  33struct tricore_boot_info;
  34
  35#define NB_MMU_MODES 3
  36
  37typedef struct tricore_def_t tricore_def_t;
  38
  39typedef struct CPUTriCoreState CPUTriCoreState;
  40struct CPUTriCoreState {
  41    /* GPR Register */
  42    uint32_t gpr_a[16];
  43    uint32_t gpr_d[16];
  44    /* CSFR Register */
  45    uint32_t PCXI;
  46/* Frequently accessed PSW_USB bits are stored separately for efficiency.
  47       This contains all the other bits.  Use psw_{read,write} to access
  48       the whole PSW.  */
  49    uint32_t PSW;
  50
  51    /* PSW flag cache for faster execution
  52    */
  53    uint32_t PSW_USB_C;
  54    uint32_t PSW_USB_V;   /* Only if bit 31 set, then flag is set  */
  55    uint32_t PSW_USB_SV;  /* Only if bit 31 set, then flag is set  */
  56    uint32_t PSW_USB_AV;  /* Only if bit 31 set, then flag is set. */
  57    uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
  58
  59    uint32_t PC;
  60    uint32_t SYSCON;
  61    uint32_t CPU_ID;
  62    uint32_t BIV;
  63    uint32_t BTV;
  64    uint32_t ISP;
  65    uint32_t ICR;
  66    uint32_t FCX;
  67    uint32_t LCX;
  68    uint32_t COMPAT;
  69
  70    /* Mem Protection Register */
  71    uint32_t DPR0_0L;
  72    uint32_t DPR0_0U;
  73    uint32_t DPR0_1L;
  74    uint32_t DPR0_1U;
  75    uint32_t DPR0_2L;
  76    uint32_t DPR0_2U;
  77    uint32_t DPR0_3L;
  78    uint32_t DPR0_3U;
  79
  80    uint32_t DPR1_0L;
  81    uint32_t DPR1_0U;
  82    uint32_t DPR1_1L;
  83    uint32_t DPR1_1U;
  84    uint32_t DPR1_2L;
  85    uint32_t DPR1_2U;
  86    uint32_t DPR1_3L;
  87    uint32_t DPR1_3U;
  88
  89    uint32_t DPR2_0L;
  90    uint32_t DPR2_0U;
  91    uint32_t DPR2_1L;
  92    uint32_t DPR2_1U;
  93    uint32_t DPR2_2L;
  94    uint32_t DPR2_2U;
  95    uint32_t DPR2_3L;
  96    uint32_t DPR2_3U;
  97
  98    uint32_t DPR3_0L;
  99    uint32_t DPR3_0U;
 100    uint32_t DPR3_1L;
 101    uint32_t DPR3_1U;
 102    uint32_t DPR3_2L;
 103    uint32_t DPR3_2U;
 104    uint32_t DPR3_3L;
 105    uint32_t DPR3_3U;
 106
 107    uint32_t CPR0_0L;
 108    uint32_t CPR0_0U;
 109    uint32_t CPR0_1L;
 110    uint32_t CPR0_1U;
 111    uint32_t CPR0_2L;
 112    uint32_t CPR0_2U;
 113    uint32_t CPR0_3L;
 114    uint32_t CPR0_3U;
 115
 116    uint32_t CPR1_0L;
 117    uint32_t CPR1_0U;
 118    uint32_t CPR1_1L;
 119    uint32_t CPR1_1U;
 120    uint32_t CPR1_2L;
 121    uint32_t CPR1_2U;
 122    uint32_t CPR1_3L;
 123    uint32_t CPR1_3U;
 124
 125    uint32_t CPR2_0L;
 126    uint32_t CPR2_0U;
 127    uint32_t CPR2_1L;
 128    uint32_t CPR2_1U;
 129    uint32_t CPR2_2L;
 130    uint32_t CPR2_2U;
 131    uint32_t CPR2_3L;
 132    uint32_t CPR2_3U;
 133
 134    uint32_t CPR3_0L;
 135    uint32_t CPR3_0U;
 136    uint32_t CPR3_1L;
 137    uint32_t CPR3_1U;
 138    uint32_t CPR3_2L;
 139    uint32_t CPR3_2U;
 140    uint32_t CPR3_3L;
 141    uint32_t CPR3_3U;
 142
 143    uint32_t DPM0;
 144    uint32_t DPM1;
 145    uint32_t DPM2;
 146    uint32_t DPM3;
 147
 148    uint32_t CPM0;
 149    uint32_t CPM1;
 150    uint32_t CPM2;
 151    uint32_t CPM3;
 152
 153    /* Memory Management Registers */
 154    uint32_t MMU_CON;
 155    uint32_t MMU_ASI;
 156    uint32_t MMU_TVA;
 157    uint32_t MMU_TPA;
 158    uint32_t MMU_TPX;
 159    uint32_t MMU_TFA;
 160    /* {1.3.1 only */
 161    uint32_t BMACON;
 162    uint32_t SMACON;
 163    uint32_t DIEAR;
 164    uint32_t DIETR;
 165    uint32_t CCDIER;
 166    uint32_t MIECON;
 167    uint32_t PIEAR;
 168    uint32_t PIETR;
 169    uint32_t CCPIER;
 170    /*} */
 171    /* Debug Registers */
 172    uint32_t DBGSR;
 173    uint32_t EXEVT;
 174    uint32_t CREVT;
 175    uint32_t SWEVT;
 176    uint32_t TR0EVT;
 177    uint32_t TR1EVT;
 178    uint32_t DMS;
 179    uint32_t DCX;
 180    uint32_t DBGTCR;
 181    uint32_t CCTRL;
 182    uint32_t CCNT;
 183    uint32_t ICNT;
 184    uint32_t M1CNT;
 185    uint32_t M2CNT;
 186    uint32_t M3CNT;
 187    /* Floating Point Registers */
 188    float_status fp_status;
 189    /* QEMU */
 190    int error_code;
 191    uint32_t hflags;    /* CPU State */
 192
 193    CPU_COMMON
 194
 195    /* Internal CPU feature flags.  */
 196    uint64_t features;
 197
 198    const tricore_def_t *cpu_model;
 199    void *irq[8];
 200    struct QEMUTimer *timer; /* Internal timer */
 201};
 202
 203/**
 204 * TriCoreCPU:
 205 * @env: #CPUTriCoreState
 206 *
 207 * A TriCore CPU.
 208 */
 209struct TriCoreCPU {
 210    /*< private >*/
 211    CPUState parent_obj;
 212    /*< public >*/
 213
 214    CPUTriCoreState env;
 215};
 216
 217static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCoreState *env)
 218{
 219    return TRICORE_CPU(container_of(env, TriCoreCPU, env));
 220}
 221
 222#define ENV_GET_CPU(e) CPU(tricore_env_get_cpu(e))
 223
 224#define ENV_OFFSET offsetof(TriCoreCPU, env)
 225
 226hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 227void tricore_cpu_dump_state(CPUState *cpu, FILE *f,
 228                            fprintf_function cpu_fprintf, int flags);
 229
 230
 231#define MASK_PCXI_PCPN 0xff000000
 232#define MASK_PCXI_PIE  0x00800000
 233#define MASK_PCXI_UL   0x00400000
 234#define MASK_PCXI_PCXS 0x000f0000
 235#define MASK_PCXI_PCXO 0x0000ffff
 236
 237#define MASK_PSW_USB 0xff000000
 238#define MASK_USB_C   0x80000000
 239#define MASK_USB_V   0x40000000
 240#define MASK_USB_SV  0x20000000
 241#define MASK_USB_AV  0x10000000
 242#define MASK_USB_SAV 0x08000000
 243#define MASK_PSW_PRS 0x00003000
 244#define MASK_PSW_IO  0x00000c00
 245#define MASK_PSW_IS  0x00000200
 246#define MASK_PSW_GW  0x00000100
 247#define MASK_PSW_CDE 0x00000080
 248#define MASK_PSW_CDC 0x0000007f
 249#define MASK_PSW_FPU_RM 0x3000000
 250
 251#define MASK_SYSCON_PRO_TEN 0x2
 252#define MASK_SYSCON_FCD_SF  0x1
 253
 254#define MASK_CPUID_MOD     0xffff0000
 255#define MASK_CPUID_MOD_32B 0x0000ff00
 256#define MASK_CPUID_REV     0x000000ff
 257
 258#define MASK_ICR_PIPN 0x00ff0000
 259#define MASK_ICR_IE   0x00000100
 260#define MASK_ICR_CCPN 0x000000ff
 261
 262#define MASK_FCX_FCXS 0x000f0000
 263#define MASK_FCX_FCXO 0x0000ffff
 264
 265#define MASK_LCX_LCXS 0x000f0000
 266#define MASK_LCX_LCX0 0x0000ffff
 267
 268#define MASK_DBGSR_DE 0x1
 269#define MASK_DBGSR_HALT 0x6
 270#define MASK_DBGSR_SUSP 0x10
 271#define MASK_DBGSR_PREVSUSP 0x20
 272#define MASK_DBGSR_PEVT 0x40
 273#define MASK_DBGSR_EVTSRC 0x1f00
 274
 275#define TRICORE_HFLAG_KUU     0x3
 276#define TRICORE_HFLAG_UM0     0x00002 /* user mode-0 flag          */
 277#define TRICORE_HFLAG_UM1     0x00001 /* user mode-1 flag          */
 278#define TRICORE_HFLAG_SM      0x00000 /* kernel mode flag          */
 279
 280enum tricore_features {
 281    TRICORE_FEATURE_13,
 282    TRICORE_FEATURE_131,
 283    TRICORE_FEATURE_16,
 284    TRICORE_FEATURE_161,
 285};
 286
 287static inline int tricore_feature(CPUTriCoreState *env, int feature)
 288{
 289    return (env->features & (1ULL << feature)) != 0;
 290}
 291
 292/* TriCore Traps Classes*/
 293enum {
 294    TRAPC_NONE     = -1,
 295    TRAPC_MMU      = 0,
 296    TRAPC_PROT     = 1,
 297    TRAPC_INSN_ERR = 2,
 298    TRAPC_CTX_MNG  = 3,
 299    TRAPC_SYSBUS   = 4,
 300    TRAPC_ASSERT   = 5,
 301    TRAPC_SYSCALL  = 6,
 302    TRAPC_NMI      = 7,
 303    TRAPC_IRQ      = 8
 304};
 305
 306/* Class 0 TIN */
 307enum {
 308    TIN0_VAF = 0,
 309    TIN0_VAP = 1,
 310};
 311
 312/* Class 1 TIN */
 313enum {
 314    TIN1_PRIV = 1,
 315    TIN1_MPR  = 2,
 316    TIN1_MPW  = 3,
 317    TIN1_MPX  = 4,
 318    TIN1_MPP  = 5,
 319    TIN1_MPN  = 6,
 320    TIN1_GRWP = 7,
 321};
 322
 323/* Class 2 TIN */
 324enum {
 325    TIN2_IOPC = 1,
 326    TIN2_UOPC = 2,
 327    TIN2_OPD  = 3,
 328    TIN2_ALN  = 4,
 329    TIN2_MEM  = 5,
 330};
 331
 332/* Class 3 TIN */
 333enum {
 334    TIN3_FCD  = 1,
 335    TIN3_CDO  = 2,
 336    TIN3_CDU  = 3,
 337    TIN3_FCU  = 4,
 338    TIN3_CSU  = 5,
 339    TIN3_CTYP = 6,
 340    TIN3_NEST = 7,
 341};
 342
 343/* Class 4 TIN */
 344enum {
 345    TIN4_PSE = 1,
 346    TIN4_DSE = 2,
 347    TIN4_DAE = 3,
 348    TIN4_CAE = 4,
 349    TIN4_PIE = 5,
 350    TIN4_DIE = 6,
 351};
 352
 353/* Class 5 TIN */
 354enum {
 355    TIN5_OVF  = 1,
 356    TIN5_SOVF = 1,
 357};
 358
 359/* Class 6 TIN
 360 *
 361 * Is always TIN6_SYS
 362 */
 363
 364/* Class 7 TIN */
 365enum {
 366    TIN7_NMI = 0,
 367};
 368
 369uint32_t psw_read(CPUTriCoreState *env);
 370void psw_write(CPUTriCoreState *env, uint32_t val);
 371
 372void fpu_set_state(CPUTriCoreState *env);
 373
 374#define MMU_USER_IDX 2
 375
 376void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 377
 378#define cpu_signal_handler cpu_tricore_signal_handler
 379#define cpu_list tricore_cpu_list
 380
 381static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
 382{
 383    return 0;
 384}
 385
 386
 387
 388#include "exec/cpu-all.h"
 389
 390enum {
 391    /* 1 bit to define user level / supervisor access */
 392    ACCESS_USER  = 0x00,
 393    ACCESS_SUPER = 0x01,
 394    /* 1 bit to indicate direction */
 395    ACCESS_STORE = 0x02,
 396    /* Type of instruction that generated the access */
 397    ACCESS_CODE  = 0x10, /* Code fetch access                */
 398    ACCESS_INT   = 0x20, /* Integer load/store access        */
 399    ACCESS_FLOAT = 0x30, /* floating point load/store access */
 400};
 401
 402void cpu_state_reset(CPUTriCoreState *s);
 403void tricore_tcg_init(void);
 404int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);
 405
 406static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc,
 407                                        target_ulong *cs_base, uint32_t *flags)
 408{
 409    *pc = env->PC;
 410    *cs_base = 0;
 411    *flags = 0;
 412}
 413
 414TriCoreCPU *cpu_tricore_init(const char *cpu_model);
 415
 416#define cpu_init(cpu_model) CPU(cpu_tricore_init(cpu_model))
 417
 418
 419/* helpers.c */
 420int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address,
 421                                 int rw, int mmu_idx);
 422#define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault
 423
 424#endif /* TRICORE_CPU_H */
 425