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26#ifndef IA64_TCG_TARGET_H
27#define IA64_TCG_TARGET_H
28
29#define TCG_TARGET_INSN_UNIT_SIZE 16
30#define TCG_TARGET_TLB_DISPLACEMENT_BITS 21
31
32typedef struct {
33 uint64_t lo __attribute__((aligned(16)));
34 uint64_t hi;
35} tcg_insn_unit;
36
37
38#define TCG_TARGET_NB_REGS 64
39typedef enum {
40 TCG_REG_R0 = 0,
41 TCG_REG_R1,
42 TCG_REG_R2,
43 TCG_REG_R3,
44 TCG_REG_R4,
45 TCG_REG_R5,
46 TCG_REG_R6,
47 TCG_REG_R7,
48 TCG_REG_R8,
49 TCG_REG_R9,
50 TCG_REG_R10,
51 TCG_REG_R11,
52 TCG_REG_R12,
53 TCG_REG_R13,
54 TCG_REG_R14,
55 TCG_REG_R15,
56 TCG_REG_R16,
57 TCG_REG_R17,
58 TCG_REG_R18,
59 TCG_REG_R19,
60 TCG_REG_R20,
61 TCG_REG_R21,
62 TCG_REG_R22,
63 TCG_REG_R23,
64 TCG_REG_R24,
65 TCG_REG_R25,
66 TCG_REG_R26,
67 TCG_REG_R27,
68 TCG_REG_R28,
69 TCG_REG_R29,
70 TCG_REG_R30,
71 TCG_REG_R31,
72 TCG_REG_R32,
73 TCG_REG_R33,
74 TCG_REG_R34,
75 TCG_REG_R35,
76 TCG_REG_R36,
77 TCG_REG_R37,
78 TCG_REG_R38,
79 TCG_REG_R39,
80 TCG_REG_R40,
81 TCG_REG_R41,
82 TCG_REG_R42,
83 TCG_REG_R43,
84 TCG_REG_R44,
85 TCG_REG_R45,
86 TCG_REG_R46,
87 TCG_REG_R47,
88 TCG_REG_R48,
89 TCG_REG_R49,
90 TCG_REG_R50,
91 TCG_REG_R51,
92 TCG_REG_R52,
93 TCG_REG_R53,
94 TCG_REG_R54,
95 TCG_REG_R55,
96 TCG_REG_R56,
97 TCG_REG_R57,
98 TCG_REG_R58,
99 TCG_REG_R59,
100 TCG_REG_R60,
101 TCG_REG_R61,
102 TCG_REG_R62,
103 TCG_REG_R63,
104
105 TCG_AREG0 = TCG_REG_R32,
106} TCGReg;
107
108#define TCG_CT_CONST_ZERO 0x100
109#define TCG_CT_CONST_S22 0x200
110
111
112#define TCG_REG_CALL_STACK TCG_REG_R12
113#define TCG_TARGET_STACK_ALIGN 16
114#define TCG_TARGET_CALL_STACK_OFFSET 16
115
116
117#define TCG_TARGET_HAS_div_i32 0
118#define TCG_TARGET_HAS_rem_i32 0
119#define TCG_TARGET_HAS_div_i64 0
120#define TCG_TARGET_HAS_rem_i64 0
121#define TCG_TARGET_HAS_andc_i32 1
122#define TCG_TARGET_HAS_andc_i64 1
123#define TCG_TARGET_HAS_bswap16_i32 1
124#define TCG_TARGET_HAS_bswap16_i64 1
125#define TCG_TARGET_HAS_bswap32_i32 1
126#define TCG_TARGET_HAS_bswap32_i64 1
127#define TCG_TARGET_HAS_bswap64_i64 1
128#define TCG_TARGET_HAS_eqv_i32 1
129#define TCG_TARGET_HAS_eqv_i64 1
130#define TCG_TARGET_HAS_ext8s_i32 1
131#define TCG_TARGET_HAS_ext16s_i32 1
132#define TCG_TARGET_HAS_ext8s_i64 1
133#define TCG_TARGET_HAS_ext16s_i64 1
134#define TCG_TARGET_HAS_ext32s_i64 1
135#define TCG_TARGET_HAS_ext8u_i32 1
136#define TCG_TARGET_HAS_ext16u_i32 1
137#define TCG_TARGET_HAS_ext8u_i64 1
138#define TCG_TARGET_HAS_ext16u_i64 1
139#define TCG_TARGET_HAS_ext32u_i64 1
140#define TCG_TARGET_HAS_nand_i32 1
141#define TCG_TARGET_HAS_nand_i64 1
142#define TCG_TARGET_HAS_nor_i32 1
143#define TCG_TARGET_HAS_nor_i64 1
144#define TCG_TARGET_HAS_orc_i32 1
145#define TCG_TARGET_HAS_orc_i64 1
146#define TCG_TARGET_HAS_rot_i32 1
147#define TCG_TARGET_HAS_rot_i64 1
148#define TCG_TARGET_HAS_movcond_i32 1
149#define TCG_TARGET_HAS_movcond_i64 1
150#define TCG_TARGET_HAS_deposit_i32 1
151#define TCG_TARGET_HAS_deposit_i64 1
152#define TCG_TARGET_HAS_add2_i32 0
153#define TCG_TARGET_HAS_add2_i64 0
154#define TCG_TARGET_HAS_sub2_i32 0
155#define TCG_TARGET_HAS_sub2_i64 0
156#define TCG_TARGET_HAS_mulu2_i32 0
157#define TCG_TARGET_HAS_mulu2_i64 0
158#define TCG_TARGET_HAS_muls2_i32 0
159#define TCG_TARGET_HAS_muls2_i64 0
160#define TCG_TARGET_HAS_muluh_i32 0
161#define TCG_TARGET_HAS_muluh_i64 0
162#define TCG_TARGET_HAS_mulsh_i32 0
163#define TCG_TARGET_HAS_mulsh_i64 0
164#define TCG_TARGET_HAS_extrl_i64_i32 0
165#define TCG_TARGET_HAS_extrh_i64_i32 0
166
167#define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <= 16)
168#define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <= 16)
169
170
171#define TCG_TARGET_HAS_neg_i32 0
172#define TCG_TARGET_HAS_neg_i64 0
173#define TCG_TARGET_HAS_not_i32 0
174#define TCG_TARGET_HAS_not_i64 0
175
176static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
177{
178 start = start & ~(32UL - 1UL);
179 stop = (stop + (32UL - 1UL)) & ~(32UL - 1UL);
180
181 for (; start < stop; start += 32UL) {
182 asm volatile ("fc.i %0" :: "r" (start));
183 }
184 asm volatile (";;sync.i;;srlz.i;;");
185}
186
187#endif
188