LXR qemu/tests/e1000e-test.c

   1 /*
   2 * QTest testcase for e1000e NIC
   3 *
   4 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
   5 * Developed by Daynix Computing LTD (http://www.daynix.com)
   6 *
   7 * Authors:
   8 * Dmitry Fleytman <dmitry@daynix.com>
   9 * Leonid Bloch <leonid@daynix.com>
  10 * Yan Vugenfirer <yan@daynix.com>
  11 *
  12 * This library is free software; you can redistribute it and/or
  13 * modify it under the terms of the GNU Lesser General Public
  14 * License as published by the Free Software Foundation; either
  15 * version 2 of the License, or (at your option) any later version.
  16 *
  17 * This library is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20 * Lesser General Public License for more details.
  21 *
  22 * You should have received a copy of the GNU Lesser General Public
  23 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  24 */
  25
  26
  27#include "qemu/osdep.h"
  28#include "libqtest.h"
  29#include "qemu-common.h"
  30#include "libqos/pci-pc.h"
  31#include "qemu/sockets.h"
  32#include "qemu/iov.h"
  33#include "qemu/bitops.h"
  34#include "libqos/malloc.h"
  35#include "libqos/malloc-pc.h"
  36#include "libqos/malloc-generic.h"
  37
  38#define E1000E_IMS      (0x00d0)
  39
  40#define E1000E_STATUS   (0x0008)
  41#define E1000E_STATUS_LU BIT(1)
  42#define E1000E_STATUS_ASDV1000 BIT(9)
  43
  44#define E1000E_CTRL     (0x0000)
  45#define E1000E_CTRL_RESET BIT(26)
  46
  47#define E1000E_RCTL     (0x0100)
  48#define E1000E_RCTL_EN  BIT(1)
  49#define E1000E_RCTL_UPE BIT(3)
  50#define E1000E_RCTL_MPE BIT(4)
  51
  52#define E1000E_RFCTL     (0x5008)
  53#define E1000E_RFCTL_EXTEN  BIT(15)
  54
  55#define E1000E_TCTL     (0x0400)
  56#define E1000E_TCTL_EN  BIT(1)
  57
  58#define E1000E_CTRL_EXT             (0x0018)
  59#define E1000E_CTRL_EXT_DRV_LOAD    BIT(28)
  60#define E1000E_CTRL_EXT_TXLSFLOW    BIT(22)
  61
  62#define E1000E_RX0_MSG_ID           (0)
  63#define E1000E_TX0_MSG_ID           (1)
  64#define E1000E_OTHER_MSG_ID         (2)
  65
  66#define E1000E_IVAR                 (0x00E4)
  67#define E1000E_IVAR_TEST_CFG        ((E1000E_RX0_MSG_ID << 0)    | BIT(3)  | \
  68                                     (E1000E_TX0_MSG_ID << 8)    | BIT(11) | \
  69                                     (E1000E_OTHER_MSG_ID << 16) | BIT(19) | \
  70                                     BIT(31))
  71
  72#define E1000E_RING_LEN             (0x1000)
  73#define E1000E_TXD_LEN              (16)
  74#define E1000E_RXD_LEN              (16)
  75
  76#define E1000E_TDBAL    (0x3800)
  77#define E1000E_TDBAH    (0x3804)
  78#define E1000E_TDLEN    (0x3808)
  79#define E1000E_TDH      (0x3810)
  80#define E1000E_TDT      (0x3818)
  81
  82#define E1000E_RDBAL    (0x2800)
  83#define E1000E_RDBAH    (0x2804)
  84#define E1000E_RDLEN    (0x2808)
  85#define E1000E_RDH      (0x2810)
  86#define E1000E_RDT      (0x2818)
  87
  88typedef struct e1000e_device {
  89    QPCIDevice *pci_dev;
  90    QPCIBar mac_regs;
  91
  92    uint64_t tx_ring;
  93    uint64_t rx_ring;
  94} e1000e_device;
  95
  96static int test_sockets[2];
  97static QGuestAllocator *test_alloc;
  98static QPCIBus *test_bus;
  99
 100static void e1000e_pci_foreach_callback(QPCIDevice *dev, int devfn, void *data)
 101{
 102    *(QPCIDevice **) data = dev;
 103}
 104
 105static QPCIDevice *e1000e_device_find(QPCIBus *bus)
 106{
 107    static const int e1000e_vendor_id = 0x8086;
 108    static const int e1000e_dev_id = 0x10D3;
 109
 110    QPCIDevice *e1000e_dev = NULL;
 111
 112    qpci_device_foreach(bus, e1000e_vendor_id, e1000e_dev_id,
 113        e1000e_pci_foreach_callback, &e1000e_dev);
 114
 115    g_assert_nonnull(e1000e_dev);
 116
 117    return e1000e_dev;
 118}
 119
 120static void e1000e_macreg_write(e1000e_device *d, uint32_t reg, uint32_t val)
 121{
 122    qpci_io_writel(d->pci_dev, d->mac_regs, reg, val);
 123}
 124
 125static uint32_t e1000e_macreg_read(e1000e_device *d, uint32_t reg)
 126{
 127    return qpci_io_readl(d->pci_dev, d->mac_regs, reg);
 128}
 129
 130static void e1000e_device_init(QPCIBus *bus, e1000e_device *d)
 131{
 132    uint32_t val;
 133
 134    d->pci_dev = e1000e_device_find(bus);
 135
 136    /* Enable the device */
 137    qpci_device_enable(d->pci_dev);
 138
 139    /* Map BAR0 (mac registers) */
 140    d->mac_regs = qpci_iomap(d->pci_dev, 0, NULL);
 141
 142    /* Reset the device */
 143    val = e1000e_macreg_read(d, E1000E_CTRL);
 144    e1000e_macreg_write(d, E1000E_CTRL, val | E1000E_CTRL_RESET);
 145
 146    /* Enable and configure MSI-X */
 147    qpci_msix_enable(d->pci_dev);
 148    e1000e_macreg_write(d, E1000E_IVAR, E1000E_IVAR_TEST_CFG);
 149
 150    /* Check the device status - link and speed */
 151    val = e1000e_macreg_read(d, E1000E_STATUS);
 152    g_assert_cmphex(val & (E1000E_STATUS_LU | E1000E_STATUS_ASDV1000),
 153        ==, E1000E_STATUS_LU | E1000E_STATUS_ASDV1000);
 154
 155    /* Initialize TX/RX logic */
 156    e1000e_macreg_write(d, E1000E_RCTL, 0);
 157    e1000e_macreg_write(d, E1000E_TCTL, 0);
 158
 159    /* Notify the device that the driver is ready */
 160    val = e1000e_macreg_read(d, E1000E_CTRL_EXT);
 161    e1000e_macreg_write(d, E1000E_CTRL_EXT,
 162        val | E1000E_CTRL_EXT_DRV_LOAD | E1000E_CTRL_EXT_TXLSFLOW);
 163
 164    /* Allocate and setup TX ring */
 165    d->tx_ring = guest_alloc(test_alloc, E1000E_RING_LEN);
 166    g_assert(d->tx_ring != 0);
 167
 168    e1000e_macreg_write(d, E1000E_TDBAL, (uint32_t) d->tx_ring);
 169    e1000e_macreg_write(d, E1000E_TDBAH, (uint32_t) (d->tx_ring >> 32));
 170    e1000e_macreg_write(d, E1000E_TDLEN, E1000E_RING_LEN);
 171    e1000e_macreg_write(d, E1000E_TDT, 0);
 172    e1000e_macreg_write(d, E1000E_TDH, 0);
 173
 174    /* Enable transmit */
 175    e1000e_macreg_write(d, E1000E_TCTL, E1000E_TCTL_EN);
 176
 177    /* Allocate and setup RX ring */
 178    d->rx_ring = guest_alloc(test_alloc, E1000E_RING_LEN);
 179    g_assert(d->rx_ring != 0);
 180
 181    e1000e_macreg_write(d, E1000E_RDBAL, (uint32_t)d->rx_ring);
 182    e1000e_macreg_write(d, E1000E_RDBAH, (uint32_t)(d->rx_ring >> 32));
 183    e1000e_macreg_write(d, E1000E_RDLEN, E1000E_RING_LEN);
 184    e1000e_macreg_write(d, E1000E_RDT, 0);
 185    e1000e_macreg_write(d, E1000E_RDH, 0);
 186
 187    /* Enable receive */
 188    e1000e_macreg_write(d, E1000E_RFCTL, E1000E_RFCTL_EXTEN);
 189    e1000e_macreg_write(d, E1000E_RCTL, E1000E_RCTL_EN  |
 190                                        E1000E_RCTL_UPE |
 191                                        E1000E_RCTL_MPE);
 192
 193    /* Enable all interrupts */
 194    e1000e_macreg_write(d, E1000E_IMS, 0xFFFFFFFF);
 195}
 196
 197static void e1000e_tx_ring_push(e1000e_device *d, void *descr)
 198{
 199    uint32_t tail = e1000e_macreg_read(d, E1000E_TDT);
 200    uint32_t len = e1000e_macreg_read(d, E1000E_TDLEN) / E1000E_TXD_LEN;
 201
 202    memwrite(d->tx_ring + tail * E1000E_TXD_LEN, descr, E1000E_TXD_LEN);
 203    e1000e_macreg_write(d, E1000E_TDT, (tail + 1) % len);
 204
 205    /* Read WB data for the packet transmitted */
 206    memread(d->tx_ring + tail * E1000E_TXD_LEN, descr, E1000E_TXD_LEN);
 207}
 208
 209static void e1000e_rx_ring_push(e1000e_device *d, void *descr)
 210{
 211    uint32_t tail = e1000e_macreg_read(d, E1000E_RDT);
 212    uint32_t len = e1000e_macreg_read(d, E1000E_RDLEN) / E1000E_RXD_LEN;
 213
 214    memwrite(d->rx_ring + tail * E1000E_RXD_LEN, descr, E1000E_RXD_LEN);
 215    e1000e_macreg_write(d, E1000E_RDT, (tail + 1) % len);
 216
 217    /* Read WB data for the packet received */
 218    memread(d->rx_ring + tail * E1000E_RXD_LEN, descr, E1000E_RXD_LEN);
 219}
 220
 221static void e1000e_wait_isr(e1000e_device *d, uint16_t msg_id)
 222{
 223    guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
 224
 225    do {
 226        if (qpci_msix_pending(d->pci_dev, msg_id)) {
 227            return;
 228        }
 229        clock_step(10000);
 230    } while (g_get_monotonic_time() < end_time);
 231
 232    g_error("Timeout expired");
 233}
 234
 235static void e1000e_send_verify(e1000e_device *d)
 236{
 237    struct {
 238        uint64_t buffer_addr;
 239        union {
 240            uint32_t data;
 241            struct {
 242                uint16_t length;
 243                uint8_t cso;
 244                uint8_t cmd;
 245            } flags;
 246        } lower;
 247        union {
 248            uint32_t data;
 249            struct {
 250                uint8_t status;
 251                uint8_t css;
 252                uint16_t special;
 253            } fields;
 254        } upper;
 255    } descr;
 256
 257    static const uint32_t dtyp_data = BIT(20);
 258    static const uint32_t dtyp_ext  = BIT(29);
 259    static const uint32_t dcmd_rs   = BIT(27);
 260    static const uint32_t dcmd_eop  = BIT(24);
 261    static const uint32_t dsta_dd   = BIT(0);
 262    static const int data_len = 64;
 263    char buffer[64];
 264    int ret;
 265    uint32_t recv_len;
 266
 267    /* Prepare test data buffer */
 268    uint64_t data = guest_alloc(test_alloc, data_len);
 269    memwrite(data, "TEST", 5);
 270
 271    /* Prepare TX descriptor */
 272    memset(&descr, 0, sizeof(descr));
 273    descr.buffer_addr = cpu_to_le64(data);
 274    descr.lower.data = cpu_to_le32(dcmd_rs   |
 275                                   dcmd_eop  |
 276                                   dtyp_ext  |
 277                                   dtyp_data |
 278                                   data_len);
 279
 280    /* Put descriptor to the ring */
 281    e1000e_tx_ring_push(d, &descr);
 282
 283    /* Wait for TX WB interrupt */
 284    e1000e_wait_isr(d, E1000E_TX0_MSG_ID);
 285
 286    /* Check DD bit */
 287    g_assert_cmphex(le32_to_cpu(descr.upper.data) & dsta_dd, ==, dsta_dd);
 288
 289    /* Check data sent to the backend */
 290    ret = qemu_recv(test_sockets[0], &recv_len, sizeof(recv_len), 0);
 291    g_assert_cmpint(ret, == , sizeof(recv_len));
 292    qemu_recv(test_sockets[0], buffer, 64, 0);
 293    g_assert_cmpstr(buffer, == , "TEST");
 294
 295    /* Free test data buffer */
 296    guest_free(test_alloc, data);
 297}
 298
 299static void e1000e_receive_verify(e1000e_device *d)
 300{
 301    union {
 302        struct {
 303            uint64_t buffer_addr;
 304            uint64_t reserved;
 305        } read;
 306        struct {
 307            struct {
 308                uint32_t mrq;
 309                union {
 310                    uint32_t rss;
 311                    struct {
 312                        uint16_t ip_id;
 313                        uint16_t csum;
 314                    } csum_ip;
 315                } hi_dword;
 316            } lower;
 317            struct {
 318                uint32_t status_error;
 319                uint16_t length;
 320                uint16_t vlan;
 321            } upper;
 322        } wb;
 323    } descr;
 324
 325    static const uint32_t esta_dd = BIT(0);
 326
 327    char test[] = "TEST";
 328    int len = htonl(sizeof(test));
 329    struct iovec iov[] = {
 330        {
 331            .iov_base = &len,
 332            .iov_len = sizeof(len),
 333        },{
 334            .iov_base = test,
 335            .iov_len = sizeof(test),
 336        },
 337    };
 338
 339    static const int data_len = 64;
 340    char buffer[64];
 341    int ret;
 342
 343    /* Send a dummy packet to device's socket*/
 344    ret = iov_send(test_sockets[0], iov, 2, 0, sizeof(len) + sizeof(test));
 345    g_assert_cmpint(ret, == , sizeof(test) + sizeof(len));
 346
 347    /* Prepare test data buffer */
 348    uint64_t data = guest_alloc(test_alloc, data_len);
 349
 350    /* Prepare RX descriptor */
 351    memset(&descr, 0, sizeof(descr));
 352    descr.read.buffer_addr = cpu_to_le64(data);
 353
 354    /* Put descriptor to the ring */
 355    e1000e_rx_ring_push(d, &descr);
 356
 357    /* Wait for TX WB interrupt */
 358    e1000e_wait_isr(d, E1000E_RX0_MSG_ID);
 359
 360    /* Check DD bit */
 361    g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) &
 362        esta_dd, ==, esta_dd);
 363
 364    /* Check data sent to the backend */
 365    memread(data, buffer, sizeof(buffer));
 366    g_assert_cmpstr(buffer, == , "TEST");
 367
 368    /* Free test data buffer */
 369    guest_free(test_alloc, data);
 370}
 371
 372static void e1000e_device_clear(QPCIBus *bus, e1000e_device *d)
 373{
 374    qpci_iounmap(d->pci_dev, d->mac_regs);
 375    qpci_msix_disable(d->pci_dev);
 376}
 377
 378static void data_test_init(e1000e_device *d)
 379{
 380    char *cmdline;
 381
 382    int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets);
 383    g_assert_cmpint(ret, != , -1);
 384
 385    cmdline = g_strdup_printf("-netdev socket,fd=%d,id=hs0 "
 386                              "-device e1000e,netdev=hs0", test_sockets[1]);
 387    g_assert_nonnull(cmdline);
 388
 389    qtest_start(cmdline);
 390    g_free(cmdline);
 391
 392    test_bus = qpci_init_pc(NULL);
 393    g_assert_nonnull(test_bus);
 394
 395    test_alloc = pc_alloc_init();
 396    g_assert_nonnull(test_alloc);
 397
 398    e1000e_device_init(test_bus, d);
 399}
 400
 401static void data_test_clear(e1000e_device *d)
 402{
 403    e1000e_device_clear(test_bus, d);
 404    close(test_sockets[0]);
 405    pc_alloc_uninit(test_alloc);
 406    qpci_free_pc(test_bus);
 407    qtest_end();
 408}
 409
 410static void test_e1000e_init(gconstpointer data)
 411{
 412    e1000e_device d;
 413
 414    data_test_init(&d);
 415    data_test_clear(&d);
 416}
 417
 418static void test_e1000e_tx(gconstpointer data)
 419{
 420    e1000e_device d;
 421
 422    data_test_init(&d);
 423    e1000e_send_verify(&d);
 424    data_test_clear(&d);
 425}
 426
 427static void test_e1000e_rx(gconstpointer data)
 428{
 429    e1000e_device d;
 430
 431    data_test_init(&d);
 432    e1000e_receive_verify(&d);
 433    data_test_clear(&d);
 434}
 435
 436static void test_e1000e_multiple_transfers(gconstpointer data)
 437{
 438    static const long iterations = 4 * 1024;
 439    long i;
 440
 441    e1000e_device d;
 442
 443    data_test_init(&d);
 444
 445    for (i = 0; i < iterations; i++) {
 446        e1000e_send_verify(&d);
 447        e1000e_receive_verify(&d);
 448    }
 449
 450    data_test_clear(&d);
 451}
 452
 453static void test_e1000e_hotplug(gconstpointer data)
 454{
 455    static const uint8_t slot = 0x06;
 456
 457    qtest_start("-device e1000e");
 458
 459    qpci_plug_device_test("e1000e", "e1000e_net", slot, NULL);
 460    qpci_unplug_acpi_device_test("e1000e_net", slot);
 461
 462    qtest_end();
 463}
 464
 465int main(int argc, char **argv)
 466{
 467    g_test_init(&argc, &argv, NULL);
 468
 469    qtest_add_data_func("e1000e/init", NULL, test_e1000e_init);
 470    qtest_add_data_func("e1000e/tx", NULL, test_e1000e_tx);
 471    qtest_add_data_func("e1000e/rx", NULL, test_e1000e_rx);
 472    qtest_add_data_func("e1000e/multiple_transfers", NULL,
 473        test_e1000e_multiple_transfers);
 474    qtest_add_data_func("e1000e/hotplug", NULL, test_e1000e_hotplug);
 475
 476    return g_test_run();
 477}
 478