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21#include "qemu/osdep.h"
22#include "hw/hw.h"
23#include "hw/pci/pci.h"
24#include "sysemu/dma.h"
25#include "sysemu/block-backend.h"
26#include "hw/pci/msi.h"
27#include "hw/pci/msix.h"
28#include "qemu/iov.h"
29#include "hw/scsi/scsi.h"
30#include "block/scsi.h"
31#include "trace.h"
32#include "qapi/error.h"
33#include "mfi.h"
34
35#define MEGASAS_VERSION_GEN1 "1.70"
36#define MEGASAS_VERSION_GEN2 "1.80"
37#define MEGASAS_MAX_FRAMES 2048
38#define MEGASAS_DEFAULT_FRAMES 1000
39#define MEGASAS_GEN2_DEFAULT_FRAMES 1008
40#define MEGASAS_MAX_SGE 128
41#define MEGASAS_DEFAULT_SGE 80
42#define MEGASAS_MAX_SECTORS 0xFFFF
43#define MEGASAS_MAX_ARRAYS 128
44
45#define MEGASAS_HBA_SERIAL "QEMU123456"
46#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
47#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
48
49#define MEGASAS_FLAG_USE_JBOD 0
50#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
51#define MEGASAS_FLAG_USE_QUEUE64 1
52#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
53
54static const char *mfi_frame_desc[] = {
55 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
56 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
57
58typedef struct MegasasCmd {
59 uint32_t index;
60 uint16_t flags;
61 uint16_t count;
62 uint64_t context;
63
64 hwaddr pa;
65 hwaddr pa_size;
66 uint32_t dcmd_opcode;
67 union mfi_frame *frame;
68 SCSIRequest *req;
69 QEMUSGList qsg;
70 void *iov_buf;
71 size_t iov_size;
72 size_t iov_offset;
73 struct MegasasState *state;
74} MegasasCmd;
75
76typedef struct MegasasState {
77
78 PCIDevice parent_obj;
79
80
81 MemoryRegion mmio_io;
82 MemoryRegion port_io;
83 MemoryRegion queue_io;
84 uint32_t frame_hi;
85
86 int fw_state;
87 uint32_t fw_sge;
88 uint32_t fw_cmds;
89 uint32_t flags;
90 int fw_luns;
91 int intr_mask;
92 int doorbell;
93 int busy;
94 int diag;
95 int adp_reset;
96 OnOffAuto msi;
97 OnOffAuto msix;
98
99 MegasasCmd *event_cmd;
100 int event_locale;
101 int event_class;
102 int event_count;
103 int shutdown_event;
104 int boot_event;
105
106 uint64_t sas_addr;
107 char *hba_serial;
108
109 uint64_t reply_queue_pa;
110 void *reply_queue;
111 int reply_queue_len;
112 int reply_queue_head;
113 int reply_queue_tail;
114 uint64_t consumer_pa;
115 uint64_t producer_pa;
116
117 MegasasCmd frames[MEGASAS_MAX_FRAMES];
118 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
119 SCSIBus bus;
120} MegasasState;
121
122typedef struct MegasasBaseClass {
123 PCIDeviceClass parent_class;
124 const char *product_name;
125 const char *product_version;
126 int mmio_bar;
127 int ioport_bar;
128 int osts;
129} MegasasBaseClass;
130
131#define TYPE_MEGASAS_BASE "megasas-base"
132#define TYPE_MEGASAS_GEN1 "megasas"
133#define TYPE_MEGASAS_GEN2 "megasas-gen2"
134
135#define MEGASAS(obj) \
136 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
137
138#define MEGASAS_DEVICE_CLASS(oc) \
139 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
140#define MEGASAS_DEVICE_GET_CLASS(oc) \
141 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
142
143#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
144
145static bool megasas_intr_enabled(MegasasState *s)
146{
147 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
148 MEGASAS_INTR_DISABLED_MASK) {
149 return true;
150 }
151 return false;
152}
153
154static bool megasas_use_queue64(MegasasState *s)
155{
156 return s->flags & MEGASAS_MASK_USE_QUEUE64;
157}
158
159static bool megasas_use_msix(MegasasState *s)
160{
161 return s->msix != ON_OFF_AUTO_OFF;
162}
163
164static bool megasas_is_jbod(MegasasState *s)
165{
166 return s->flags & MEGASAS_MASK_USE_JBOD;
167}
168
169static void megasas_frame_set_cmd_status(MegasasState *s,
170 unsigned long frame, uint8_t v)
171{
172 PCIDevice *pci = &s->parent_obj;
173 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), v);
174}
175
176static void megasas_frame_set_scsi_status(MegasasState *s,
177 unsigned long frame, uint8_t v)
178{
179 PCIDevice *pci = &s->parent_obj;
180 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status), v);
181}
182
183
184
185
186
187static uint64_t megasas_frame_get_context(MegasasState *s,
188 unsigned long frame)
189{
190 PCIDevice *pci = &s->parent_obj;
191 return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context));
192}
193
194static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
195{
196 return cmd->flags & MFI_FRAME_IEEE_SGL;
197}
198
199static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
200{
201 return cmd->flags & MFI_FRAME_SGL64;
202}
203
204static bool megasas_frame_is_sense64(MegasasCmd *cmd)
205{
206 return cmd->flags & MFI_FRAME_SENSE64;
207}
208
209static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
210 union mfi_sgl *sgl)
211{
212 uint64_t addr;
213
214 if (megasas_frame_is_ieee_sgl(cmd)) {
215 addr = le64_to_cpu(sgl->sg_skinny->addr);
216 } else if (megasas_frame_is_sgl64(cmd)) {
217 addr = le64_to_cpu(sgl->sg64->addr);
218 } else {
219 addr = le32_to_cpu(sgl->sg32->addr);
220 }
221 return addr;
222}
223
224static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
225 union mfi_sgl *sgl)
226{
227 uint32_t len;
228
229 if (megasas_frame_is_ieee_sgl(cmd)) {
230 len = le32_to_cpu(sgl->sg_skinny->len);
231 } else if (megasas_frame_is_sgl64(cmd)) {
232 len = le32_to_cpu(sgl->sg64->len);
233 } else {
234 len = le32_to_cpu(sgl->sg32->len);
235 }
236 return len;
237}
238
239static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
240 union mfi_sgl *sgl)
241{
242 uint8_t *next = (uint8_t *)sgl;
243
244 if (megasas_frame_is_ieee_sgl(cmd)) {
245 next += sizeof(struct mfi_sg_skinny);
246 } else if (megasas_frame_is_sgl64(cmd)) {
247 next += sizeof(struct mfi_sg64);
248 } else {
249 next += sizeof(struct mfi_sg32);
250 }
251
252 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
253 return NULL;
254 }
255 return (union mfi_sgl *)next;
256}
257
258static void megasas_soft_reset(MegasasState *s);
259
260static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
261{
262 int i;
263 int iov_count = 0;
264 size_t iov_size = 0;
265
266 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
267 iov_count = cmd->frame->header.sge_count;
268 if (iov_count > MEGASAS_MAX_SGE) {
269 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
270 MEGASAS_MAX_SGE);
271 return iov_count;
272 }
273 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
274 for (i = 0; i < iov_count; i++) {
275 dma_addr_t iov_pa, iov_size_p;
276
277 if (!sgl) {
278 trace_megasas_iovec_sgl_underflow(cmd->index, i);
279 goto unmap;
280 }
281 iov_pa = megasas_sgl_get_addr(cmd, sgl);
282 iov_size_p = megasas_sgl_get_len(cmd, sgl);
283 if (!iov_pa || !iov_size_p) {
284 trace_megasas_iovec_sgl_invalid(cmd->index, i,
285 iov_pa, iov_size_p);
286 goto unmap;
287 }
288 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
289 sgl = megasas_sgl_next(cmd, sgl);
290 iov_size += (size_t)iov_size_p;
291 }
292 if (cmd->iov_size > iov_size) {
293 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
294 } else if (cmd->iov_size < iov_size) {
295 trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size);
296 }
297 cmd->iov_offset = 0;
298 return 0;
299unmap:
300 qemu_sglist_destroy(&cmd->qsg);
301 return iov_count - i;
302}
303
304
305
306
307static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
308 uint8_t sense_len)
309{
310 PCIDevice *pcid = PCI_DEVICE(cmd->state);
311 uint32_t pa_hi = 0, pa_lo;
312 hwaddr pa;
313 int frame_sense_len;
314
315 frame_sense_len = cmd->frame->header.sense_len;
316 if (sense_len > frame_sense_len) {
317 sense_len = frame_sense_len;
318 }
319 if (sense_len) {
320 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
321 if (megasas_frame_is_sense64(cmd)) {
322 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
323 }
324 pa = ((uint64_t) pa_hi << 32) | pa_lo;
325 pci_dma_write(pcid, pa, sense_ptr, sense_len);
326 cmd->frame->header.sense_len = sense_len;
327 }
328 return sense_len;
329}
330
331static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
332{
333 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
334 uint8_t sense_len = 18;
335
336 memset(sense_buf, 0, sense_len);
337 sense_buf[0] = 0xf0;
338 sense_buf[2] = sense.key;
339 sense_buf[7] = 10;
340 sense_buf[12] = sense.asc;
341 sense_buf[13] = sense.ascq;
342 megasas_build_sense(cmd, sense_buf, sense_len);
343}
344
345static void megasas_copy_sense(MegasasCmd *cmd)
346{
347 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
348 uint8_t sense_len;
349
350 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
351 SCSI_SENSE_BUF_SIZE);
352 megasas_build_sense(cmd, sense_buf, sense_len);
353}
354
355
356
357
358static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
359{
360 memset(cdb, 0, 6);
361 cdb[0] = INQUIRY;
362 if (pg > 0) {
363 cdb[1] = 0x1;
364 cdb[2] = pg;
365 }
366 cdb[3] = (len >> 8) & 0xff;
367 cdb[4] = (len & 0xff);
368 return len;
369}
370
371
372
373
374static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
375 uint32_t len, bool is_write)
376{
377 memset(cdb, 0x0, 16);
378 if (is_write) {
379 cdb[0] = WRITE_16;
380 } else {
381 cdb[0] = READ_16;
382 }
383 cdb[2] = (lba >> 56) & 0xff;
384 cdb[3] = (lba >> 48) & 0xff;
385 cdb[4] = (lba >> 40) & 0xff;
386 cdb[5] = (lba >> 32) & 0xff;
387 cdb[6] = (lba >> 24) & 0xff;
388 cdb[7] = (lba >> 16) & 0xff;
389 cdb[8] = (lba >> 8) & 0xff;
390 cdb[9] = (lba) & 0xff;
391 cdb[10] = (len >> 24) & 0xff;
392 cdb[11] = (len >> 16) & 0xff;
393 cdb[12] = (len >> 8) & 0xff;
394 cdb[13] = (len) & 0xff;
395}
396
397
398
399
400static uint64_t megasas_fw_time(void)
401{
402 struct tm curtime;
403
404 qemu_get_timedate(&curtime, 0);
405 return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
406 ((uint64_t)curtime.tm_min & 0xff) << 40 |
407 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
408 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
409 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
410 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
411}
412
413
414
415
416
417
418
419static uint64_t megasas_get_sata_addr(uint16_t id)
420{
421 uint64_t addr = (0x1221ULL << 48);
422 return addr | ((uint64_t)id << 24);
423}
424
425
426
427
428static int megasas_next_index(MegasasState *s, int index, int limit)
429{
430 index++;
431 if (index == limit) {
432 index = 0;
433 }
434 return index;
435}
436
437static MegasasCmd *megasas_lookup_frame(MegasasState *s,
438 hwaddr frame)
439{
440 MegasasCmd *cmd = NULL;
441 int num = 0, index;
442
443 index = s->reply_queue_head;
444
445 while (num < s->fw_cmds) {
446 if (s->frames[index].pa && s->frames[index].pa == frame) {
447 cmd = &s->frames[index];
448 break;
449 }
450 index = megasas_next_index(s, index, s->fw_cmds);
451 num++;
452 }
453
454 return cmd;
455}
456
457static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
458{
459 PCIDevice *p = PCI_DEVICE(s);
460
461 if (cmd->pa_size) {
462 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
463 }
464 cmd->frame = NULL;
465 cmd->pa = 0;
466 cmd->pa_size = 0;
467 clear_bit(cmd->index, s->frame_map);
468}
469
470
471
472
473
474static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
475 hwaddr frame, uint64_t context, int count)
476{
477 PCIDevice *pcid = PCI_DEVICE(s);
478 MegasasCmd *cmd = NULL;
479 int frame_size = MFI_FRAME_SIZE * 16;
480 hwaddr frame_size_p = frame_size;
481 unsigned long index;
482
483 index = 0;
484 while (index < s->fw_cmds) {
485 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
486 if (!s->frames[index].pa)
487 break;
488
489 trace_megasas_qf_mapped(index);
490 }
491 if (index >= s->fw_cmds) {
492
493 trace_megasas_qf_busy(frame);
494 return NULL;
495 }
496 cmd = &s->frames[index];
497 set_bit(index, s->frame_map);
498 trace_megasas_qf_new(index, frame);
499
500 cmd->pa = frame;
501
502 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
503 if (frame_size_p != frame_size) {
504 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
505 if (cmd->frame) {
506 megasas_unmap_frame(s, cmd);
507 }
508 s->event_count++;
509 return NULL;
510 }
511 cmd->pa_size = frame_size_p;
512 cmd->context = context;
513 if (!megasas_use_queue64(s)) {
514 cmd->context &= (uint64_t)0xFFFFFFFF;
515 }
516 cmd->count = count;
517 cmd->dcmd_opcode = -1;
518 s->busy++;
519
520 if (s->consumer_pa) {
521 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
522 }
523 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
524 s->reply_queue_head, s->reply_queue_tail, s->busy);
525
526 return cmd;
527}
528
529static void megasas_complete_frame(MegasasState *s, uint64_t context)
530{
531 PCIDevice *pci_dev = PCI_DEVICE(s);
532 int tail, queue_offset;
533
534
535 s->busy--;
536 if (s->reply_queue_pa) {
537
538
539
540
541
542 if (megasas_use_queue64(s)) {
543 queue_offset = s->reply_queue_head * sizeof(uint64_t);
544 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
545 } else {
546 queue_offset = s->reply_queue_head * sizeof(uint32_t);
547 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
548 }
549 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
550 trace_megasas_qf_complete(context, s->reply_queue_head,
551 s->reply_queue_tail, s->busy);
552 }
553
554 if (megasas_intr_enabled(s)) {
555
556 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
557 tail = s->reply_queue_head;
558 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
559 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
560 s->busy);
561 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head);
562
563 if (msix_enabled(pci_dev)) {
564 trace_megasas_msix_raise(0);
565 msix_notify(pci_dev, 0);
566 } else if (msi_enabled(pci_dev)) {
567 trace_megasas_msi_raise(0);
568 msi_notify(pci_dev, 0);
569 } else {
570 s->doorbell++;
571 if (s->doorbell == 1) {
572 trace_megasas_irq_raise();
573 pci_irq_assert(pci_dev);
574 }
575 }
576 } else {
577 trace_megasas_qf_complete_noirq(context);
578 }
579}
580
581static void megasas_complete_command(MegasasCmd *cmd)
582{
583 qemu_sglist_destroy(&cmd->qsg);
584 cmd->iov_size = 0;
585 cmd->iov_offset = 0;
586
587 cmd->req->hba_private = NULL;
588 scsi_req_unref(cmd->req);
589 cmd->req = NULL;
590
591 megasas_unmap_frame(cmd->state, cmd);
592 megasas_complete_frame(cmd->state, cmd->context);
593}
594
595static void megasas_reset_frames(MegasasState *s)
596{
597 int i;
598 MegasasCmd *cmd;
599
600 for (i = 0; i < s->fw_cmds; i++) {
601 cmd = &s->frames[i];
602 if (cmd->pa) {
603 megasas_unmap_frame(s, cmd);
604 }
605 }
606 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
607}
608
609static void megasas_abort_command(MegasasCmd *cmd)
610{
611
612 if (cmd->req != NULL) {
613 scsi_req_cancel(cmd->req);
614 }
615}
616
617static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
618{
619 PCIDevice *pcid = PCI_DEVICE(s);
620 uint32_t pa_hi, pa_lo;
621 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
622 struct mfi_init_qinfo *initq = NULL;
623 uint32_t flags;
624 int ret = MFI_STAT_OK;
625
626 if (s->reply_queue_pa) {
627 trace_megasas_initq_mapped(s->reply_queue_pa);
628 goto out;
629 }
630 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
631 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
632 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
633 trace_megasas_init_firmware((uint64_t)iq_pa);
634 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
635 if (!initq || initq_size != sizeof(*initq)) {
636 trace_megasas_initq_map_failed(cmd->index);
637 s->event_count++;
638 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
639 goto out;
640 }
641 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
642 if (s->reply_queue_len > s->fw_cmds) {
643 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
644 s->event_count++;
645 ret = MFI_STAT_INVALID_PARAMETER;
646 goto out;
647 }
648 pa_lo = le32_to_cpu(initq->rq_addr_lo);
649 pa_hi = le32_to_cpu(initq->rq_addr_hi);
650 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
651 pa_lo = le32_to_cpu(initq->ci_addr_lo);
652 pa_hi = le32_to_cpu(initq->ci_addr_hi);
653 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
654 pa_lo = le32_to_cpu(initq->pi_addr_lo);
655 pa_hi = le32_to_cpu(initq->pi_addr_hi);
656 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
657 s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa);
658 s->reply_queue_head %= MEGASAS_MAX_FRAMES;
659 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
660 s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
661 flags = le32_to_cpu(initq->flags);
662 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
663 s->flags |= MEGASAS_MASK_USE_QUEUE64;
664 }
665 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
666 s->reply_queue_len, s->reply_queue_head,
667 s->reply_queue_tail, flags);
668 megasas_reset_frames(s);
669 s->fw_state = MFI_FWSTATE_OPERATIONAL;
670out:
671 if (initq) {
672 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
673 }
674 return ret;
675}
676
677static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
678{
679 dma_addr_t iov_pa, iov_size;
680 int iov_count;
681
682 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
683 iov_count = cmd->frame->header.sge_count;
684 if (!iov_count) {
685 trace_megasas_dcmd_zero_sge(cmd->index);
686 cmd->iov_size = 0;
687 return 0;
688 } else if (iov_count > 1) {
689 trace_megasas_dcmd_invalid_sge(cmd->index, iov_count);
690 cmd->iov_size = 0;
691 return -EINVAL;
692 }
693 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
694 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
695 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
696 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
697 cmd->iov_size = iov_size;
698 return 0;
699}
700
701static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
702{
703 trace_megasas_finish_dcmd(cmd->index, iov_size);
704
705 if (iov_size > cmd->iov_size) {
706 if (megasas_frame_is_ieee_sgl(cmd)) {
707 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
708 } else if (megasas_frame_is_sgl64(cmd)) {
709 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
710 } else {
711 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
712 }
713 }
714}
715
716static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
717{
718 PCIDevice *pci_dev = PCI_DEVICE(s);
719 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
720 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
721 struct mfi_ctrl_info info;
722 size_t dcmd_size = sizeof(info);
723 BusChild *kid;
724 int num_pd_disks = 0;
725
726 memset(&info, 0x0, dcmd_size);
727 if (cmd->iov_size < dcmd_size) {
728 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
729 dcmd_size);
730 return MFI_STAT_INVALID_PARAMETER;
731 }
732
733 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
734 info.pci.device = cpu_to_le16(pci_class->device_id);
735 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
736 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
737
738
739
740
741
742
743
744
745
746
747
748 info.host.type = MFI_INFO_HOST_PCIE;
749 info.device.type = MFI_INFO_DEV_SAS3G;
750 info.device.port_count = 8;
751 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
752 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
753 uint16_t pd_id;
754
755 if (num_pd_disks < 8) {
756 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
757 info.device.port_addr[num_pd_disks] =
758 cpu_to_le64(megasas_get_sata_addr(pd_id));
759 }
760 num_pd_disks++;
761 }
762
763 memcpy(info.product_name, base_class->product_name, 24);
764 snprintf(info.serial_number, 32, "%s", s->hba_serial);
765 snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
766 memcpy(info.image_component[0].name, "APP", 3);
767 snprintf(info.image_component[0].version, 10, "%s-QEMU",
768 base_class->product_version);
769 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
770 memcpy(info.image_component[0].build_time, "12:34:56", 8);
771 info.image_component_count = 1;
772 if (pci_dev->has_rom) {
773 uint8_t biosver[32];
774 uint8_t *ptr;
775
776 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
777 memcpy(biosver, ptr + 0x41, 31);
778 biosver[31] = 0;
779 memcpy(info.image_component[1].name, "BIOS", 4);
780 memcpy(info.image_component[1].version, biosver,
781 strlen((const char *)biosver));
782 info.image_component_count++;
783 }
784 info.current_fw_time = cpu_to_le32(megasas_fw_time());
785 info.max_arms = 32;
786 info.max_spans = 8;
787 info.max_arrays = MEGASAS_MAX_ARRAYS;
788 info.max_lds = MFI_MAX_LD;
789 info.max_cmds = cpu_to_le16(s->fw_cmds);
790 info.max_sg_elements = cpu_to_le16(s->fw_sge);
791 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
792 if (!megasas_is_jbod(s))
793 info.lds_present = cpu_to_le16(num_pd_disks);
794 info.pd_present = cpu_to_le16(num_pd_disks);
795 info.pd_disks_present = cpu_to_le16(num_pd_disks);
796 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
797 MFI_INFO_HW_MEM |
798 MFI_INFO_HW_FLASH);
799 info.memory_size = cpu_to_le16(512);
800 info.nvram_size = cpu_to_le16(32);
801 info.flash_size = cpu_to_le16(16);
802 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
803 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
804 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
805 MFI_INFO_AOPS_MIXED_ARRAY);
806 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
807 MFI_INFO_LDOPS_ACCESS_POLICY |
808 MFI_INFO_LDOPS_IO_POLICY |
809 MFI_INFO_LDOPS_WRITE_POLICY |
810 MFI_INFO_LDOPS_READ_POLICY);
811 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
812 info.stripe_sz_ops.min = 3;
813 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
814 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
815 info.properties.intr_throttle_cnt = cpu_to_le16(16);
816 info.properties.intr_throttle_timeout = cpu_to_le16(50);
817 info.properties.rebuild_rate = 30;
818 info.properties.patrol_read_rate = 30;
819 info.properties.bgi_rate = 30;
820 info.properties.cc_rate = 30;
821 info.properties.recon_rate = 30;
822 info.properties.cache_flush_interval = 4;
823 info.properties.spinup_drv_cnt = 2;
824 info.properties.spinup_delay = 6;
825 info.properties.ecc_bucket_size = 15;
826 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
827 info.properties.expose_encl_devices = 1;
828 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
829 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
830 MFI_INFO_PDOPS_FORCE_OFFLINE);
831 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
832 MFI_INFO_PDMIX_SATA |
833 MFI_INFO_PDMIX_LD);
834
835 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
836 return MFI_STAT_OK;
837}
838
839static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
840{
841 struct mfi_defaults info;
842 size_t dcmd_size = sizeof(struct mfi_defaults);
843
844 memset(&info, 0x0, dcmd_size);
845 if (cmd->iov_size < dcmd_size) {
846 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
847 dcmd_size);
848 return MFI_STAT_INVALID_PARAMETER;
849 }
850
851 info.sas_addr = cpu_to_le64(s->sas_addr);
852 info.stripe_size = 3;
853 info.flush_time = 4;
854 info.background_rate = 30;
855 info.allow_mix_in_enclosure = 1;
856 info.allow_mix_in_ld = 1;
857 info.direct_pd_mapping = 1;
858
859 info.bios_enumerate_lds = 1;
860 info.disable_ctrl_r = 1;
861 info.expose_enclosure_devices = 1;
862 info.disable_preboot_cli = 1;
863 info.cluster_disable = 1;
864
865 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
866 return MFI_STAT_OK;
867}
868
869static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
870{
871 struct mfi_bios_data info;
872 size_t dcmd_size = sizeof(info);
873
874 memset(&info, 0x0, dcmd_size);
875 if (cmd->iov_size < dcmd_size) {
876 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
877 dcmd_size);
878 return MFI_STAT_INVALID_PARAMETER;
879 }
880 info.continue_on_error = 1;
881 info.verbose = 1;
882 if (megasas_is_jbod(s)) {
883 info.expose_all_drives = 1;
884 }
885
886 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
887 return MFI_STAT_OK;
888}
889
890static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
891{
892 uint64_t fw_time;
893 size_t dcmd_size = sizeof(fw_time);
894
895 fw_time = cpu_to_le64(megasas_fw_time());
896
897 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
898 return MFI_STAT_OK;
899}
900
901static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
902{
903 uint64_t fw_time;
904
905
906 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
907
908 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
909 fw_time = cpu_to_le64(megasas_fw_time());
910 return MFI_STAT_OK;
911}
912
913static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
914{
915 struct mfi_evt_log_state info;
916 size_t dcmd_size = sizeof(info);
917
918 memset(&info, 0, dcmd_size);
919
920 info.newest_seq_num = cpu_to_le32(s->event_count);
921 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
922 info.boot_seq_num = cpu_to_le32(s->boot_event);
923
924 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
925 return MFI_STAT_OK;
926}
927
928static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
929{
930 union mfi_evt event;
931
932 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
933 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
934 sizeof(struct mfi_evt_detail));
935 return MFI_STAT_INVALID_PARAMETER;
936 }
937 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
938 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
939 s->event_locale = event.members.locale;
940 s->event_class = event.members.class;
941 s->event_cmd = cmd;
942
943 s->busy--;
944 cmd->iov_size = sizeof(struct mfi_evt_detail);
945 return MFI_STAT_INVALID_STATUS;
946}
947
948static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
949{
950 struct mfi_pd_list info;
951 size_t dcmd_size = sizeof(info);
952 BusChild *kid;
953 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
954
955 memset(&info, 0, dcmd_size);
956 offset = 8;
957 dcmd_limit = offset + sizeof(struct mfi_pd_address);
958 if (cmd->iov_size < dcmd_limit) {
959 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
960 dcmd_limit);
961 return MFI_STAT_INVALID_PARAMETER;
962 }
963
964 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
965 if (max_pd_disks > MFI_MAX_SYS_PDS) {
966 max_pd_disks = MFI_MAX_SYS_PDS;
967 }
968 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
969 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
970 uint16_t pd_id;
971
972 if (num_pd_disks >= max_pd_disks)
973 break;
974
975 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
976 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
977 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
978 info.addr[num_pd_disks].encl_index = 0;
979 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
980 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
981 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
982 info.addr[num_pd_disks].sas_addr[0] =
983 cpu_to_le64(megasas_get_sata_addr(pd_id));
984 num_pd_disks++;
985 offset += sizeof(struct mfi_pd_address);
986 }
987 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
988 max_pd_disks, offset);
989
990 info.size = cpu_to_le32(offset);
991 info.count = cpu_to_le32(num_pd_disks);
992
993 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
994 return MFI_STAT_OK;
995}
996
997static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
998{
999 uint16_t flags;
1000
1001
1002 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1003 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1004 if (flags == MR_PD_QUERY_TYPE_ALL ||
1005 megasas_is_jbod(s)) {
1006 return megasas_dcmd_pd_get_list(s, cmd);
1007 }
1008
1009 return MFI_STAT_OK;
1010}
1011
1012static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1013 MegasasCmd *cmd)
1014{
1015 struct mfi_pd_info *info = cmd->iov_buf;
1016 size_t dcmd_size = sizeof(struct mfi_pd_info);
1017 uint64_t pd_size;
1018 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1019 uint8_t cmdbuf[6];
1020 SCSIRequest *req;
1021 size_t len, resid;
1022
1023 if (!cmd->iov_buf) {
1024 cmd->iov_buf = g_malloc0(dcmd_size);
1025 info = cmd->iov_buf;
1026 info->inquiry_data[0] = 0x7f;
1027 info->vpd_page83[0] = 0x7f;
1028 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1029 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1030 if (!req) {
1031 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1032 "PD get info std inquiry");
1033 g_free(cmd->iov_buf);
1034 cmd->iov_buf = NULL;
1035 return MFI_STAT_FLASH_ALLOC_FAIL;
1036 }
1037 trace_megasas_dcmd_internal_submit(cmd->index,
1038 "PD get info std inquiry", lun);
1039 len = scsi_req_enqueue(req);
1040 if (len > 0) {
1041 cmd->iov_size = len;
1042 scsi_req_continue(req);
1043 }
1044 return MFI_STAT_INVALID_STATUS;
1045 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1046 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1047 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1048 if (!req) {
1049 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1050 "PD get info vpd inquiry");
1051 return MFI_STAT_FLASH_ALLOC_FAIL;
1052 }
1053 trace_megasas_dcmd_internal_submit(cmd->index,
1054 "PD get info vpd inquiry", lun);
1055 len = scsi_req_enqueue(req);
1056 if (len > 0) {
1057 cmd->iov_size = len;
1058 scsi_req_continue(req);
1059 }
1060 return MFI_STAT_INVALID_STATUS;
1061 }
1062
1063 if ((info->inquiry_data[0] >> 5) == 0) {
1064 if (megasas_is_jbod(cmd->state)) {
1065 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1066 } else {
1067 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1068 }
1069 } else {
1070 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1071 }
1072
1073 info->ref.v.device_id = cpu_to_le16(pd_id);
1074 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1075 MFI_PD_DDF_TYPE_INTF_SAS);
1076 blk_get_geometry(sdev->conf.blk, &pd_size);
1077 info->raw_size = cpu_to_le64(pd_size);
1078 info->non_coerced_size = cpu_to_le64(pd_size);
1079 info->coerced_size = cpu_to_le64(pd_size);
1080 info->encl_device_id = 0xFFFF;
1081 info->slot_number = (sdev->id & 0xFF);
1082 info->path_info.count = 1;
1083 info->path_info.sas_addr[0] =
1084 cpu_to_le64(megasas_get_sata_addr(pd_id));
1085 info->connected_port_bitmap = 0x1;
1086 info->device_speed = 1;
1087 info->link_speed = 1;
1088 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1089 g_free(cmd->iov_buf);
1090 cmd->iov_size = dcmd_size - resid;
1091 cmd->iov_buf = NULL;
1092 return MFI_STAT_OK;
1093}
1094
1095static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1096{
1097 size_t dcmd_size = sizeof(struct mfi_pd_info);
1098 uint16_t pd_id;
1099 uint8_t target_id, lun_id;
1100 SCSIDevice *sdev = NULL;
1101 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1102
1103 if (cmd->iov_size < dcmd_size) {
1104 return MFI_STAT_INVALID_PARAMETER;
1105 }
1106
1107
1108 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1109 target_id = (pd_id >> 8) & 0xFF;
1110 lun_id = pd_id & 0xFF;
1111 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1112 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1113
1114 if (sdev) {
1115
1116 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1117 }
1118
1119 return retval;
1120}
1121
1122static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1123{
1124 struct mfi_ld_list info;
1125 size_t dcmd_size = sizeof(info), resid;
1126 uint32_t num_ld_disks = 0, max_ld_disks;
1127 uint64_t ld_size;
1128 BusChild *kid;
1129
1130 memset(&info, 0, dcmd_size);
1131 if (cmd->iov_size > dcmd_size) {
1132 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1133 dcmd_size);
1134 return MFI_STAT_INVALID_PARAMETER;
1135 }
1136
1137 max_ld_disks = (cmd->iov_size - 8) / 16;
1138 if (megasas_is_jbod(s)) {
1139 max_ld_disks = 0;
1140 }
1141 if (max_ld_disks > MFI_MAX_LD) {
1142 max_ld_disks = MFI_MAX_LD;
1143 }
1144 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1145 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1146
1147 if (num_ld_disks >= max_ld_disks) {
1148 break;
1149 }
1150
1151 blk_get_geometry(sdev->conf.blk, &ld_size);
1152 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1153 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1154 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1155 num_ld_disks++;
1156 }
1157 info.ld_count = cpu_to_le32(num_ld_disks);
1158 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1159
1160 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1161 cmd->iov_size = dcmd_size - resid;
1162 return MFI_STAT_OK;
1163}
1164
1165static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1166{
1167 uint16_t flags;
1168 struct mfi_ld_targetid_list info;
1169 size_t dcmd_size = sizeof(info), resid;
1170 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1171 BusChild *kid;
1172
1173
1174 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1175 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1176 if (flags != MR_LD_QUERY_TYPE_ALL &&
1177 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1178 max_ld_disks = 0;
1179 }
1180
1181 memset(&info, 0, dcmd_size);
1182 if (cmd->iov_size < 12) {
1183 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1184 dcmd_size);
1185 return MFI_STAT_INVALID_PARAMETER;
1186 }
1187 dcmd_size = sizeof(uint32_t) * 2 + 3;
1188 max_ld_disks = cmd->iov_size - dcmd_size;
1189 if (megasas_is_jbod(s)) {
1190 max_ld_disks = 0;
1191 }
1192 if (max_ld_disks > MFI_MAX_LD) {
1193 max_ld_disks = MFI_MAX_LD;
1194 }
1195 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1196 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1197
1198 if (num_ld_disks >= max_ld_disks) {
1199 break;
1200 }
1201 info.targetid[num_ld_disks] = sdev->lun;
1202 num_ld_disks++;
1203 dcmd_size++;
1204 }
1205 info.ld_count = cpu_to_le32(num_ld_disks);
1206 info.size = dcmd_size;
1207 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1208
1209 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1210 cmd->iov_size = dcmd_size - resid;
1211 return MFI_STAT_OK;
1212}
1213
1214static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1215 MegasasCmd *cmd)
1216{
1217 struct mfi_ld_info *info = cmd->iov_buf;
1218 size_t dcmd_size = sizeof(struct mfi_ld_info);
1219 uint8_t cdb[6];
1220 SCSIRequest *req;
1221 ssize_t len, resid;
1222 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1223 uint64_t ld_size;
1224
1225 if (!cmd->iov_buf) {
1226 cmd->iov_buf = g_malloc0(dcmd_size);
1227 info = cmd->iov_buf;
1228 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1229 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1230 if (!req) {
1231 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1232 "LD get info vpd inquiry");
1233 g_free(cmd->iov_buf);
1234 cmd->iov_buf = NULL;
1235 return MFI_STAT_FLASH_ALLOC_FAIL;
1236 }
1237 trace_megasas_dcmd_internal_submit(cmd->index,
1238 "LD get info vpd inquiry", lun);
1239 len = scsi_req_enqueue(req);
1240 if (len > 0) {
1241 cmd->iov_size = len;
1242 scsi_req_continue(req);
1243 }
1244 return MFI_STAT_INVALID_STATUS;
1245 }
1246
1247 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1248 info->ld_config.properties.ld.v.target_id = lun;
1249 info->ld_config.params.stripe_size = 3;
1250 info->ld_config.params.num_drives = 1;
1251 info->ld_config.params.is_consistent = 1;
1252
1253 blk_get_geometry(sdev->conf.blk, &ld_size);
1254 info->size = cpu_to_le64(ld_size);
1255 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1256 info->ld_config.span[0].start_block = 0;
1257 info->ld_config.span[0].num_blocks = info->size;
1258 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1259
1260 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1261 g_free(cmd->iov_buf);
1262 cmd->iov_size = dcmd_size - resid;
1263 cmd->iov_buf = NULL;
1264 return MFI_STAT_OK;
1265}
1266
1267static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1268{
1269 struct mfi_ld_info info;
1270 size_t dcmd_size = sizeof(info);
1271 uint16_t ld_id;
1272 uint32_t max_ld_disks = s->fw_luns;
1273 SCSIDevice *sdev = NULL;
1274 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1275
1276 if (cmd->iov_size < dcmd_size) {
1277 return MFI_STAT_INVALID_PARAMETER;
1278 }
1279
1280
1281 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1282 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1283
1284 if (megasas_is_jbod(s)) {
1285 return MFI_STAT_DEVICE_NOT_FOUND;
1286 }
1287
1288 if (ld_id < max_ld_disks) {
1289 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1290 }
1291
1292 if (sdev) {
1293 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1294 }
1295
1296 return retval;
1297}
1298
1299static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1300{
1301 uint8_t data[4096] = { 0 };
1302 struct mfi_config_data *info;
1303 int num_pd_disks = 0, array_offset, ld_offset;
1304 BusChild *kid;
1305
1306 if (cmd->iov_size > 4096) {
1307 return MFI_STAT_INVALID_PARAMETER;
1308 }
1309
1310 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1311 num_pd_disks++;
1312 }
1313 info = (struct mfi_config_data *)&data;
1314
1315
1316
1317
1318
1319
1320 info->array_count = num_pd_disks;
1321 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1322 info->log_drv_count = num_pd_disks;
1323 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1324 info->spares_count = 0;
1325 info->spares_size = sizeof(struct mfi_spare);
1326 info->size = sizeof(struct mfi_config_data) + info->array_size +
1327 info->log_drv_size;
1328 if (info->size > 4096) {
1329 return MFI_STAT_INVALID_PARAMETER;
1330 }
1331
1332 array_offset = sizeof(struct mfi_config_data);
1333 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1334
1335 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1336 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1337 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1338 struct mfi_array *array;
1339 struct mfi_ld_config *ld;
1340 uint64_t pd_size;
1341 int i;
1342
1343 array = (struct mfi_array *)(data + array_offset);
1344 blk_get_geometry(sdev->conf.blk, &pd_size);
1345 array->size = cpu_to_le64(pd_size);
1346 array->num_drives = 1;
1347 array->array_ref = cpu_to_le16(sdev_id);
1348 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1349 array->pd[0].ref.v.seq_num = 0;
1350 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1351 array->pd[0].encl.pd = 0xFF;
1352 array->pd[0].encl.slot = (sdev->id & 0xFF);
1353 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1354 array->pd[i].ref.v.device_id = 0xFFFF;
1355 array->pd[i].ref.v.seq_num = 0;
1356 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1357 array->pd[i].encl.pd = 0xFF;
1358 array->pd[i].encl.slot = 0xFF;
1359 }
1360 array_offset += sizeof(struct mfi_array);
1361 ld = (struct mfi_ld_config *)(data + ld_offset);
1362 memset(ld, 0, sizeof(struct mfi_ld_config));
1363 ld->properties.ld.v.target_id = sdev->id;
1364 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1365 MR_LD_CACHE_READ_ADAPTIVE;
1366 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1367 MR_LD_CACHE_READ_ADAPTIVE;
1368 ld->params.state = MFI_LD_STATE_OPTIMAL;
1369 ld->params.stripe_size = 3;
1370 ld->params.num_drives = 1;
1371 ld->params.span_depth = 1;
1372 ld->params.is_consistent = 1;
1373 ld->span[0].start_block = 0;
1374 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1375 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1376 ld_offset += sizeof(struct mfi_ld_config);
1377 }
1378
1379 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1380 return MFI_STAT_OK;
1381}
1382
1383static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1384{
1385 struct mfi_ctrl_props info;
1386 size_t dcmd_size = sizeof(info);
1387
1388 memset(&info, 0x0, dcmd_size);
1389 if (cmd->iov_size < dcmd_size) {
1390 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1391 dcmd_size);
1392 return MFI_STAT_INVALID_PARAMETER;
1393 }
1394 info.pred_fail_poll_interval = cpu_to_le16(300);
1395 info.intr_throttle_cnt = cpu_to_le16(16);
1396 info.intr_throttle_timeout = cpu_to_le16(50);
1397 info.rebuild_rate = 30;
1398 info.patrol_read_rate = 30;
1399 info.bgi_rate = 30;
1400 info.cc_rate = 30;
1401 info.recon_rate = 30;
1402 info.cache_flush_interval = 4;
1403 info.spinup_drv_cnt = 2;
1404 info.spinup_delay = 6;
1405 info.ecc_bucket_size = 15;
1406 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1407 info.expose_encl_devices = 1;
1408
1409 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1410 return MFI_STAT_OK;
1411}
1412
1413static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1414{
1415 blk_drain_all();
1416 return MFI_STAT_OK;
1417}
1418
1419static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1420{
1421 s->fw_state = MFI_FWSTATE_READY;
1422 return MFI_STAT_OK;
1423}
1424
1425
1426static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1427{
1428 uint16_t target_id;
1429 int i;
1430
1431
1432 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1433 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1434 for (i = 0; i < s->fw_cmds; i++) {
1435 MegasasCmd *tmp_cmd = &s->frames[i];
1436 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1437 SCSIDevice *d = tmp_cmd->req->dev;
1438 qdev_reset_all(&d->qdev);
1439 }
1440 }
1441 return MFI_STAT_OK;
1442}
1443
1444static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1445{
1446 struct mfi_ctrl_props info;
1447 size_t dcmd_size = sizeof(info);
1448
1449 if (cmd->iov_size < dcmd_size) {
1450 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1451 dcmd_size);
1452 return MFI_STAT_INVALID_PARAMETER;
1453 }
1454 dma_buf_write((uint8_t *)&info, dcmd_size, &cmd->qsg);
1455 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
1456 return MFI_STAT_OK;
1457}
1458
1459static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1460{
1461 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1462 return MFI_STAT_OK;
1463}
1464
1465static const struct dcmd_cmd_tbl_t {
1466 int opcode;
1467 const char *desc;
1468 int (*func)(MegasasState *s, MegasasCmd *cmd);
1469} dcmd_cmd_tbl[] = {
1470 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1471 megasas_dcmd_dummy },
1472 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1473 megasas_ctrl_get_info },
1474 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1475 megasas_dcmd_get_properties },
1476 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1477 megasas_dcmd_set_properties },
1478 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1479 megasas_dcmd_dummy },
1480 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1481 megasas_dcmd_dummy },
1482 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1483 megasas_dcmd_dummy },
1484 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1485 megasas_dcmd_dummy },
1486 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1487 megasas_dcmd_dummy },
1488 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1489 megasas_event_info },
1490 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1491 megasas_dcmd_dummy },
1492 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1493 megasas_event_wait },
1494 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1495 megasas_ctrl_shutdown },
1496 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1497 megasas_dcmd_dummy },
1498 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1499 megasas_dcmd_get_fw_time },
1500 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1501 megasas_dcmd_set_fw_time },
1502 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1503 megasas_dcmd_get_bios_info },
1504 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1505 megasas_dcmd_dummy },
1506 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1507 megasas_mfc_get_defaults },
1508 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1509 megasas_dcmd_dummy },
1510 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1511 megasas_cache_flush },
1512 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1513 megasas_dcmd_pd_get_list },
1514 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1515 megasas_dcmd_pd_list_query },
1516 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1517 megasas_dcmd_pd_get_info },
1518 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1519 megasas_dcmd_dummy },
1520 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1521 megasas_dcmd_dummy },
1522 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1523 megasas_dcmd_dummy },
1524 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1525 megasas_dcmd_dummy },
1526 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1527 megasas_dcmd_ld_get_list},
1528 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1529 megasas_dcmd_ld_list_query },
1530 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1531 megasas_dcmd_ld_get_info },
1532 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1533 megasas_dcmd_dummy },
1534 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1535 megasas_dcmd_dummy },
1536 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1537 megasas_dcmd_dummy },
1538 { MFI_DCMD_CFG_READ, "CFG_READ",
1539 megasas_dcmd_cfg_read },
1540 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1541 megasas_dcmd_dummy },
1542 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1543 megasas_dcmd_dummy },
1544 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1545 megasas_dcmd_dummy },
1546 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1547 megasas_dcmd_dummy },
1548 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1549 megasas_dcmd_dummy },
1550 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1551 megasas_dcmd_dummy },
1552 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1553 megasas_dcmd_dummy },
1554 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1555 megasas_dcmd_dummy },
1556 { MFI_DCMD_CLUSTER, "CLUSTER",
1557 megasas_dcmd_dummy },
1558 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1559 megasas_dcmd_dummy },
1560 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1561 megasas_cluster_reset_ld },
1562 { -1, NULL, NULL }
1563};
1564
1565static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1566{
1567 int retval = 0;
1568 size_t len;
1569 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1570
1571 cmd->dcmd_opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1572 trace_megasas_handle_dcmd(cmd->index, cmd->dcmd_opcode);
1573 if (megasas_map_dcmd(s, cmd) < 0) {
1574 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1575 }
1576 while (cmdptr->opcode != -1 && cmdptr->opcode != cmd->dcmd_opcode) {
1577 cmdptr++;
1578 }
1579 len = cmd->iov_size;
1580 if (cmdptr->opcode == -1) {
1581 trace_megasas_dcmd_unhandled(cmd->index, cmd->dcmd_opcode, len);
1582 retval = megasas_dcmd_dummy(s, cmd);
1583 } else {
1584 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1585 retval = cmdptr->func(s, cmd);
1586 }
1587 if (retval != MFI_STAT_INVALID_STATUS) {
1588 megasas_finish_dcmd(cmd, len);
1589 }
1590 return retval;
1591}
1592
1593static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1594 SCSIRequest *req, size_t resid)
1595{
1596 int retval = MFI_STAT_OK;
1597 int lun = req->lun;
1598
1599 trace_megasas_dcmd_internal_finish(cmd->index, cmd->dcmd_opcode, lun);
1600 cmd->iov_size -= resid;
1601 switch (cmd->dcmd_opcode) {
1602 case MFI_DCMD_PD_GET_INFO:
1603 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1604 break;
1605 case MFI_DCMD_LD_GET_INFO:
1606 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1607 break;
1608 default:
1609 trace_megasas_dcmd_internal_invalid(cmd->index, cmd->dcmd_opcode);
1610 retval = MFI_STAT_INVALID_DCMD;
1611 break;
1612 }
1613 if (retval != MFI_STAT_INVALID_STATUS) {
1614 megasas_finish_dcmd(cmd, cmd->iov_size);
1615 }
1616 return retval;
1617}
1618
1619static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1620{
1621 int len;
1622
1623 len = scsi_req_enqueue(cmd->req);
1624 if (len < 0) {
1625 len = -len;
1626 }
1627 if (len > 0) {
1628 if (len > cmd->iov_size) {
1629 if (is_write) {
1630 trace_megasas_iov_write_overflow(cmd->index, len,
1631 cmd->iov_size);
1632 } else {
1633 trace_megasas_iov_read_overflow(cmd->index, len,
1634 cmd->iov_size);
1635 }
1636 }
1637 if (len < cmd->iov_size) {
1638 if (is_write) {
1639 trace_megasas_iov_write_underflow(cmd->index, len,
1640 cmd->iov_size);
1641 } else {
1642 trace_megasas_iov_read_underflow(cmd->index, len,
1643 cmd->iov_size);
1644 }
1645 cmd->iov_size = len;
1646 }
1647 scsi_req_continue(cmd->req);
1648 }
1649 return len;
1650}
1651
1652static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1653 int frame_cmd)
1654{
1655 uint8_t *cdb;
1656 int target_id, lun_id, cdb_len;
1657 bool is_write;
1658 struct SCSIDevice *sdev = NULL;
1659 bool is_logical = (frame_cmd == MFI_CMD_LD_SCSI_IO);
1660
1661 cdb = cmd->frame->pass.cdb;
1662 target_id = cmd->frame->header.target_id;
1663 lun_id = cmd->frame->header.lun_id;
1664 cdb_len = cmd->frame->header.cdb_len;
1665
1666 if (is_logical) {
1667 if (target_id >= MFI_MAX_LD || lun_id != 0) {
1668 trace_megasas_scsi_target_not_present(
1669 mfi_frame_desc[frame_cmd], is_logical, target_id, lun_id);
1670 return MFI_STAT_DEVICE_NOT_FOUND;
1671 }
1672 }
1673 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1674
1675 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1676 trace_megasas_handle_scsi(mfi_frame_desc[frame_cmd], is_logical,
1677 target_id, lun_id, sdev, cmd->iov_size);
1678
1679 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1680 trace_megasas_scsi_target_not_present(
1681 mfi_frame_desc[frame_cmd], is_logical, target_id, lun_id);
1682 return MFI_STAT_DEVICE_NOT_FOUND;
1683 }
1684
1685 if (cdb_len > 16) {
1686 trace_megasas_scsi_invalid_cdb_len(
1687 mfi_frame_desc[frame_cmd], is_logical,
1688 target_id, lun_id, cdb_len);
1689 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1690 cmd->frame->header.scsi_status = CHECK_CONDITION;
1691 s->event_count++;
1692 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1693 }
1694
1695 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1696 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1697 cmd->frame->header.scsi_status = CHECK_CONDITION;
1698 s->event_count++;
1699 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1700 }
1701
1702 cmd->req = scsi_req_new(sdev, cmd->index, lun_id, cdb, cmd);
1703 if (!cmd->req) {
1704 trace_megasas_scsi_req_alloc_failed(
1705 mfi_frame_desc[frame_cmd], target_id, lun_id);
1706 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1707 cmd->frame->header.scsi_status = BUSY;
1708 s->event_count++;
1709 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1710 }
1711
1712 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1713 if (cmd->iov_size) {
1714 if (is_write) {
1715 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
1716 } else {
1717 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
1718 }
1719 } else {
1720 trace_megasas_scsi_nodata(cmd->index);
1721 }
1722 megasas_enqueue_req(cmd, is_write);
1723 return MFI_STAT_INVALID_STATUS;
1724}
1725
1726static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd, int frame_cmd)
1727{
1728 uint32_t lba_count, lba_start_hi, lba_start_lo;
1729 uint64_t lba_start;
1730 bool is_write = (frame_cmd == MFI_CMD_LD_WRITE);
1731 uint8_t cdb[16];
1732 int len;
1733 struct SCSIDevice *sdev = NULL;
1734 int target_id, lun_id, cdb_len;
1735
1736 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1737 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1738 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1739 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1740
1741 target_id = cmd->frame->header.target_id;
1742 lun_id = cmd->frame->header.lun_id;
1743 cdb_len = cmd->frame->header.cdb_len;
1744
1745 if (target_id < MFI_MAX_LD && lun_id == 0) {
1746 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1747 }
1748
1749 trace_megasas_handle_io(cmd->index,
1750 mfi_frame_desc[frame_cmd], target_id, lun_id,
1751 (unsigned long)lba_start, (unsigned long)lba_count);
1752 if (!sdev) {
1753 trace_megasas_io_target_not_present(cmd->index,
1754 mfi_frame_desc[frame_cmd], target_id, lun_id);
1755 return MFI_STAT_DEVICE_NOT_FOUND;
1756 }
1757
1758 if (cdb_len > 16) {
1759 trace_megasas_scsi_invalid_cdb_len(
1760 mfi_frame_desc[frame_cmd], 1, target_id, lun_id, cdb_len);
1761 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1762 cmd->frame->header.scsi_status = CHECK_CONDITION;
1763 s->event_count++;
1764 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1765 }
1766
1767 cmd->iov_size = lba_count * sdev->blocksize;
1768 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1769 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1770 cmd->frame->header.scsi_status = CHECK_CONDITION;
1771 s->event_count++;
1772 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1773 }
1774
1775 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1776 cmd->req = scsi_req_new(sdev, cmd->index,
1777 lun_id, cdb, cmd);
1778 if (!cmd->req) {
1779 trace_megasas_scsi_req_alloc_failed(
1780 mfi_frame_desc[frame_cmd], target_id, lun_id);
1781 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1782 cmd->frame->header.scsi_status = BUSY;
1783 s->event_count++;
1784 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1785 }
1786 len = megasas_enqueue_req(cmd, is_write);
1787 if (len > 0) {
1788 if (is_write) {
1789 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1790 } else {
1791 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1792 }
1793 }
1794 return MFI_STAT_INVALID_STATUS;
1795}
1796
1797static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1798{
1799 MegasasCmd *cmd = req->hba_private;
1800
1801 if (cmd->dcmd_opcode != -1) {
1802 return NULL;
1803 } else {
1804 return &cmd->qsg;
1805 }
1806}
1807
1808static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1809{
1810 MegasasCmd *cmd = req->hba_private;
1811 uint8_t *buf;
1812
1813 trace_megasas_io_complete(cmd->index, len);
1814
1815 if (cmd->dcmd_opcode != -1) {
1816 scsi_req_continue(req);
1817 return;
1818 }
1819
1820 buf = scsi_req_get_buf(req);
1821 if (cmd->dcmd_opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1822 struct mfi_pd_info *info = cmd->iov_buf;
1823
1824 if (info->inquiry_data[0] == 0x7f) {
1825 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1826 memcpy(info->inquiry_data, buf, len);
1827 } else if (info->vpd_page83[0] == 0x7f) {
1828 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1829 memcpy(info->vpd_page83, buf, len);
1830 }
1831 scsi_req_continue(req);
1832 } else if (cmd->dcmd_opcode == MFI_DCMD_LD_GET_INFO) {
1833 struct mfi_ld_info *info = cmd->iov_buf;
1834
1835 if (cmd->iov_buf) {
1836 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1837 scsi_req_continue(req);
1838 }
1839 }
1840}
1841
1842static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1843 size_t resid)
1844{
1845 MegasasCmd *cmd = req->hba_private;
1846 uint8_t cmd_status = MFI_STAT_OK;
1847
1848 trace_megasas_command_complete(cmd->index, status, resid);
1849
1850 if (req->io_canceled) {
1851 return;
1852 }
1853
1854 if (cmd->req == NULL) {
1855
1856
1857
1858 cmd_status = megasas_finish_internal_dcmd(cmd, req, resid);
1859 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1860 return;
1861 }
1862 } else {
1863 req->status = status;
1864 trace_megasas_scsi_complete(cmd->index, req->status,
1865 cmd->iov_size, req->cmd.xfer);
1866 if (req->status != GOOD) {
1867 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1868 }
1869 if (req->status == CHECK_CONDITION) {
1870 megasas_copy_sense(cmd);
1871 }
1872
1873 cmd->frame->header.scsi_status = req->status;
1874 }
1875 cmd->frame->header.cmd_status = cmd_status;
1876 megasas_complete_command(cmd);
1877}
1878
1879static void megasas_command_cancelled(SCSIRequest *req)
1880{
1881 MegasasCmd *cmd = req->hba_private;
1882
1883 if (!cmd) {
1884 return;
1885 }
1886 cmd->frame->header.cmd_status = MFI_STAT_SCSI_IO_FAILED;
1887 megasas_complete_command(cmd);
1888}
1889
1890static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1891{
1892 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
1893 hwaddr abort_addr, addr_hi, addr_lo;
1894 MegasasCmd *abort_cmd;
1895
1896 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1897 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1898 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1899
1900 abort_cmd = megasas_lookup_frame(s, abort_addr);
1901 if (!abort_cmd) {
1902 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1903 s->event_count++;
1904 return MFI_STAT_OK;
1905 }
1906 if (!megasas_use_queue64(s)) {
1907 abort_ctx &= (uint64_t)0xFFFFFFFF;
1908 }
1909 if (abort_cmd->context != abort_ctx) {
1910 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->context,
1911 abort_cmd->index);
1912 s->event_count++;
1913 return MFI_STAT_ABORT_NOT_POSSIBLE;
1914 }
1915 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1916 megasas_abort_command(abort_cmd);
1917 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1918 s->event_cmd = NULL;
1919 }
1920 s->event_count++;
1921 return MFI_STAT_OK;
1922}
1923
1924static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1925 uint32_t frame_count)
1926{
1927 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1928 uint64_t frame_context;
1929 int frame_cmd;
1930 MegasasCmd *cmd;
1931
1932
1933
1934
1935
1936 frame_context = megasas_frame_get_context(s, frame_addr);
1937
1938 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1939 if (!cmd) {
1940
1941 trace_megasas_frame_busy(frame_addr);
1942 megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1943 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1944 megasas_complete_frame(s, frame_context);
1945 s->event_count++;
1946 return;
1947 }
1948 frame_cmd = cmd->frame->header.frame_cmd;
1949 switch (frame_cmd) {
1950 case MFI_CMD_INIT:
1951 frame_status = megasas_init_firmware(s, cmd);
1952 break;
1953 case MFI_CMD_DCMD:
1954 frame_status = megasas_handle_dcmd(s, cmd);
1955 break;
1956 case MFI_CMD_ABORT:
1957 frame_status = megasas_handle_abort(s, cmd);
1958 break;
1959 case MFI_CMD_PD_SCSI_IO:
1960 case MFI_CMD_LD_SCSI_IO:
1961 frame_status = megasas_handle_scsi(s, cmd, frame_cmd);
1962 break;
1963 case MFI_CMD_LD_READ:
1964 case MFI_CMD_LD_WRITE:
1965 frame_status = megasas_handle_io(s, cmd, frame_cmd);
1966 break;
1967 default:
1968 trace_megasas_unhandled_frame_cmd(cmd->index, frame_cmd);
1969 s->event_count++;
1970 break;
1971 }
1972 if (frame_status != MFI_STAT_INVALID_STATUS) {
1973 if (cmd->frame) {
1974 cmd->frame->header.cmd_status = frame_status;
1975 } else {
1976 megasas_frame_set_cmd_status(s, frame_addr, frame_status);
1977 }
1978 megasas_unmap_frame(s, cmd);
1979 megasas_complete_frame(s, cmd->context);
1980 }
1981}
1982
1983static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
1984 unsigned size)
1985{
1986 MegasasState *s = opaque;
1987 PCIDevice *pci_dev = PCI_DEVICE(s);
1988 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
1989 uint32_t retval = 0;
1990
1991 switch (addr) {
1992 case MFI_IDB:
1993 retval = 0;
1994 trace_megasas_mmio_readl("MFI_IDB", retval);
1995 break;
1996 case MFI_OMSG0:
1997 case MFI_OSP0:
1998 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
1999 (s->fw_state & MFI_FWSTATE_MASK) |
2000 ((s->fw_sge & 0xff) << 16) |
2001 (s->fw_cmds & 0xFFFF);
2002 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2003 retval);
2004 break;
2005 case MFI_OSTS:
2006 if (megasas_intr_enabled(s) && s->doorbell) {
2007 retval = base_class->osts;
2008 }
2009 trace_megasas_mmio_readl("MFI_OSTS", retval);
2010 break;
2011 case MFI_OMSK:
2012 retval = s->intr_mask;
2013 trace_megasas_mmio_readl("MFI_OMSK", retval);
2014 break;
2015 case MFI_ODCR0:
2016 retval = s->doorbell ? 1 : 0;
2017 trace_megasas_mmio_readl("MFI_ODCR0", retval);
2018 break;
2019 case MFI_DIAG:
2020 retval = s->diag;
2021 trace_megasas_mmio_readl("MFI_DIAG", retval);
2022 break;
2023 case MFI_OSP1:
2024 retval = 15;
2025 trace_megasas_mmio_readl("MFI_OSP1", retval);
2026 break;
2027 default:
2028 trace_megasas_mmio_invalid_readl(addr);
2029 break;
2030 }
2031 return retval;
2032}
2033
2034static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2035
2036static void megasas_mmio_write(void *opaque, hwaddr addr,
2037 uint64_t val, unsigned size)
2038{
2039 MegasasState *s = opaque;
2040 PCIDevice *pci_dev = PCI_DEVICE(s);
2041 uint64_t frame_addr;
2042 uint32_t frame_count;
2043 int i;
2044
2045 switch (addr) {
2046 case MFI_IDB:
2047 trace_megasas_mmio_writel("MFI_IDB", val);
2048 if (val & MFI_FWINIT_ABORT) {
2049
2050 for (i = 0; i < s->fw_cmds; i++) {
2051 megasas_abort_command(&s->frames[i]);
2052 }
2053 }
2054 if (val & MFI_FWINIT_READY) {
2055
2056 megasas_soft_reset(s);
2057 }
2058 if (val & MFI_FWINIT_MFIMODE) {
2059
2060 }
2061 if (val & MFI_FWINIT_STOP_ADP) {
2062
2063 s->fw_state = MFI_FWSTATE_FAULT;
2064 }
2065 break;
2066 case MFI_OMSK:
2067 trace_megasas_mmio_writel("MFI_OMSK", val);
2068 s->intr_mask = val;
2069 if (!megasas_intr_enabled(s) &&
2070 !msi_enabled(pci_dev) &&
2071 !msix_enabled(pci_dev)) {
2072 trace_megasas_irq_lower();
2073 pci_irq_deassert(pci_dev);
2074 }
2075 if (megasas_intr_enabled(s)) {
2076 if (msix_enabled(pci_dev)) {
2077 trace_megasas_msix_enabled(0);
2078 } else if (msi_enabled(pci_dev)) {
2079 trace_megasas_msi_enabled(0);
2080 } else {
2081 trace_megasas_intr_enabled();
2082 }
2083 } else {
2084 trace_megasas_intr_disabled();
2085 megasas_soft_reset(s);
2086 }
2087 break;
2088 case MFI_ODCR0:
2089 trace_megasas_mmio_writel("MFI_ODCR0", val);
2090 s->doorbell = 0;
2091 if (megasas_intr_enabled(s)) {
2092 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
2093 trace_megasas_irq_lower();
2094 pci_irq_deassert(pci_dev);
2095 }
2096 }
2097 break;
2098 case MFI_IQPH:
2099 trace_megasas_mmio_writel("MFI_IQPH", val);
2100
2101 s->frame_hi = val;
2102 break;
2103 case MFI_IQPL:
2104 trace_megasas_mmio_writel("MFI_IQPL", val);
2105
2106
2107 case MFI_IQP:
2108 if (addr == MFI_IQP) {
2109 trace_megasas_mmio_writel("MFI_IQP", val);
2110
2111 s->frame_hi = 0;
2112 }
2113 frame_addr = (val & ~0x1F);
2114
2115 frame_addr |= ((uint64_t)s->frame_hi << 32);
2116 s->frame_hi = 0;
2117 frame_count = (val >> 1) & 0xF;
2118 megasas_handle_frame(s, frame_addr, frame_count);
2119 break;
2120 case MFI_SEQ:
2121 trace_megasas_mmio_writel("MFI_SEQ", val);
2122
2123 if (adp_reset_seq[s->adp_reset++] == val) {
2124 if (s->adp_reset == 6) {
2125 s->adp_reset = 0;
2126 s->diag = MFI_DIAG_WRITE_ENABLE;
2127 }
2128 } else {
2129 s->adp_reset = 0;
2130 s->diag = 0;
2131 }
2132 break;
2133 case MFI_DIAG:
2134 trace_megasas_mmio_writel("MFI_DIAG", val);
2135
2136 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2137 (val & MFI_DIAG_RESET_ADP)) {
2138 s->diag |= MFI_DIAG_RESET_ADP;
2139 megasas_soft_reset(s);
2140 s->adp_reset = 0;
2141 s->diag = 0;
2142 }
2143 break;
2144 default:
2145 trace_megasas_mmio_invalid_writel(addr, val);
2146 break;
2147 }
2148}
2149
2150static const MemoryRegionOps megasas_mmio_ops = {
2151 .read = megasas_mmio_read,
2152 .write = megasas_mmio_write,
2153 .endianness = DEVICE_LITTLE_ENDIAN,
2154 .impl = {
2155 .min_access_size = 8,
2156 .max_access_size = 8,
2157 }
2158};
2159
2160static uint64_t megasas_port_read(void *opaque, hwaddr addr,
2161 unsigned size)
2162{
2163 return megasas_mmio_read(opaque, addr & 0xff, size);
2164}
2165
2166static void megasas_port_write(void *opaque, hwaddr addr,
2167 uint64_t val, unsigned size)
2168{
2169 megasas_mmio_write(opaque, addr & 0xff, val, size);
2170}
2171
2172static const MemoryRegionOps megasas_port_ops = {
2173 .read = megasas_port_read,
2174 .write = megasas_port_write,
2175 .endianness = DEVICE_LITTLE_ENDIAN,
2176 .impl = {
2177 .min_access_size = 4,
2178 .max_access_size = 4,
2179 }
2180};
2181
2182static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
2183 unsigned size)
2184{
2185 return 0;
2186}
2187
2188static void megasas_queue_write(void *opaque, hwaddr addr,
2189 uint64_t val, unsigned size)
2190{
2191 return;
2192}
2193
2194static const MemoryRegionOps megasas_queue_ops = {
2195 .read = megasas_queue_read,
2196 .write = megasas_queue_write,
2197 .endianness = DEVICE_LITTLE_ENDIAN,
2198 .impl = {
2199 .min_access_size = 8,
2200 .max_access_size = 8,
2201 }
2202};
2203
2204static void megasas_soft_reset(MegasasState *s)
2205{
2206 int i;
2207 MegasasCmd *cmd;
2208
2209 trace_megasas_reset(s->fw_state);
2210 for (i = 0; i < s->fw_cmds; i++) {
2211 cmd = &s->frames[i];
2212 megasas_abort_command(cmd);
2213 }
2214 if (s->fw_state == MFI_FWSTATE_READY) {
2215 BusChild *kid;
2216
2217
2218
2219
2220
2221
2222 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2223 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
2224
2225 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2226 scsi_device_unit_attention_reported(sdev);
2227 }
2228 }
2229 megasas_reset_frames(s);
2230 s->reply_queue_len = s->fw_cmds;
2231 s->reply_queue_pa = 0;
2232 s->consumer_pa = 0;
2233 s->producer_pa = 0;
2234 s->fw_state = MFI_FWSTATE_READY;
2235 s->doorbell = 0;
2236 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2237 s->frame_hi = 0;
2238 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2239 s->event_count++;
2240 s->boot_event = s->event_count;
2241}
2242
2243static void megasas_scsi_reset(DeviceState *dev)
2244{
2245 MegasasState *s = MEGASAS(dev);
2246
2247 megasas_soft_reset(s);
2248}
2249
2250static const VMStateDescription vmstate_megasas_gen1 = {
2251 .name = "megasas",
2252 .version_id = 0,
2253 .minimum_version_id = 0,
2254 .fields = (VMStateField[]) {
2255 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2256 VMSTATE_MSIX(parent_obj, MegasasState),
2257
2258 VMSTATE_INT32(fw_state, MegasasState),
2259 VMSTATE_INT32(intr_mask, MegasasState),
2260 VMSTATE_INT32(doorbell, MegasasState),
2261 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2262 VMSTATE_UINT64(consumer_pa, MegasasState),
2263 VMSTATE_UINT64(producer_pa, MegasasState),
2264 VMSTATE_END_OF_LIST()
2265 }
2266};
2267
2268static const VMStateDescription vmstate_megasas_gen2 = {
2269 .name = "megasas-gen2",
2270 .version_id = 0,
2271 .minimum_version_id = 0,
2272 .minimum_version_id_old = 0,
2273 .fields = (VMStateField[]) {
2274 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2275 VMSTATE_MSIX(parent_obj, MegasasState),
2276
2277 VMSTATE_INT32(fw_state, MegasasState),
2278 VMSTATE_INT32(intr_mask, MegasasState),
2279 VMSTATE_INT32(doorbell, MegasasState),
2280 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2281 VMSTATE_UINT64(consumer_pa, MegasasState),
2282 VMSTATE_UINT64(producer_pa, MegasasState),
2283 VMSTATE_END_OF_LIST()
2284 }
2285};
2286
2287static void megasas_scsi_uninit(PCIDevice *d)
2288{
2289 MegasasState *s = MEGASAS(d);
2290
2291 if (megasas_use_msix(s)) {
2292 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2293 }
2294 msi_uninit(d);
2295}
2296
2297static const struct SCSIBusInfo megasas_scsi_info = {
2298 .tcq = true,
2299 .max_target = MFI_MAX_LD,
2300 .max_lun = 255,
2301
2302 .transfer_data = megasas_xfer_complete,
2303 .get_sg_list = megasas_get_sg_list,
2304 .complete = megasas_command_complete,
2305 .cancel = megasas_command_cancelled,
2306};
2307
2308static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
2309{
2310 MegasasState *s = MEGASAS(dev);
2311 MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
2312 uint8_t *pci_conf;
2313 int i, bar_type;
2314 Error *err = NULL;
2315 int ret;
2316
2317 pci_conf = dev->config;
2318
2319
2320 pci_conf[PCI_LATENCY_TIMER] = 0;
2321
2322 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2323
2324 if (s->msi != ON_OFF_AUTO_OFF) {
2325 ret = msi_init(dev, 0x50, 1, true, false, &err);
2326
2327
2328 assert(!ret || ret == -ENOTSUP);
2329 if (ret && s->msi == ON_OFF_AUTO_ON) {
2330
2331 error_append_hint(&err, "You have to use msi=auto (default) or "
2332 "msi=off with this machine type.\n");
2333 error_propagate(errp, err);
2334 return;
2335 } else if (ret) {
2336
2337 s->msi = ON_OFF_AUTO_OFF;
2338 error_free(err);
2339 }
2340 }
2341
2342 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
2343 "megasas-mmio", 0x4000);
2344 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
2345 "megasas-io", 256);
2346 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
2347 "megasas-queue", 0x40000);
2348
2349 if (megasas_use_msix(s) &&
2350 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2351 &s->mmio_io, b->mmio_bar, 0x3800, 0x68, NULL)) {
2352
2353 s->msix = ON_OFF_AUTO_OFF;
2354 }
2355
2356 if (pci_is_express(dev)) {
2357 pcie_endpoint_cap_init(dev, 0xa0);
2358 }
2359
2360 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
2361 pci_register_bar(dev, b->ioport_bar,
2362 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2363 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
2364 pci_register_bar(dev, 3, bar_type, &s->queue_io);
2365
2366 if (megasas_use_msix(s)) {
2367 msix_vector_use(dev, 0);
2368 }
2369
2370 s->fw_state = MFI_FWSTATE_READY;
2371 if (!s->sas_addr) {
2372 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2373 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2374 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2375 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2376 s->sas_addr |= PCI_FUNC(dev->devfn);
2377 }
2378 if (!s->hba_serial) {
2379 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
2380 }
2381 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2382 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2383 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2384 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2385 } else {
2386 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2387 }
2388 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2389 s->fw_cmds = MEGASAS_MAX_FRAMES;
2390 }
2391 trace_megasas_init(s->fw_sge, s->fw_cmds,
2392 megasas_is_jbod(s) ? "jbod" : "raid");
2393
2394 if (megasas_is_jbod(s)) {
2395 s->fw_luns = MFI_MAX_SYS_PDS;
2396 } else {
2397 s->fw_luns = MFI_MAX_LD;
2398 }
2399 s->producer_pa = 0;
2400 s->consumer_pa = 0;
2401 for (i = 0; i < s->fw_cmds; i++) {
2402 s->frames[i].index = i;
2403 s->frames[i].context = -1;
2404 s->frames[i].pa = 0;
2405 s->frames[i].state = s;
2406 }
2407
2408 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2409 &megasas_scsi_info, NULL);
2410}
2411
2412static Property megasas_properties_gen1[] = {
2413 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2414 MEGASAS_DEFAULT_SGE),
2415 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2416 MEGASAS_DEFAULT_FRAMES),
2417 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2418 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2419 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2420 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2421 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2422 MEGASAS_FLAG_USE_JBOD, false),
2423 DEFINE_PROP_END_OF_LIST(),
2424};
2425
2426static Property megasas_properties_gen2[] = {
2427 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2428 MEGASAS_DEFAULT_SGE),
2429 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2430 MEGASAS_GEN2_DEFAULT_FRAMES),
2431 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2432 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2433 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2434 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2435 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2436 MEGASAS_FLAG_USE_JBOD, false),
2437 DEFINE_PROP_END_OF_LIST(),
2438};
2439
2440typedef struct MegasasInfo {
2441 const char *name;
2442 const char *desc;
2443 const char *product_name;
2444 const char *product_version;
2445 uint16_t device_id;
2446 uint16_t subsystem_id;
2447 int ioport_bar;
2448 int mmio_bar;
2449 bool is_express;
2450 int osts;
2451 const VMStateDescription *vmsd;
2452 Property *props;
2453} MegasasInfo;
2454
2455static struct MegasasInfo megasas_devices[] = {
2456 {
2457 .name = TYPE_MEGASAS_GEN1,
2458 .desc = "LSI MegaRAID SAS 1078",
2459 .product_name = "LSI MegaRAID SAS 8708EM2",
2460 .product_version = MEGASAS_VERSION_GEN1,
2461 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2462 .subsystem_id = 0x1013,
2463 .ioport_bar = 2,
2464 .mmio_bar = 0,
2465 .osts = MFI_1078_RM | 1,
2466 .is_express = false,
2467 .vmsd = &vmstate_megasas_gen1,
2468 .props = megasas_properties_gen1,
2469 },{
2470 .name = TYPE_MEGASAS_GEN2,
2471 .desc = "LSI MegaRAID SAS 2108",
2472 .product_name = "LSI MegaRAID SAS 9260-8i",
2473 .product_version = MEGASAS_VERSION_GEN2,
2474 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2475 .subsystem_id = 0x9261,
2476 .ioport_bar = 0,
2477 .mmio_bar = 1,
2478 .osts = MFI_GEN2_RM,
2479 .is_express = true,
2480 .vmsd = &vmstate_megasas_gen2,
2481 .props = megasas_properties_gen2,
2482 }
2483};
2484
2485static void megasas_class_init(ObjectClass *oc, void *data)
2486{
2487 DeviceClass *dc = DEVICE_CLASS(oc);
2488 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2489 MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
2490 const MegasasInfo *info = data;
2491
2492 pc->realize = megasas_scsi_realize;
2493 pc->exit = megasas_scsi_uninit;
2494 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2495 pc->device_id = info->device_id;
2496 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2497 pc->subsystem_id = info->subsystem_id;
2498 pc->class_id = PCI_CLASS_STORAGE_RAID;
2499 pc->is_express = info->is_express;
2500 e->mmio_bar = info->mmio_bar;
2501 e->ioport_bar = info->ioport_bar;
2502 e->osts = info->osts;
2503 e->product_name = info->product_name;
2504 e->product_version = info->product_version;
2505 dc->props = info->props;
2506 dc->reset = megasas_scsi_reset;
2507 dc->vmsd = info->vmsd;
2508 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2509 dc->desc = info->desc;
2510}
2511
2512static const TypeInfo megasas_info = {
2513 .name = TYPE_MEGASAS_BASE,
2514 .parent = TYPE_PCI_DEVICE,
2515 .instance_size = sizeof(MegasasState),
2516 .class_size = sizeof(MegasasBaseClass),
2517 .abstract = true,
2518};
2519
2520static void megasas_register_types(void)
2521{
2522 int i;
2523
2524 type_register_static(&megasas_info);
2525 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2526 const MegasasInfo *info = &megasas_devices[i];
2527 TypeInfo type_info = {};
2528
2529 type_info.name = info->name;
2530 type_info.parent = TYPE_MEGASAS_BASE;
2531 type_info.class_data = (void *)info;
2532 type_info.class_init = megasas_class_init;
2533
2534 type_register(&type_info);
2535 }
2536}
2537
2538type_init(megasas_register_types)
2539
