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14#ifndef HW_VIRTIO_GPU_H
15#define HW_VIRTIO_GPU_H
16
17#include "qemu/queue.h"
18#include "ui/qemu-pixman.h"
19#include "ui/console.h"
20#include "hw/virtio/virtio.h"
21#include "hw/pci/pci.h"
22#include "qemu/log.h"
23
24#include "standard-headers/linux/virtio_gpu.h"
25#define TYPE_VIRTIO_GPU "virtio-gpu-device"
26#define VIRTIO_GPU(obj) \
27 OBJECT_CHECK(VirtIOGPU, (obj), TYPE_VIRTIO_GPU)
28
29#define VIRTIO_ID_GPU 16
30
31struct virtio_gpu_simple_resource {
32 uint32_t resource_id;
33 uint32_t width;
34 uint32_t height;
35 uint32_t format;
36 uint64_t *addrs;
37 struct iovec *iov;
38 unsigned int iov_cnt;
39 uint32_t scanout_bitmask;
40 pixman_image_t *image;
41 uint64_t hostmem;
42 QTAILQ_ENTRY(virtio_gpu_simple_resource) next;
43};
44
45struct virtio_gpu_scanout {
46 QemuConsole *con;
47 DisplaySurface *ds;
48 uint32_t width, height;
49 int x, y;
50 int invalidate;
51 uint32_t resource_id;
52 struct virtio_gpu_update_cursor cursor;
53 QEMUCursor *current_cursor;
54};
55
56struct virtio_gpu_requested_state {
57 uint32_t width, height;
58 int x, y;
59};
60
61enum virtio_gpu_conf_flags {
62 VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
63 VIRTIO_GPU_FLAG_STATS_ENABLED,
64};
65
66#define virtio_gpu_virgl_enabled(_cfg) \
67 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
68#define virtio_gpu_stats_enabled(_cfg) \
69 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
70
71struct virtio_gpu_conf {
72 uint64_t max_hostmem;
73 uint32_t max_outputs;
74 uint32_t flags;
75};
76
77struct virtio_gpu_ctrl_command {
78 VirtQueueElement elem;
79 VirtQueue *vq;
80 struct virtio_gpu_ctrl_hdr cmd_hdr;
81 uint32_t error;
82 bool waiting;
83 bool finished;
84 QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
85};
86
87typedef struct VirtIOGPU {
88 VirtIODevice parent_obj;
89
90 QEMUBH *ctrl_bh;
91 QEMUBH *cursor_bh;
92 VirtQueue *ctrl_vq;
93 VirtQueue *cursor_vq;
94
95 int enable;
96
97 int config_size;
98 DeviceState *qdev;
99
100 QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
101 QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
102 QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
103
104 struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS];
105 struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS];
106
107 struct virtio_gpu_conf conf;
108 uint64_t hostmem;
109 int enabled_output_bitmask;
110 struct virtio_gpu_config virtio_config;
111
112 bool use_virgl_renderer;
113 bool renderer_inited;
114 int renderer_blocked;
115 QEMUTimer *fence_poll;
116 QEMUTimer *print_stats;
117
118 uint32_t inflight;
119 struct {
120 uint32_t max_inflight;
121 uint32_t requests;
122 uint32_t req_3d;
123 uint32_t bytes_3d;
124 } stats;
125
126 Error *migration_blocker;
127} VirtIOGPU;
128
129extern const GraphicHwOps virtio_gpu_ops;
130
131
132#define DEFINE_VIRTIO_GPU_PCI_PROPERTIES(_state) \
133 DEFINE_PROP_BIT("ioeventfd", _state, flags, \
134 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, false), \
135 DEFINE_PROP_UINT32("vectors", _state, nvectors, 3)
136
137#define VIRTIO_GPU_FILL_CMD(out) do { \
138 size_t s; \
139 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
140 &out, sizeof(out)); \
141 if (s != sizeof(out)) { \
142 qemu_log_mask(LOG_GUEST_ERROR, \
143 "%s: command size incorrect %zu vs %zu\n", \
144 __func__, s, sizeof(out)); \
145 return; \
146 } \
147 } while (0)
148
149
150void virtio_gpu_ctrl_response(VirtIOGPU *g,
151 struct virtio_gpu_ctrl_command *cmd,
152 struct virtio_gpu_ctrl_hdr *resp,
153 size_t resp_len);
154void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
155 struct virtio_gpu_ctrl_command *cmd,
156 enum virtio_gpu_ctrl_type type);
157void virtio_gpu_get_display_info(VirtIOGPU *g,
158 struct virtio_gpu_ctrl_command *cmd);
159int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,
160 struct virtio_gpu_ctrl_command *cmd,
161 uint64_t **addr, struct iovec **iov);
162void virtio_gpu_cleanup_mapping_iov(struct iovec *iov, uint32_t count);
163void virtio_gpu_process_cmdq(VirtIOGPU *g);
164
165
166void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
167 struct virtio_gpu_ctrl_command *cmd);
168void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
169void virtio_gpu_virgl_reset(VirtIOGPU *g);
170int virtio_gpu_virgl_init(VirtIOGPU *g);
171
172#endif
173