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22#include "qemu/osdep.h"
23#include "qapi/error.h"
24#include "qemu-common.h"
25#include "cpu.h"
26#include "hw/arm/fsl-imx31.h"
27#include "sysemu/sysemu.h"
28#include "exec/address-spaces.h"
29#include "hw/boards.h"
30#include "chardev/char.h"
31
32static void fsl_imx31_init(Object *obj)
33{
34 FslIMX31State *s = FSL_IMX31(obj);
35 int i;
36
37 object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);
38
39 sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
40 TYPE_IMX_AVIC);
41
42 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);
43
44 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
45 sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
46 TYPE_IMX_SERIAL);
47 }
48
49 sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);
50
51 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
52 sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
53 TYPE_IMX_EPIT);
54 }
55
56 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
57 sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
58 TYPE_IMX_I2C);
59 }
60
61 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
62 sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
63 TYPE_IMX_GPIO);
64 }
65}
66
67static void fsl_imx31_realize(DeviceState *dev, Error **errp)
68{
69 FslIMX31State *s = FSL_IMX31(dev);
70 uint16_t i;
71 Error *err = NULL;
72
73 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
74 if (err) {
75 error_propagate(errp, err);
76 return;
77 }
78
79 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
80 if (err) {
81 error_propagate(errp, err);
82 return;
83 }
84 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
85 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
86 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
87 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
88 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
89
90 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
91 if (err) {
92 error_propagate(errp, err);
93 return;
94 }
95 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
96
97
98 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
99 static const struct {
100 hwaddr addr;
101 unsigned int irq;
102 } serial_table[FSL_IMX31_NUM_UARTS] = {
103 { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
104 { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
105 };
106
107 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
108
109 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
110 if (err) {
111 error_propagate(errp, err);
112 return;
113 }
114
115 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
116 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
117 qdev_get_gpio_in(DEVICE(&s->avic),
118 serial_table[i].irq));
119 }
120
121 s->gpt.ccm = IMX_CCM(&s->ccm);
122
123 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
124 if (err) {
125 error_propagate(errp, err);
126 return;
127 }
128
129 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
130 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
131 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));
132
133
134 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
135 static const struct {
136 hwaddr addr;
137 unsigned int irq;
138 } epit_table[FSL_IMX31_NUM_EPITS] = {
139 { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
140 { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
141 };
142
143 s->epit[i].ccm = IMX_CCM(&s->ccm);
144
145 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
146 if (err) {
147 error_propagate(errp, err);
148 return;
149 }
150
151 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
152 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
153 qdev_get_gpio_in(DEVICE(&s->avic),
154 epit_table[i].irq));
155 }
156
157
158 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
159 static const struct {
160 hwaddr addr;
161 unsigned int irq;
162 } i2c_table[FSL_IMX31_NUM_I2CS] = {
163 { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
164 { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
165 { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
166 };
167
168
169 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
170 if (err) {
171 error_propagate(errp, err);
172 return;
173 }
174
175 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
176
177 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
178 qdev_get_gpio_in(DEVICE(&s->avic),
179 i2c_table[i].irq));
180 }
181
182
183 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
184 static const struct {
185 hwaddr addr;
186 unsigned int irq;
187 } gpio_table[FSL_IMX31_NUM_GPIOS] = {
188 { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
189 { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
190 { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
191 };
192
193 object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
194 &error_abort);
195 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
196 if (err) {
197 error_propagate(errp, err);
198 return;
199 }
200 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
201
202 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
203 qdev_get_gpio_in(DEVICE(&s->avic),
204 gpio_table[i].irq));
205 }
206
207
208 memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom",
209 FSL_IMX31_SECURE_ROM_SIZE, &err);
210 if (err) {
211 error_propagate(errp, err);
212 return;
213 }
214 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
215 &s->secure_rom);
216
217
218 memory_region_init_rom(&s->rom, NULL, "imx31.rom",
219 FSL_IMX31_ROM_SIZE, &err);
220 if (err) {
221 error_propagate(errp, err);
222 return;
223 }
224 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
225 &s->rom);
226
227
228 memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
229 &err);
230 if (err) {
231 error_propagate(errp, err);
232 return;
233 }
234 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
235 &s->iram);
236
237
238 memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
239 &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
240 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
241 &s->iram_alias);
242}
243
244static void fsl_imx31_class_init(ObjectClass *oc, void *data)
245{
246 DeviceClass *dc = DEVICE_CLASS(oc);
247
248 dc->realize = fsl_imx31_realize;
249 dc->desc = "i.MX31 SOC";
250
251
252
253
254 dc->user_creatable = false;
255}
256
257static const TypeInfo fsl_imx31_type_info = {
258 .name = TYPE_FSL_IMX31,
259 .parent = TYPE_DEVICE,
260 .instance_size = sizeof(FslIMX31State),
261 .instance_init = fsl_imx31_init,
262 .class_init = fsl_imx31_class_init,
263};
264
265static void fsl_imx31_register_types(void)
266{
267 type_register_static(&fsl_imx31_type_info);
268}
269
270type_init(fsl_imx31_register_types)
271