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25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "qapi/error.h"
28#include "qemu-common.h"
29#include "hw/arm/arm.h"
30#include "exec/address-spaces.h"
31#include "hw/char/serial.h"
32#include "hw/boards.h"
33#include "hw/arm/msf2-soc.h"
34#include "hw/misc/unimp.h"
35
36#define MSF2_TIMER_BASE 0x40004000
37#define MSF2_SYSREG_BASE 0x40038000
38
39#define ENVM_BASE_ADDRESS 0x60000000
40
41#define SRAM_BASE_ADDRESS 0x20000000
42
43#define MSF2_ENVM_MAX_SIZE (512 * KiB)
44
45
46
47
48
49
50#define MSF2_ESRAM_MAX_SIZE (80 * KiB)
51
52static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
53static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
54
55static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
56static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
57static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
58
59static void do_sys_reset(void *opaque, int n, int level)
60{
61 if (level) {
62 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
63 }
64}
65
66static void m2sxxx_soc_initfn(Object *obj)
67{
68 MSF2State *s = MSF2_SOC(obj);
69 int i;
70
71 sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
72 TYPE_ARMV7M);
73
74 sysbus_init_child_obj(obj, "sysreg", &s->sysreg, sizeof(s->sysreg),
75 TYPE_MSF2_SYSREG);
76
77 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
78 TYPE_MSS_TIMER);
79
80 for (i = 0; i < MSF2_NUM_SPIS; i++) {
81 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
82 TYPE_MSS_SPI);
83 }
84}
85
86static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
87{
88 MSF2State *s = MSF2_SOC(dev_soc);
89 DeviceState *dev, *armv7m;
90 SysBusDevice *busdev;
91 Error *err = NULL;
92 int i;
93
94 MemoryRegion *system_memory = get_system_memory();
95 MemoryRegion *nvm = g_new(MemoryRegion, 1);
96 MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
97 MemoryRegion *sram = g_new(MemoryRegion, 1);
98
99 memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
100 &error_fatal);
101
102
103
104
105
106
107 memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",
108 nvm, 0, s->envm_size);
109
110 memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
111 memory_region_add_subregion(system_memory, 0, nvm_alias);
112
113 memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
114 &error_fatal);
115 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
116
117 armv7m = DEVICE(&s->armv7m);
118 qdev_prop_set_uint32(armv7m, "num-irq", 81);
119 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
120 object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
121 "memory", &error_abort);
122 object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
123 if (err != NULL) {
124 error_propagate(errp, err);
125 return;
126 }
127
128 if (!s->m3clk) {
129 error_setg(errp, "Invalid m3clk value");
130 error_append_hint(errp, "m3clk can not be zero\n");
131 return;
132 }
133
134 qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
135 qemu_allocate_irq(&do_sys_reset, NULL, 0));
136
137 system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
138
139 for (i = 0; i < MSF2_NUM_UARTS; i++) {
140 if (serial_hd(i)) {
141 serial_mm_init(get_system_memory(), uart_addr[i], 2,
142 qdev_get_gpio_in(armv7m, uart_irq[i]),
143 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
144 }
145 }
146
147 dev = DEVICE(&s->timer);
148
149 qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
150 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
151 if (err != NULL) {
152 error_propagate(errp, err);
153 return;
154 }
155 busdev = SYS_BUS_DEVICE(dev);
156 sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
157 sysbus_connect_irq(busdev, 0,
158 qdev_get_gpio_in(armv7m, timer_irq[0]));
159 sysbus_connect_irq(busdev, 1,
160 qdev_get_gpio_in(armv7m, timer_irq[1]));
161
162 dev = DEVICE(&s->sysreg);
163 qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
164 qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
165 object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
166 if (err != NULL) {
167 error_propagate(errp, err);
168 return;
169 }
170 busdev = SYS_BUS_DEVICE(dev);
171 sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
172
173 for (i = 0; i < MSF2_NUM_SPIS; i++) {
174 gchar *bus_name;
175
176 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
177 if (err != NULL) {
178 error_propagate(errp, err);
179 return;
180 }
181
182 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
183 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
184 qdev_get_gpio_in(armv7m, spi_irq[i]));
185
186
187 bus_name = g_strdup_printf("spi%d", i);
188 object_property_add_alias(OBJECT(s), bus_name,
189 OBJECT(&s->spi[i]), "spi",
190 &error_abort);
191 g_free(bus_name);
192 }
193
194
195 create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
196 create_unimplemented_device("dma", 0x40003000, 0x1000);
197 create_unimplemented_device("watchdog", 0x40005000, 0x1000);
198 create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
199 create_unimplemented_device("gpio", 0x40013000, 0x1000);
200 create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
201 create_unimplemented_device("can", 0x40015000, 0x1000);
202 create_unimplemented_device("rtc", 0x40017000, 0x1000);
203 create_unimplemented_device("apb_config", 0x40020000, 0x10000);
204 create_unimplemented_device("emac", 0x40041000, 0x1000);
205 create_unimplemented_device("usb", 0x40043000, 0x1000);
206}
207
208static Property m2sxxx_soc_properties[] = {
209
210
211
212
213 DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
214 DEFINE_PROP_STRING("part-name", MSF2State, part_name),
215 DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
216 DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
217 MSF2_ESRAM_MAX_SIZE),
218
219 DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
220
221 DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
222 DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
223 DEFINE_PROP_END_OF_LIST(),
224};
225
226static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
227{
228 DeviceClass *dc = DEVICE_CLASS(klass);
229
230 dc->realize = m2sxxx_soc_realize;
231 dc->props = m2sxxx_soc_properties;
232}
233
234static const TypeInfo m2sxxx_soc_info = {
235 .name = TYPE_MSF2_SOC,
236 .parent = TYPE_SYS_BUS_DEVICE,
237 .instance_size = sizeof(MSF2State),
238 .instance_init = m2sxxx_soc_initfn,
239 .class_init = m2sxxx_soc_class_init,
240};
241
242static void m2sxxx_soc_types(void)
243{
244 type_register_static(&m2sxxx_soc_info);
245}
246
247type_init(m2sxxx_soc_types)
248