LXR qemu/hw/arm/realview.c

   1/*
   2 * ARM RealView Baseboard System emulation.
   3 *
   4 * Copyright (c) 2006-2007 CodeSourcery.
   5 * Written by Paul Brook
   6 *
   7 * This code is licensed under the GPL.
   8 */
   9
  10#include "qemu/osdep.h"
  11#include "qapi/error.h"
  12#include "qemu-common.h"
  13#include "cpu.h"
  14#include "hw/sysbus.h"
  15#include "hw/arm/arm.h"
  16#include "hw/arm/primecell.h"
  17#include "hw/devices.h"
  18#include "hw/pci/pci.h"
  19#include "net/net.h"
  20#include "sysemu/sysemu.h"
  21#include "hw/boards.h"
  22#include "hw/i2c/i2c.h"
  23#include "exec/address-spaces.h"
  24#include "qemu/error-report.h"
  25#include "hw/char/pl011.h"
  26#include "hw/cpu/a9mpcore.h"
  27#include "hw/intc/realview_gic.h"
  28
  29#define SMP_BOOT_ADDR 0xe0000000
  30#define SMP_BOOTREG_ADDR 0x10000030
  31
  32/* Board init.  */
  33
  34static struct arm_boot_info realview_binfo = {
  35    .smp_loader_start = SMP_BOOT_ADDR,
  36    .smp_bootreg_addr = SMP_BOOTREG_ADDR,
  37};
  38
  39/* The following two lists must be consistent.  */
  40enum realview_board_type {
  41    BOARD_EB,
  42    BOARD_EB_MPCORE,
  43    BOARD_PB_A8,
  44    BOARD_PBX_A9,
  45};
  46
  47static const int realview_board_id[] = {
  48    0x33b,
  49    0x33b,
  50    0x769,
  51    0x76d
  52};
  53
  54static void realview_init(MachineState *machine,
  55                          enum realview_board_type board_type)
  56{
  57    ARMCPU *cpu = NULL;
  58    CPUARMState *env;
  59    MemoryRegion *sysmem = get_system_memory();
  60    MemoryRegion *ram_lo;
  61    MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
  62    MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
  63    MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
  64    DeviceState *dev, *sysctl, *gpio2, *pl041;
  65    SysBusDevice *busdev;
  66    qemu_irq pic[64];
  67    qemu_irq mmc_irq[2];
  68    PCIBus *pci_bus = NULL;
  69    NICInfo *nd;
  70    I2CBus *i2c;
  71    int n;
  72    int done_nic = 0;
  73    qemu_irq cpu_irq[4];
  74    int is_mpcore = 0;
  75    int is_pb = 0;
  76    uint32_t proc_id = 0;
  77    uint32_t sys_id;
  78    ram_addr_t low_ram_size;
  79    ram_addr_t ram_size = machine->ram_size;
  80    hwaddr periphbase = 0;
  81
  82    switch (board_type) {
  83    case BOARD_EB:
  84        break;
  85    case BOARD_EB_MPCORE:
  86        is_mpcore = 1;
  87        periphbase = 0x10100000;
  88        break;
  89    case BOARD_PB_A8:
  90        is_pb = 1;
  91        break;
  92    case BOARD_PBX_A9:
  93        is_mpcore = 1;
  94        is_pb = 1;
  95        periphbase = 0x1f000000;
  96        break;
  97    }
  98
  99    for (n = 0; n < smp_cpus; n++) {
 100        Object *cpuobj = object_new(machine->cpu_type);
 101
 102        /* By default A9,A15 and ARM1176 CPUs have EL3 enabled.  This board
 103         * does not currently support EL3 so the CPU EL3 property is disabled
 104         * before realization.
 105         */
 106        if (object_property_find(cpuobj, "has_el3", NULL)) {
 107            object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
 108        }
 109
 110        if (is_pb && is_mpcore) {
 111            object_property_set_int(cpuobj, periphbase, "reset-cbar",
 112                                    &error_fatal);
 113        }
 114
 115        object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 116
 117        cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
 118    }
 119    cpu = ARM_CPU(first_cpu);
 120    env = &cpu->env;
 121    if (arm_feature(env, ARM_FEATURE_V7)) {
 122        if (is_mpcore) {
 123            proc_id = 0x0c000000;
 124        } else {
 125            proc_id = 0x0e000000;
 126        }
 127    } else if (arm_feature(env, ARM_FEATURE_V6K)) {
 128        proc_id = 0x06000000;
 129    } else if (arm_feature(env, ARM_FEATURE_V6)) {
 130        proc_id = 0x04000000;
 131    } else {
 132        proc_id = 0x02000000;
 133    }
 134
 135    if (is_pb && ram_size > 0x20000000) {
 136        /* Core tile RAM.  */
 137        ram_lo = g_new(MemoryRegion, 1);
 138        low_ram_size = ram_size - 0x20000000;
 139        ram_size = 0x20000000;
 140        memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size,
 141                               &error_fatal);
 142        memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
 143    }
 144
 145    memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size,
 146                           &error_fatal);
 147    low_ram_size = ram_size;
 148    if (low_ram_size > 0x10000000)
 149      low_ram_size = 0x10000000;
 150    /* SDRAM at address zero.  */
 151    memory_region_init_alias(ram_alias, NULL, "realview.alias",
 152                             ram_hi, 0, low_ram_size);
 153    memory_region_add_subregion(sysmem, 0, ram_alias);
 154    if (is_pb) {
 155        /* And again at a high address.  */
 156        memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
 157    } else {
 158        ram_size = low_ram_size;
 159    }
 160
 161    sys_id = is_pb ? 0x01780500 : 0xc1400400;
 162    sysctl = qdev_create(NULL, "realview_sysctl");
 163    qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 164    qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
 165    qdev_init_nofail(sysctl);
 166    sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
 167
 168    if (is_mpcore) {
 169        dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
 170        qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 171        qdev_init_nofail(dev);
 172        busdev = SYS_BUS_DEVICE(dev);
 173        sysbus_mmio_map(busdev, 0, periphbase);
 174        for (n = 0; n < smp_cpus; n++) {
 175            sysbus_connect_irq(busdev, n, cpu_irq[n]);
 176        }
 177        sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL);
 178        /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */
 179        realview_binfo.gic_cpu_if_addr = periphbase + 0x100;
 180    } else {
 181        uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
 182        /* For now just create the nIRQ GIC, and ignore the others.  */
 183        dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]);
 184    }
 185    for (n = 0; n < 64; n++) {
 186        pic[n] = qdev_get_gpio_in(dev, n);
 187    }
 188
 189    pl041 = qdev_create(NULL, "pl041");
 190    qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 191    qdev_init_nofail(pl041);
 192    sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
 193    sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);
 194
 195    sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
 196    sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
 197
 198    pl011_create(0x10009000, pic[12], serial_hd(0));
 199    pl011_create(0x1000a000, pic[13], serial_hd(1));
 200    pl011_create(0x1000b000, pic[14], serial_hd(2));
 201    pl011_create(0x1000c000, pic[15], serial_hd(3));
 202
 203    /* DMA controller is optional, apparently.  */
 204    sysbus_create_simple("pl081", 0x10030000, pic[24]);
 205
 206    sysbus_create_simple("sp804", 0x10011000, pic[4]);
 207    sysbus_create_simple("sp804", 0x10012000, pic[5]);
 208
 209    sysbus_create_simple("pl061", 0x10013000, pic[6]);
 210    sysbus_create_simple("pl061", 0x10014000, pic[7]);
 211    gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
 212
 213    sysbus_create_simple("pl111", 0x10020000, pic[23]);
 214
 215    dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
 216    /* Wire up MMC card detect and read-only signals. These have
 217     * to go to both the PL061 GPIO and the sysctl register.
 218     * Note that the PL181 orders these lines (readonly,inserted)
 219     * and the PL061 has them the other way about. Also the card
 220     * detect line is inverted.
 221     */
 222    mmc_irq[0] = qemu_irq_split(
 223        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
 224        qdev_get_gpio_in(gpio2, 1));
 225    mmc_irq[1] = qemu_irq_split(
 226        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
 227        qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
 228    qdev_connect_gpio_out(dev, 0, mmc_irq[0]);
 229    qdev_connect_gpio_out(dev, 1, mmc_irq[1]);
 230
 231    sysbus_create_simple("pl031", 0x10017000, pic[10]);
 232
 233    if (!is_pb) {
 234        dev = qdev_create(NULL, "realview_pci");
 235        busdev = SYS_BUS_DEVICE(dev);
 236        qdev_init_nofail(dev);
 237        sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
 238        sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
 239        sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */
 240        sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */
 241        sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */
 242        sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */
 243        sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */
 244        sysbus_connect_irq(busdev, 0, pic[48]);
 245        sysbus_connect_irq(busdev, 1, pic[49]);
 246        sysbus_connect_irq(busdev, 2, pic[50]);
 247        sysbus_connect_irq(busdev, 3, pic[51]);
 248        pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 249        if (machine_usb(machine)) {
 250            pci_create_simple(pci_bus, -1, "pci-ohci");
 251        }
 252        n = drive_get_max_bus(IF_SCSI);
 253        while (n >= 0) {
 254            lsi53c895a_create(pci_bus);
 255            n--;
 256        }
 257    }
 258    for(n = 0; n < nb_nics; n++) {
 259        nd = &nd_table[n];
 260
 261        if (!done_nic && (!nd->model ||
 262                    strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
 263            if (is_pb) {
 264                lan9118_init(nd, 0x4e000000, pic[28]);
 265            } else {
 266                smc91c111_init(nd, 0x4e000000, pic[28]);
 267            }
 268            done_nic = 1;
 269        } else {
 270            if (pci_bus) {
 271                pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
 272            }
 273        }
 274    }
 275
 276    dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
 277    i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 278    i2c_create_slave(i2c, "ds1338", 0x68);
 279
 280    /* Memory map for RealView Emulation Baseboard:  */
 281    /* 0x10000000 System registers.  */
 282    /*  0x10001000 System controller.  */
 283    /* 0x10002000 Two-Wire Serial Bus.  */
 284    /* 0x10003000 Reserved.  */
 285    /*  0x10004000 AACI.  */
 286    /*  0x10005000 MCI.  */
 287    /* 0x10006000 KMI0.  */
 288    /* 0x10007000 KMI1.  */
 289    /*  0x10008000 Character LCD. (EB) */
 290    /* 0x10009000 UART0.  */
 291    /* 0x1000a000 UART1.  */
 292    /* 0x1000b000 UART2.  */
 293    /* 0x1000c000 UART3.  */
 294    /*  0x1000d000 SSPI.  */
 295    /*  0x1000e000 SCI.  */
 296    /* 0x1000f000 Reserved.  */
 297    /*  0x10010000 Watchdog.  */
 298    /* 0x10011000 Timer 0+1.  */
 299    /* 0x10012000 Timer 2+3.  */
 300    /*  0x10013000 GPIO 0.  */
 301    /*  0x10014000 GPIO 1.  */
 302    /*  0x10015000 GPIO 2.  */
 303    /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
 304    /* 0x10017000 RTC.  */
 305    /*  0x10018000 DMC.  */
 306    /*  0x10019000 PCI controller config.  */
 307    /*  0x10020000 CLCD.  */
 308    /* 0x10030000 DMA Controller.  */
 309    /* 0x10040000 GIC1. (EB) */
 310    /*  0x10050000 GIC2. (EB) */
 311    /*  0x10060000 GIC3. (EB) */
 312    /*  0x10070000 GIC4. (EB) */
 313    /*  0x10080000 SMC.  */
 314    /* 0x1e000000 GIC1. (PB) */
 315    /*  0x1e001000 GIC2. (PB) */
 316    /*  0x1e002000 GIC3. (PB) */
 317    /*  0x1e003000 GIC4. (PB) */
 318    /*  0x40000000 NOR flash.  */
 319    /*  0x44000000 DoC flash.  */
 320    /*  0x48000000 SRAM.  */
 321    /*  0x4c000000 Configuration flash.  */
 322    /* 0x4e000000 Ethernet.  */
 323    /*  0x4f000000 USB.  */
 324    /*  0x50000000 PISMO.  */
 325    /*  0x54000000 PISMO.  */
 326    /*  0x58000000 PISMO.  */
 327    /*  0x5c000000 PISMO.  */
 328    /* 0x60000000 PCI.  */
 329    /* 0x60000000 PCI Self Config.  */
 330    /* 0x61000000 PCI Config.  */
 331    /* 0x62000000 PCI IO.  */
 332    /* 0x63000000 PCI mem 0.  */
 333    /* 0x64000000 PCI mem 1.  */
 334    /* 0x68000000 PCI mem 2.  */
 335
 336    /* ??? Hack to map an additional page of ram for the secondary CPU
 337       startup code.  I guess this works on real hardware because the
 338       BootROM happens to be in ROM/flash or in memory that isn't clobbered
 339       until after Linux boots the secondary CPUs.  */
 340    memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000,
 341                           &error_fatal);
 342    memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
 343
 344    realview_binfo.ram_size = ram_size;
 345    realview_binfo.kernel_filename = machine->kernel_filename;
 346    realview_binfo.kernel_cmdline = machine->kernel_cmdline;
 347    realview_binfo.initrd_filename = machine->initrd_filename;
 348    realview_binfo.nb_cpus = smp_cpus;
 349    realview_binfo.board_id = realview_board_id[board_type];
 350    realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
 351    arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo);
 352}
 353
 354static void realview_eb_init(MachineState *machine)
 355{
 356    realview_init(machine, BOARD_EB);
 357}
 358
 359static void realview_eb_mpcore_init(MachineState *machine)
 360{
 361    realview_init(machine, BOARD_EB_MPCORE);
 362}
 363
 364static void realview_pb_a8_init(MachineState *machine)
 365{
 366    realview_init(machine, BOARD_PB_A8);
 367}
 368
 369static void realview_pbx_a9_init(MachineState *machine)
 370{
 371    realview_init(machine, BOARD_PBX_A9);
 372}
 373
 374static void realview_eb_class_init(ObjectClass *oc, void *data)
 375{
 376    MachineClass *mc = MACHINE_CLASS(oc);
 377
 378    mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)";
 379    mc->init = realview_eb_init;
 380    mc->block_default_type = IF_SCSI;
 381    mc->ignore_memory_transaction_failures = true;
 382    mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
 383}
 384
 385static const TypeInfo realview_eb_type = {
 386    .name = MACHINE_TYPE_NAME("realview-eb"),
 387    .parent = TYPE_MACHINE,
 388    .class_init = realview_eb_class_init,
 389};
 390
 391static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
 392{
 393    MachineClass *mc = MACHINE_CLASS(oc);
 394
 395    mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)";
 396    mc->init = realview_eb_mpcore_init;
 397    mc->block_default_type = IF_SCSI;
 398    mc->max_cpus = 4;
 399    mc->ignore_memory_transaction_failures = true;
 400    mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore");
 401}
 402
 403static const TypeInfo realview_eb_mpcore_type = {
 404    .name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
 405    .parent = TYPE_MACHINE,
 406    .class_init = realview_eb_mpcore_class_init,
 407};
 408
 409static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
 410{
 411    MachineClass *mc = MACHINE_CLASS(oc);
 412
 413    mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
 414    mc->init = realview_pb_a8_init;
 415    mc->ignore_memory_transaction_failures = true;
 416    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
 417}
 418
 419static const TypeInfo realview_pb_a8_type = {
 420    .name = MACHINE_TYPE_NAME("realview-pb-a8"),
 421    .parent = TYPE_MACHINE,
 422    .class_init = realview_pb_a8_class_init,
 423};
 424
 425static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
 426{
 427    MachineClass *mc = MACHINE_CLASS(oc);
 428
 429    mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9";
 430    mc->init = realview_pbx_a9_init;
 431    mc->max_cpus = 4;
 432    mc->ignore_memory_transaction_failures = true;
 433    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 434}
 435
 436static const TypeInfo realview_pbx_a9_type = {
 437    .name = MACHINE_TYPE_NAME("realview-pbx-a9"),
 438    .parent = TYPE_MACHINE,
 439    .class_init = realview_pbx_a9_class_init,
 440};
 441
 442static void realview_machine_init(void)
 443{
 444    type_register_static(&realview_eb_type);
 445    type_register_static(&realview_eb_mpcore_type);
 446    type_register_static(&realview_pb_a8_type);
 447    type_register_static(&realview_pbx_a9_type);
 448}
 449
 450type_init(realview_machine_init)
 451